1 chemical engineering tools for semiconductor fabrication david cohen, phd aiche norcal symposium...
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Chemical Engineering Tools for Semiconductor Fabrication
Chemical Engineering Tools for Semiconductor Fabrication
David Cohen, PhDAIChE Norcal Symposium
April 12, 2005
David Cohen, PhDAIChE Norcal Symposium
April 12, 2005
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Integrated CircuitIntegrated Circuit
Courtesy of Integrated Circuit Engineering (ICE)
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Moore’s LawMoore’s Law
Courtesy of Intel
Number of Transistors per Integrated Circuit
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Chemical Unit OperationsChemical Unit Operations
SABRE xT
ALTUS
INTERCONNECT
VIA
CONTACT
INOVA xT
METALS
STI
SPEED
ILD/PMD
PASSIVATION
IMD
BARRIER/ARL
VECTOR
DIELECTRICS
SEQUEL
FEATURE SIZE
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Example of Chemical Process - ElectroplatingExample of Chemical Process - Electroplating
Electrofill
Cu Anode
Cathode (Wafer)
Cu0 (solid) = Cu+2(aq) + 2e-
Cu+2(aq) + 2e- = Cu0 (solid)
CuSO4 Electrolyte
Novellus Sabre
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Example of Chemical Process - CVDExample of Chemical Process - CVD
Heater Block
Shower Head
SiN
RF Plasma
SiH4, NH3 and N2
Optional RF Bias
RFPower PECVD
Novellus Vector
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Plasmas TodayPlasmas Today
PECVDPlasmas have played vital role in: Physical Vapor Deposition Plasma Enhanced Chemical
Vapor Deposition (right) Etching Cleaning Passivation Plasma sources of UV
radiation for lithography
Plasmas have played vital role in: Physical Vapor Deposition Plasma Enhanced Chemical
Vapor Deposition (right) Etching Cleaning Passivation Plasma sources of UV
radiation for lithography
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Future Limitations of PlasmasFuture Limitations of Plasmas
Extreme selectivity required for advanced applications.• Need to produce desired plasma chemical
reactions and prevent undesirable ones.• The ability to tailor the energy distributions
of plasma particles is key to this selectivity.
As feature sizes get smaller, plasma energy requirements get larger.
Need to enhance models to fully couple reactor scale to feature scale.
Extreme selectivity required for advanced applications.• Need to produce desired plasma chemical
reactions and prevent undesirable ones.• The ability to tailor the energy distributions
of plasma particles is key to this selectivity.
As feature sizes get smaller, plasma energy requirements get larger.
Need to enhance models to fully couple reactor scale to feature scale.
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Atomic Layer DepositionAtomic Layer Deposition
Surface controlled, layer by layer deposition method
Surface controlled, layer by layer deposition method
ALD Group, Univ of Colorado
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Quantum Chemistry ModelingQuantum Chemistry Modeling
Predict surface reactions to understand ALD Challenge coupling reactor scale flow behavior with surface
chemistry Ability to model is limited by computational power because of
extreme complexity of film growth chemistry
Predict surface reactions to understand ALD Challenge coupling reactor scale flow behavior with surface
chemistry Ability to model is limited by computational power because of
extreme complexity of film growth chemistry
Collin Mui, Novellus Systems
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Moving to Low-kMoving to Low-k
As features become smaller, reduced capacitance is necessary to increase IC clock speed
Reduction in dielectric constant (k)
SiO2 is primary insulator – k=4.0
Need to get down to k<2.0
As features become smaller, reduced capacitance is necessary to increase IC clock speed
Reduction in dielectric constant (k)
SiO2 is primary insulator – k=4.0
Need to get down to k<2.0
Material Dielectric Constant
Deposition Method
FSG (Fluorinated Silicate Glass) 3.4-3.8 CVD Polyimides 3.0-3.5 Spin-on DLC (Diamond-Like Carbon) 2.8-3.0 CVD SOG (Spin-On Glass) 2.7-3.1 Spin-on
Siloxanes 2.7-2.9 Spin-on Poly(arylene ethers) 2.6-2.9 Spin-on Fluorinated Polyimides 2.5-3.3 Spin-on C-doped Oxide 2.5-2.9 CVD
PTFE ? 2.0 Spin-on Nanoporous Silica ? 2.0 Spin-on Nanoporous Organic ? 2.0 Spin-on
Mesoporous Silica 1.9-2.2 Supercritical CO2 Silica Xerogels 1.5-2.2 Spin-on Silica Aerogels 1.1-2.2 Spin-on
Air Gap 1.0 TBD
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Challenges of Low-kChallenges of Low-k
0
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Porosity
Die
lectr
ic C
on
sta
nt
SiO2
SiN
Porosity increases with decreasing dielectric constant (k)
Thermal Conductivity Mechanical Strength
(CMP, bonding, packaging) Pore Size
• killer pore (< 10% CD)• need for CVD barrier• CVD barrier increases
effective k
Porosity increases with decreasing dielectric constant (k)
Thermal Conductivity Mechanical Strength
(CMP, bonding, packaging) Pore Size
• killer pore (< 10% CD)• need for CVD barrier• CVD barrier increases
effective k
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Chemical Mechanical PlanarizationChemical Mechanical Planarization
Removes surface textures and allows multiple interconnect layers to be used
Removes excess material
Removes surface textures and allows multiple interconnect layers to be used
Removes excess material
Novellus XcedaCourtesy of Alpsitec
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CMP ChallengesCMP Challenges
Pressure of CMP Pad results in dishing of soft materials or damage of low-k films
Pressure of CMP Pad results in dishing of soft materials or damage of low-k films
Need to provide better polishing control• Chemistry of CMP slurries will drive more uniform
polish• Chemical polish can replace mechanical force
Uniformity prediction relies on development of model that takes into account pad motion, fluid-structure interaction, and removal rate
Need to provide better polishing control• Chemistry of CMP slurries will drive more uniform
polish• Chemical polish can replace mechanical force
Uniformity prediction relies on development of model that takes into account pad motion, fluid-structure interaction, and removal rate
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Electroplating ModelingElectroplating Modeling
Need to include:• turbulent/rotating flow• mass transfer• electrical current flow• terminal effect (electrical current flow in the seed layer)• Chemistry – not well understood
Need to include:• turbulent/rotating flow• mass transfer• electrical current flow• terminal effect (electrical current flow in the seed layer)• Chemistry – not well understood
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Use of Electroplating ModelsUse of Electroplating Models
Model can be used to test various additive chemistries for Cu electroplating
Model can be used to test various additive chemistries for Cu electroplating
Larry Gochberg, Novellus Systems
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Effluent ManagementEffluent Management
On-site abatement necessary to minimize environmental impact of IC manufacturing
Gas phase emissions• Hazardous Air Pollutants (HAPs)• Volatile Organic Compounds (VOCs)• Ozone Depleting Substances (ODSs)• Perfluorinated Compounds (PFCs)
Liquid phase emissions• Suspended solids• Phosphates, Nitrates• Organics• Transition Metals• pH, Temperature, etc.
On-site abatement necessary to minimize environmental impact of IC manufacturing
Gas phase emissions• Hazardous Air Pollutants (HAPs)• Volatile Organic Compounds (VOCs)• Ozone Depleting Substances (ODSs)• Perfluorinated Compounds (PFCs)
Liquid phase emissions• Suspended solids• Phosphates, Nitrates• Organics• Transition Metals• pH, Temperature, etc.
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SummarySummary
There are a number of chemical unit operations involved in IC manufacture.
Feature size has evolved to below 100 nm. New technologies will be required to keep
reducing IC feature size. Modeling enhancements are needed to better
understand plasma, electroplating, CMP, ALD. Advances in semiconductor manufacture need to
include emission control and energy reduction.
There are a number of chemical unit operations involved in IC manufacture.
Feature size has evolved to below 100 nm. New technologies will be required to keep
reducing IC feature size. Modeling enhancements are needed to better
understand plasma, electroplating, CMP, ALD. Advances in semiconductor manufacture need to
include emission control and energy reduction.