1 carnegie mellon university center for silicon system implementation an architectural exploration...
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Carnegie Mellon University Center for Silicon System Implementation1
An Architectural Exploration of Via Patterned Gate Arrays
An Architectural Exploration of Via Patterned Gate Arrays
Chetan Patel, Anthony Cozzie, Herman Schmit, Larry Pileggi
Center for Silicon Systems Implementation Carnegie Mellon University
Carnegie Mellon University Center for Silicon System Implementation2
OutlineOutline
Overview of VPGA Exploring the area between ASICs and Programmable ICs.
CLB exploration of Look-Up Table sizes Area Model Delay Model Results
Interconnect exploration Switch Block Crossbar Results
Conclusion
Carnegie Mellon University Center for Silicon System Implementation3
The future of ASIC designs?The future of ASIC designs?
eFPGA ICCAD 2002
Carnegie Mellon University Center for Silicon System Implementation4
Manufacturability issuesManufacturability issues
Becoming more difficult to anticipate all potential failures Cannot simply increase design rules to prevent all possible manufacturing
failures
As optical wavelengths approach critical distances, problems arise with the physical geometries Manufacturability and timing are greatly affected by process variations
130 nm lithography without optical proximity correction
IBM Corp
Carnegie Mellon University Center for Silicon System Implementation5
Programmable ICsProgrammable ICs
Programmable ICs combat the problem facing ASICs by offering numerous advantages Regular geometrical patterns Predictability Built-in testability Reprogrammability
With advantages comes critical disadvantages
Lower performance
Higher power
Larger chip area
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New Circuit FabricsNew Circuit Fabrics
VPGA attempts to explore the middle ground between ASICs and FPGAs:
FPGA
FPGA
FPGAASIC
NewRegular Logic
Fabrics
Leverages the regularity and predictability of FPGAs with the performance and power consumption of an ASIC Regular patterns for address the issues facing manufacturability Regular logic blocks allow predictability in timing and power
Prefabrication of wafers up to Metal 2 Allows for shared mask costs across an application domain
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VPGAVPGA
Via Patterned Gate Array Regular logic blocks that are via
configurable Wafers prefabricated up to Metal 2 layer and
customization done during BEOL (back end of line) manufacturing
Regular power distribution and clock like an FPGA
Fixed regular interconnect architecture Talk primarily aims at what determining
the composition of the CLB and also the fixed interconnect architecture
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Architectural DecisionsArchitectural Decisions
Look-Up Table Experiment Architecture of VPGA very similar to that of an FPGA
(regular logic blocks connected by a fixed interconnect architecture)
Because of these similarites, reconstruct LUT size experiments conducted on FPGAs
Using a simple CLB configuration, replace the FPGA components with their VPGA counterparts
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Experimental FlowExperimental Flow
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LUT Area ModelLUT Area Model
Assume each LUT is a k-1 level tree with complimentary pull up and pull down network Each of the leaf nodes can connect directly to
VDD, ground, or another kth input or its compliment
Area model must account for customization Customization done between Metal 2 and
Metal 3 layers Extra area required for local interconnect
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LUT Delay ModelLUT Delay Model
To keep consistency with Area Model, all transistors were minimum size
Using ST’s 0.13 m technology, we simulated each of the LUTs in HSPICE
Each LUT configured to perform NAND function for ease of testing
Carnegie Mellon University Center for Silicon System Implementation13
CLB Area/Delay ModelCLB Area/Delay Model
The CLB area must also include the area taken up by the I/O buffers as well as the DFF.
3 LUT 4 LUT 5 LUT
LUT area (m2) 45.02 113.36 260.70
LUT delay (ps) 88.70 118.60 152.60
CLB area (m2) 125.18 207.04 369.45
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ResultsResults
LUT size vs. Critical path and Total Area
0
1
2
3
4
5
6
7
8
3 4 5
LUT s ize
del
ay (
ns)
0
100000
200000
300000
400000
500000
600000
700000
800000
Are
a (
m
2)
Critical path
Area
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LUT size conclusionsLUT size conclusions
LUT size of 4 superior in terms of Total area and also critical path delay
LUT size of 3 is comparable to a 4 LUT in terms of critical path delay May warrant further investigation about which LUT is
more beneficial in terms of a heterogeneous CLB
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Interconnect StructuresInterconnect Structures
Determine an interconnect structure suitable for VPGA that sits atop CLB
Can use vpr to model the interconnect with slight variations
VPGA
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Switch Block architectureSwitch Block architecture
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Crossbar architectureCrossbar architecture
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TradeoffsTradeoffs
Routing architecture constrained to fit atop CLB
Switch block architecture much large and less dense than crossbar
Crossbar architecture has extra vias to segment wires
Crossbar architecture also has dangling capacitance problem
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Experimental FlowExperimental Flow
Carnegie Mellon University Center for Silicon System Implementation21
ResultsResults
LUT size vs. Critical path
0
1
2
3
4
5
6
7
8
9
10
3 4 5
LUT s ize
Cri
tica
l pat
h (
ns)
Switch Block
Crossbar
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LUT size vs. Average channel width
0
2
4
6
8
10
12
3 4 5
LUT size
Ch
ann
el w
idth
Switch Block
Crossbar
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ConclusionsConclusions
Switch Block architecture superior in terms of critical path Crossbar architecture travels through many more vias Vias add up with large fan-out nets
Crossbar architecture benefits Increase flexibility which allows less routing tracks Increased density also allows for more available tracks then
then Switch Block May be useful when routing congestion is a problem May improve delay in crossbar architecture by segmenting
wires, thus longer wires pass through less vias