1 at-speed bisr analyzer for embedded word-oriented memories xiaogang du sudhakar m. reddy ece...
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At-Speed BISR Analyzer for Embedded Word-Oriented Memories
Xiaogang DuSudhakar M. Reddy
ECE Department University of Iowa
17th International Conference on VLSI Design (VLSID2004)
Wu-Tung ChengJoseph Rayhawk
Nilanjan Mukherjee
Mentor Graphics Corporation
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Reference
A BISR Analyzer (CRESTA) for embedded DRAMs T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada H. Hidaka
ITC 2000
BIST for Deep Submicron ASIC Memories with High Performance Application
T.J. Powell, W.T. Cheng, J. Rayhawk, O. Samman, P. Policke, S. Lai
ITC 2003
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Outline
What’s CRESTA ? What’s new ? Hardware Implement Conclusion
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CRESTA
IntroductionExample SimulationHardware ArchitectureAdv. & Disadv.
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Introduction
CRESTA = Comprehensive Real-time Exhaustive Search Test and Analysis
At-Speed Multiple sub-analyzers try different order of
spare rows/columns concurrently Detection Ability can become 100% Save address to repair by CAM
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Algorithm
During Memory BIST (for each Sub-analyzer n): If (Fail == 1) If ((Column_Addr not in CAM_C) && (Row_Addr not in CAM_R)) If (No more spare resouce) UnSuc[n] == 1 Else if (current spare resouce == row) CAM_R_cur = Row_Addr Point to next spare resouce Else if (current spare resouce == column) CAM_C_cur = Column_Addr Point to next spare resouce
Post Memory BIST: If (UnSuc != all ‘1’) Repairable, choose one of result that UnSuc[n] == 0 as your strategy Else Unrepairable
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Example
5 x 5 Memory array 2 spare column 2 spare row 6 type BISR strategies
RRCC, RCRC, RCCRCRRC, CRCR, CCRR
1
3
2
8
4
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Sequence of Repair Analysis
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3
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3
2
8
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3
2
8
4
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3
2
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2
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1. R-R-C-C 2. R-C-R-C 3. R-C-C-R
4. C-R-R-C 5. C-R-C-R 6. C-C-R-R
R RR R R R
R R R R RR
C C CC C C
CC CC C C
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FSM of Sub-analyzer
R1
Start
C2
UnSuc C1
R2[0]
[2][3]
[1]
[4] [2][3]
[2][3]
[2][3]
[1][2]
[0]
[0]
[0]
[0][4]
[4]
[2]
[0] Initialize[1] Fail[2] Pass[3] Fail & Match[4] Fail & Mismatch
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Architecture
CAM Array(Row)
CAM Array(Column)
L10
L11
L12
L13
Unsuc1
Fail
Row Address
Column Address
UnSuc
FSM
WE
WE
。。。
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Adv & Disadv
Advantage:At-Speed, shorter test cycleNeed not to store fail addressArea overhead only 1%
Disadvantage:Dramatically increase area overhead with the
number of sparesOnly can deal with bit-oriented memory
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Proposed Algorithm
Algorithm for Linear MemoryExample SimulationModify for Multiplexed Memory
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Linear Architecture
Address width = 6 Word width = 4 Multiple Faults in a
word cannot be achieved in one cycle
Column Repair Vector (CRV)
D0 D1 D2 D3
0 A0 A0 A0 A0
1 A1 A1 A1 A1
2 A2 A2 A2 A2
63 A63 A63 A63 A63
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Algorithm
During Memory BIST: If (Fail_Map != 0) If ((Fail_Map not in CRV) && (Row_Addr not in Spare_Rows)) If (No more spare resouce) unrepairable Else if (current spare resouce == row) Spare_Row = Row_Addr Point to next spare resouce Else if (current spare resouce == column) CRV = CRV | Fail_Map Point to next spare resouce
Post Memory BIST: If ((!unrepairable) && (# of 1 in CRV <= # of spare column)) Repairable Else Unrepairable
Fail_Map = Fault Signature
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Example of C-C-R-R
C-C-R-RRC C
1
2 2 2
3 3 3
1
0 0 0 0 0
0 0 0 0 01 1 11 1
1 11 1 1
CRV
Fail_Map
# of 1 in CRV == 5 > 2Unrepairable !!
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Example of C-R-R-C
C-R-R-CRRC C
1
2 2 2
3 3 3
1
0 0 0 0 0
0 0 0 0 01 1 11 1
1 1
CRV
Fail_Map
# of 1 in CRV == 2 <= 2Repairable !!
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Multiplexed Architecture
Address width = 6 Word width = 2 MUX-level = 2 Row address = Addr
ess/MUX-level Column address = A
ddress%MUX-level Designed for avoid i
ntra-word coupling fault
D0 D0 D1 D1
0 A0 A1 A0 A1
1 A2 A3 A2 A3
2 A4 A5 A4 A5
31 A62 A63 A62 A63
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Modification for Multiplexed Architecture
Method 1 Size of CRV = the # of bits in a row Use the same algorithm in linear architecture Area overhead is too large
Method 2 Several word-size of CRVs as W-CRVs Size of W-CRV = word size + length of MUX-level # of W-CRVs = # of spare columns Not only Compare with Column address but also MU
X-level
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Examples(1)
0 1 0 1
0 0000 0010
1
2 0000 0100
3
1 0 0 0 0 0 1 1 0
0 0 0 0 0 0 0 0 0
MUX-level
CRV
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Examples(2)
0 1 0 1
0
1 0000 0010
2
3 0100 0000
1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0
MUX-level
CRV
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Hardware
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Architecture of BIST & BISRA
BIST Controller
Memory
BISRA Controller
Pass / Fail
Repair Data
Repairable
Restart
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R/W Operation with MBIST Full-Speed
SetupRead 1
SetupWrite 1
SetupRead 2
SetupWrite 2
SetupRead 3
Read 1 Write 1 Read 2 Write 2
CompareRead 1
CompareRead 2
Pass/FailRead 1
Pass/FailRead 2
ClockCycle 1
ClockCycle 1
ClockCycle 1
ClockCycle 1
ClockCycle 1
Clock
Addr / CtrlData
Memory
CompareCircuitry
Output
。。。
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MBIST Full-Speed Controller
FSM
Compare Capture
Reference Data
Con-trol
DataAdd-ress
CompareUnit
Memory
Logic Logic
Pass / Fail
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BISRA Controller with C(m+n, m) Engines
Arbiter
SRA CAR
SRA CAR
BISRA Engine
BISRA Engine
Fail_Map
Address
Spare Resource Allocation
Control and
Report
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BISRA Controller with 1 Engine
SRA CAR
BISRA Engine
Repair Strategy
Reconfiguration(RSR)
Fail_Map
Address
Restart
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Reconfigure the Repair Strategy by LFSR
By using LFSR “1” == Spare Row, “0” == Spare Column 1001→1010 → 0101 → 1100 → 0110 → 0011
Spare Resources
Strategy Polynomial
Initial Strategy
1R1C 1+x2 10
1R2C 1+x3 100
2R1C 1+x3 110
2R2C 1+x+x2+x4 1001
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Repair Strategy Selection Algorithm
R
R
R
R R R
RR
R
C
C
C
C C
C
C
C
C
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Experiment Result
TI TMS320C6414T with 90 nm tech. 3 controller, each with 7k to 8.5k gate 10% faster than normal functional frequency to
detect performance related defect
Controller #1 Controller #2 Controller #3
Memories 22 single port 31 single port 32 single port
Repair No Yes Yes
Mem Length 80 – 1024 128 – 1024 8192
Data Width 32 – 64 6 – 42 32
Clock Freq. 400 MHz 800 MHz 800 MHz
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Conclusion
Proposed a at-speed BISRA algorithms for word-oriented memories
By modifying the CRESTA and by using CRV, multiple-failure in a word can handle at speed.
Single or multiple repair engine for trade off. Repair strategies can either be generated by an
on-chip LFSR or by an external ATE A branch and bound repair strategy selection
algorithm to reduce repair time