1

Arithmetic, ALUsArithmetic, ALUs

Lecture 9Digital Design and Computer Architecture

Harris & HarrisMorgan Kaufmann / Elsevier, 2007

2

1-Bit Adders1-Bit Adders

HalfAdder

A B

S

Cout +

FullAdder

A B

S

Cout Cin+

3

Multi-bit AdderMulti-bit Adder

A B

S

Cout Cin+N

NN

4

Ripple-carry AdderRipple-carry Adder

S31

A30 B30

S30

A1 B1

S1

A0 B0

S0

C30 C29 C1 C0

Cout ++++

A31 B31

Cin

5

SubtractorSubtractor

+

A B

-

Y Y

A B

NN

N

N N

N

N

6

Comparator: EqualityComparator: Equality

A3

B3

A2

B2

A1

B1

A0

B0

Equal=

A B

Equal

44

7

Comparator: Less ThanComparator: Less Than

A < B

-

BA

[N-1]

N

N N

8

Arithmetic Logic Unit (ALU)Arithmetic Logic Unit (ALU)

ALU

N N

N

3

A B

Y

F

F2:0 Function

000 A & B

001 A | B

010 A + B

011 not used

100 A & B

101 A | ~B

110 A - B

111 SLT

9

ALU DesignALU Design

+

2 01

A B

Cout

Y

3

01

F2

F1:0

[N-1] S

NN

N

N

N NNN

N

2

Ze

roE

xtend

10

ALU FunctionALU Function

+

2 01

A B

Cout

Y

3

01

F2

F1:0

[N-1] S

NN

N

N

N NNN

N

2

Ze

roE

xtend

F2:0 Function

000 A & B

001 A | B

010 A + B

011 not used

100 A & B

101 A | ~B

110 A - B

111 SLT

11

Set Less Than (SLT)Set Less Than (SLT)

+

2 01

A B

Cout

Y

3

01

F2

F1:0

[N-1] S

NN

N

N

N NNN

N

2

Ze

roE

xtend

12

ShiftersShifters• Logical shifter: shifts value to left or right and fills empty

spaces with 0’s

• Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb).

• Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end

13

Shifter DesignShifter Design

A3:0 Y3:0

shamt1:0

>>

2

4 4

A3 A2 A1 A0

Y3

Y2

Y1

Y0

shamt1:0

00

01

10

11

S1:0

S1:0

S1:0

S1:0

00

01

10

11

00

01

10

11

00

01

10

11

2

14

ExampleExample

Write verilog code to implement the following

function in hardware:

y = b’c’ + ab’

Name the module “sillyfunction”.

15

TestbenchesTestbenches

• Verilog code written to test other verilog modules

• Not synthesizeable

16

Simple TestbenchSimple Testbenchmodule testbench1();

reg a, b, c;

wire y;

// instantiate device under test

sillyfunction dut(a, b, c, y);

// apply inputs one at a time

initial begin

a = 0; b = 0; c = 0; #10;

c = 1; #10;

b = 1; c = 0; #10;

c = 1; #10;

a = 1; b = 0; c = 0; #10;

c = 1; #10;

b = 1; c = 0; #10;

c = 1; #10;

end

endmodule

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Self-checking TestbenchSelf-checking Testbenchmodule testbench2();

reg a, b, c;

wire y;

// instantiate device under test

sillyfunction dut(a, b, c, y);

// apply inputs one at a time

// checking results

initial begin

a = 0; b = 0; c = 0; #10;

if (y !== 1) $display("000 failed.");

c = 1; #10;

if (y !== 0) $display("001 failed.");

b = 1; c = 0; #10;

if (y !== 0) $display("010 failed.");

c = 1; #10;

if (y !== 0) $display("011 failed.");

18

Self-checking Testbench (cont.)Self-checking Testbench (cont.)

a = 1; b = 0; c = 0; #10;

if (y !== 1) $display("100 failed.");

c = 1; #10;

if (y !== 1) $display("101 failed.");

b = 1; c = 0; #10;

if (y !== 0) $display("110 failed.");

c = 1; #10;

if (y !== 0) $display("111 failed.");

end

endmodule

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Testbench with TestvectorsTestbench with Testvectors

• Write testvectors file• Testbench:

1. Generates clock for assigning inputs, reading outputs

2. Reads testvectors file into array

3. Assigns inputs, expected outputs

4. Compares outputs to expected outputs and reports errors

20

Testvectors FileTestvectors File

File: example.tv

000_1

001_0

010_0

011_0

100_1

101_1

110_0

111_0

21

Testbench: 1. Generate ClockTestbench: 1. Generate Clock

module testbench3();

reg clk, reset;

reg a, b, c, yexpected;

wire y;

reg [31:0] vectornum, errors;

reg [3:0] testvectors[10000:0];

// instantiate device under test

sillyfunction dut(a, b, c, y);

// generate clock

always

begin

clk = 1; #5; clk = 0; #5;

end

22

2. Read Testvectors into Array2. Read Testvectors into Array

// at start of test, load vectors

// and pulse reset

initial

begin

$readmemb("example.tv", testvectors);

vectornum = 0; errors = 0;

reset = 1; #27; reset = 0;

end

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3. Assign Inputs, Expected Outputs3. Assign Inputs, Expected Outputs

// apply test vectors on rising edge of clk

always @(posedge clk)

begin

#1; {a, b, c, yexpected} =

testvectors[vectornum];

end

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4. Compare Outputs with Expected4. Compare Outputs with Expected// check results on falling edge of clk

always @(negedge clk)

if (~reset) begin // skip during reset

if (y !== yexpected) begin

$display("Error: inputs = %b",

{a, b, c});

$display(" outputs = %b (%b expected)",

y, yexpected);

errors = errors + 1;

end

vectornum = vectornum + 1;

if (testvectors[vectornum] === 4'bx) begin

$display("%d tests completed with %d errors",

vectornum, errors);

$finish;

end

end

endmodule

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