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Analog Leaf Cell (ALC) Group

Advisor: Prof. David Parent

Taslima RahmanMariavanessa Pascua

Siu Kuen LeungKuang-Wai (Kenneth) Tseng

Scott Echols

12/02/2005

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What is our project??

Designing a teaching environment targeted to all EE students

Implementing Super MOSWriting up tutorials

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Outline Problem Objective Skillsets Block Diagram Previous Work Schedule Resources & Cost Targeted Audience Preliminary work Conclusion

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Problem

Not all EE students have the hands-on experience of an IC design, fabrication, & testing flow

EE students need to be better prepared to compete for jobs in the global economy

Learning the IC design flow is time consuming

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Objective

Providing Analog Leaf Cell Environment Semi-custom design

approach for EE124 Reduction of learning and

fabrication time

Prepare all EE students Compete for jobs in a

global economy Require less on the job

training

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Skillsets

The Skills that we need to implement our project

EE129, EE166, AND EE124

EE129 (Introduction to IC Processing)EE166 (Design of CMOS Digital Integrated

Circuit)EE124 (Microelectronic Design II)

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Block DiagramProcess Steps to Implement our Project

DESIGN(State of the art

CAD tool)

TEST(TEST DEVICES ON WAFER IN

FAB LAB)

WRITE UP TUTORIALS(SET UP A MINI LAB

MANUAL FOR EE124 AND EE129)

PROCESS(FABRICATE

WAFER IN FAB LAB)

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Previous Work

1999 no Custom IC resources From 2001 to 2005-(only selected students)From 2005 to future-(all EE students)Fundamental to SJSU EE Students.

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Schedule

ID Task NameSep 2005 Oct 2005 Nov 2005 Dec 2005 Jan 2006 Feb 2006 Mar 2006 Apr 20069/4 9/11 9/18 9/25 10/2 10/9 10/16 10/23 10/30 11/6 11/13 11/20 11/27 12/4 12/11 12/18 12/25 1/1 1/8 1/15 1/22 1/29 2/5 2/12 2/19 2/26 3/5 3/12 3/19 3/26 4/2 4/9 4/16 4/23

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9/30/200522dResearch

1/26/200684dDesign & Simulation

11/30/200515dWafer Test Bench Set Up

1/26/200631dFabrication Mask1 to Mask3

2/20/200618dWafer Fabrication Mask4

3/10/200614dProcess Wafer Testing

3/20/20067dDesign Adjustment

3/30/20069dWafer Fabrication Mask4

3/30/20069dProcess Wafer Testing

5/1/200623dDocumenting

Duration Finish Date

% Completed

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Resources and Cost

ResourcesFabrication LabCadence LabAdvisor – Dr. Parent

Cost Using Fabrication and Cadence Lab ($100 per hour)

FREE!Mask ($650) FREE!Dr Parent Advising ($100 per hour) FREE!Group Working hours ($150 per hour)Total Cost = $ 0 ??

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Targeted Audience

All EE StudentsPotential EE students, transfer students,

high school students

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Preliminary WorkCurrent Mirror schematic

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Preliminary Work

Super MOS schematic

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Preliminary WorkCurrent Mirror

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Preliminary WorkSuper MOS

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Conclusion

Several devices will be designed, fabricated, and tested using the ALC template.

Simulations using the Cadence lab will be used to verify correct design flow.

The fabrication lab will be used to manufacture and test the devices.

The devices will be used to aid graduate students for MEMS research and may also lead to further undergraduate projects.