1 a monolithic low-bandwidth jitter- cleaning pll with hitless switching for sonet/sdh clock...
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A Monolithic Low-Bandwidth Jitter-Cleaning PLL with Hitless Switching
for SONET/SDH Clock Generation
D. Wei, Y. Huang, B. Garlepp and J. Hein
Silicon Laboratories Inc., Austin, Texas
Presented in ISSCC, Feb, 2006
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New Breed of Analog Designers: digAnalog
• Requirement for analog interface is higher and higher (i.e. multimedia application), yet technology advancement shies away from the analog performance– Example: 1/f noise, gate leakage, device non-ideality
• Digital signal processing is so powerful today!– Deep sub-micron CMOS– More computation power for limited-size area
• Integration is the trend– Consumer electronics require compactness– Delicate process means higher ASP and lower revenues
Q: can we enhance the “analog” performance by the power of “digital”?
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Insights of Analog-to-digital Interface
Sig (analog)
D0
D1
D2
D3
D4
D5
D6
D7
Ts 1-to-1 digital-to-analog mappingè DD is still analogè trade the speed with accuracyè Nyquest Rate ADC
Go against the technology trend
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Insights of Analog-to-digital Interface (con’t)
D0
D1
D2
D3
D4
D5
D6
D7
`
Ts
Sig (analog)
Sig is the “moving average” of Doutè Each individual Dn does not matter any moreè analog errors (DD) are less emphasizedè trade accuracy with speedè Sigma-delat ADC
Demand faster technology but with less accuracy!
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digAnalog Design Rules
• Good understanding of the system requirements– “To dig or not to dig, that is the question”
• Pick the right “candidate” (voltage, current, flux, phase, …) to process– What defines your “signal”?
• Faster technology available (and cheap!)– signal bandwidth vs. sampling clock
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Example: Switch References in PLL
Synthesizer
A (system clk)
D1 D2 D3 D4 D5D0 high speed serial data link
B (local osc.)
Output CLK
Q: How can we switch the input reference without causing ouptut CLK phase to move?
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What should I digitize?
V(t)
F(t)
F(t)
Continuous, physical element, high speed
Discrete, physical element, low speed
Continuous, abstract element, high speed (burst)
zero-crossing time stamp
Math derivative
Energy signature
Oscillator
“amplitude”
“phase”
“frequency”
è Phase detector output can realistically digitized!
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SONET/SDH Clock Management
100% Redundancy is required at the line-card timing reference
Ultimate Timing Source
BITS CLOCK
Timing Card
Backplane
jitter2
jitter1
FPGA
CMU
TX
19M/155M/622M
Line Card
8KHz19.44MHz
Timing Card
Optical Link
CLK A
CLK B
Delay1
Delay2
OC48: 2.488Gb/sOC192: 9.95Gb/s
switch
Low BWPLL
data
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Type-II PLL Phase Transient During Reference-switching
• Dmax : maximum phase deviation• t : maximum phase step slope
DintCLKA(t)
CLKB(t)
D(t) + noise
t
0
Din
PFDLoop Filter
VCO
/N
Divider
Sel A
Sel B
Type-II PLL
t
Dt
Dout Dmax
t
200
2
20
2)(
sssH
10
Maximum Time Interval Error (MTIE)
Phase Offset (25.7ns max)
Frequency Offset (9.2ppm max)
Typical LBW choice: 250Hz (clk rearrangement) ~ 1KHz( frequency translation)
slope < 81ns/1.326ms
Din
DoutPha
se
Time
max(outtt) = DIn x 2p x LBW
Dout
Pha
se
Time
maxDerror)= Mramp/(2p x LBW)
Mramp (sec/sec)
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“Hitless” Phase-Switching Architecture
t=t1, selA=1 / selB=0 A- offsetA,0 = out,1, offsetB,1 = B
t=t2, selA=0 / selB=1 B- offsetB,1 = out,2, offsetA,2 = A
Dout,1,2 = (A-B)-(offsetA,0-offsetB,1) = 0 if A and B ~ constant
out
Z-1
Loop Filter
selA
selB
+
+
-
-
+
+
DSPLL (Digital)
off
setA
off
setB
A
VCO
AnalogAnalog
Z-1
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Digital Implementation of Hitless Switching (1)
AZ
PFDA CP
Offset DACA 6
311MHz
1
4
FB DAC
PFDB CP
AZOffset DACB 6
311MHz
1
4
PFD ADCFB DAC
A/B
DLF4 VCO20
/M
2swalA
Swallow Control
2swalB
swallow divider
swalB 2
swallow divider
swalA 2
2.5GHz
17/16/15
17/16/15
swalB2
fdbk, A
fdbk, B
ref, A
ref, B
SWA
SWB
swalA2
Swallow Control
CLKdiv
311MHz
CLKdiv
311MHz
CLK A19.44MHz
CLK B19.44MHz
4
4
/8
PLL LBW < 12KHz PFD DADC fs = 311MHz
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PFD ADC and Auto-zero Loop
Loop Bandwidth < 12KHz vs. DADC fs = 311MHz SNR > 22bits PFD full scale = 6.42ns Offset DAC LSB ~ 100ps
AutoZero (AZ)
AZ
PFD
Offset DAC 7
311MHz
1
4swal
2
Ref. Clk4
Fdbk Clk
D1bit ADC
FB DAC
Accum.117
G7
4
+D-D
72swal
“shift” the offset DAC value AZ bandwidth ~ 100KHz D avoids the DAC overflow
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What if Frequency Error Is Present?
/8
/15, /16, /17
VCO
D D D D
PFDSwallowControl
RefClk
d2
d2
/15 pulse
/17 pulse
-FSPD
+FSPDTime
D
A-B
k=0 k=1 k=7
25.7ns
FSPD= 3.21ns
offsetA-offsetB
D
D
RefClk
2.488GHz 311MHz
Dout,1,2 = (A-B) - (offsetA-offsetB) – k (0.5 2FSPD)
8FSP
D
Doffset,max =FSPD modulus (k=0~7)
2FSPD: Phase Detector Full-scale (6.42ns)
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Digital Implementation of Hitless Switching (2)
Each swallow: TD = 8Tvco
AZ
PFDA CP
Offset DACA 6
311MHz
1
4
FB DAC
PFDB CP
AZOffset DACB 6
311MHz
1
4
FB DAC
A/B
DLF4 VCO20
/M
2swalA
Swallow Control
2swalB
swallow divider
swalB2
swallow divider
swalA2
2.5GHz
17/16/15
17/16/15
swalB 2
fdbk, A
fdbk, B
ref, A
ref, B
SWA
SWB
swalA 2
Swallow Control
CLKdiv
311MHz
CLKdiv
311MHz
CLK A19.44MHz
CLK B19.44MHz
4
4
/8
fdbk, B
ref, B
ref, B
TD
“lag”
swalB = [10]
swalB = [01]
“lead”
Swallow Control
TD
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Phase Transient Measurement Setup
Linear phase detector “demodulates” the DUT output phase LOS (loss-of-signal) on clkB triggers the oscilloscope
Agilent HP8664A
splittersplitter
Linear PD
INPB
INPA
19.44MHz
19.44MHz
trigger
out
Delayline
DUT
clkA out
LOSclkBoscilloscope
adjustable D
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Measured Phase Transient During Reference-switching
Mode: Auto-switching (LOS triggers the switching)
LOSB trigger the switching
Wandering due to LOS
Loop relocks the phase
residual D = 35ps
116ps
Initial D = 180 (~25ns)
PD out
LOSB
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Removing the External Loop Filter
DSP implementation replaces the bulky external loop filters (LF) Less Bill-of-Materials (BOM) Avoid excess noise-coupling at post-LF nodes
FPGA
CMU
TX
19M/155M/622M
Line CardOptical Link
OC48: 2.488Gb/sOC192: 9.95Gb/s
switchLow BW
PLL
data
clkA
clkB
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Package InductorQ ~ 40
FIR Gain
Accum. D
4
46
20
20
6
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Digital Loop Filter (DLF)
m-bit DAC Array + 2n multiplexer
(m + n = 20)
varactor array
Vg
DSP-based Loop Filter Implementation
Gain ratio controls LBW and peaking
No external loop filter components needed
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PLL Bandwidth and Peaking ControlFeedforward (F)
Integration (I)
PFD ADC
feedforward bits added Input bits accumulated
varactor codes Reduced by D (rounding)
KF ~ LBW / (KPD x Kv) KI ~ (LBW)2 x (-1) / (KPD x Kv)
For Type-II PLL with low-peaking (<0.1dB),
FIR Gain
Accum. D
4
46
20
20
6
20DAC
VCO Tank2.488GHz
20 bit ?2V
Kv=75MHz/2Vè Vn = 4nV/sqrt(Hz)?
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DAC Expander
DAC15
DAC15
DAC15
DAC15
DAC15
DAC15
DAC15
DAC15
128 multiplexers
Vg(0)Vg(1)Vg(2)
……
.
Vg(126)Vg(127)
128 sub-varactors
Vref, hi Vref, lo
MUX Control
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Digital Loop Filter
Connecting the Loop Filter to Varactors
2nd-order D generates varactor cntl. voltage
DAC expander reduces the analog hardware cost by 16x
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VCO Varactor Implementation
Fvco
Cvaractor32 segments
75MHz
Vg1 Vg8
4 cells overlapped
VCO Kv reducedsub-varactor C-V linearized
Kv < 1.2MHz / Volt
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
MUXVg
DAC E
MUX (n)
MUX(n+8)
MUX(n+5~127)=0MUX(0~n+1)=Vref
DAC Expander Output(LSB = 2-20)
“0”
Vref =2V
Var
acto
r T
unin
g V
olta
ge
low Fvcohigh Fvco
8 DACs barrel-shifted to minimize the hardwares
q Requires 128 sub-varactors / MUXs
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Varactor DAC and Multiplexer
At any instant, only 8 varactors receive DAC tuning voltages
Varactor DAC (x8)
2nd order D RZ
1
Vref, hi
Vref, loclk
15
posSel
negSel
dacSel
Vref, lo
Vref, hi
Vg
posSel
negSel
dacSel
Vref, lo
Vref, hi
Vg
2nd order D RZ
1
Vref, hi
Vref, loclk
15
Varactor MUX (x128)
DAC A
DAC H
MUX(0)
MUX(127)0
816
120
A
H
dacSel[127:0]posSel[127:0]
negSel[127:0]DAC Expander
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DAC Movement Across Sub-Varactor
DAC D
DAC C
DAC B
Vg
tank
Vg
tank
Vg
tank
Vg
tank
Vg
tank
Vg
tank
Vg
tank
Analog-tuning varactors (8)Railed varactors Grounded varactors
DAC F
DAC G
DAC H
DAC A
Vg,hi = Vref, hiVg,lo = Vref, lo
barrel-shifted
Vg,hi
tank
Vg,hi
tank
Vg,hi
tank
Vg,hi
tank
Vg,lo
tank
Vg,lo
tank
Vg,lo
tank
Vg,lo
tank
DAC E
Vg,hi
tank
Vg
tank
Vg,lo
tank
DAC E
high Fvco low Fvco
Accumulator bits slowly move the DAC banks Feedforward bits vary the tuning voltage Vg
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Chip Micrograph
PFD/ADC B
PFD/ADC F
PFD/ADC A
output drivers
DAC expander
multiplexer
vara
cto
r
master regulator
VCO dividerd
igit
al r
ou
tes
/ re
gu
lato
rs
referencegenerator.
5.1mm
3.5m
m
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Discrete Solution vs. Integrated Solution
No external loop filters are required. dramatically simplifies the line card design!
50mm50
mm
discrete solution
hybrid solution
23mm
23mm
11mm
11mm
presented solution
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PLL Characteristics Measurement
Measured integrated jitter: OC48 band 0.69ps OC192 band 0.26ps
100M10 100 1K 10K 100K 1M 10M
Frequency (Hz)
L(f
) (d
Bc/
Hz)
-20
-40
-60
-80
-100
-120
-140
-160
Phase Noise @ LBW=800Hz622.08MHz Output
-97dBc/Hz@10KHz
-142dBc/Hz@1MHz
Jitter Generation
Measured peaking: < 0.1dB
Frequency (Hz)100 1K 10K
0
-2
-4
-6
-8
-10
-12
-14
-16
Lo
op
Tra
nsf
er (
dB
)
800Hz
1600Hz
3200Hz
6400Hz
Jitter Transfer2
19.44Mhz Input622.08MHz Output
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Performance SummaryTechnology 0.25-CMOS
Die Size 3.5mm by 5.1mm
Package 11 X 11 CBGA
Power @ Vdd=3.3V 350mW
Supported PLL Bandwidth (LBW) 800Hz, 1600Hz, 3200Hz, 6400Hz
Loop Transfer Peaking <0.1dB
During Reference Switch @ BW=800Hz
Maximum Output Phase Step 200ps
Maximum Output Phase Slope (MTIE: <61.08 ns/ms for 3/4E) 4.5 ns/ms
Jitter Generation @ BW=800Hz
OC-48 band (12KHz ~ 20MHz) 0.8ps (WC)
OC-192 band (50KHz ~ 80MHz) 0.4ps (WC)
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Conclusion
• Digital “hitless” clock-switching is demonstrated, enabling the on-chip implementation for SONET/SDH clock management.
• Loop components are digitally implemented, which minimizes the external noise coupling and also has the good control over loop characteristics.
• Concise digital implementation of digital varactors simplifies the hardware implementation, and enhances the VCO performance, enabling the “jitter-cleaning” to the PLL input clocks.
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