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A Fast Algorithm A Fast Algorithm for Power Grid for Power Grid

Design Design Jaskirat SinghJaskirat Singh

Sachin SapatnekarSachin Sapatnekar

Department of Electrical and Computer

Engineering University of Minnesota

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IntroductionIntroduction Power supply networkPower supply network

Provides VDD and ground Provides VDD and ground to time varying current to time varying current sources (logic gates)sources (logic gates)

VDD

GND

Power grid design issuesPower grid design issues VDD , wire width , VDD , wire width ,

currentscurrents IR drop/ground bounceIR drop/ground bounce

Signal integritySignal integrity Gate delayGate delay

ElectromigrationElectromigration Mean failure time for wiresMean failure time for wires

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IntroductionIntroduction

Power grid design problemPower grid design problem Given an estimate of loading currents and Given an estimate of loading currents and

power pad positionspower pad positions Select a set of wire widths and pitches for the Select a set of wire widths and pitches for the

multiple-layer network so thatmultiple-layer network so that Wire area is efficiently utilizedWire area is efficiently utilized Nodes (branches) satisfy voltage drop (current Nodes (branches) satisfy voltage drop (current

density) constraintsdensity) constraints Additional objectives of congestion Additional objectives of congestion

minimization/shieldingminimization/shielding

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IntroductionIntroduction

Power grid design methods

Explicit circuit simulation based method

•Detect and fix method•Accurate Design•Usually slow

Non-linear optimization based method•KCL/KVL part of constraint set•Approximations needed for efficiency•May be inaccurate due to relaxations

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MotivationMotivation Notion of Notion of localitylocality in power grid design in power grid design

““Fast Flip-chip Power Grid Analysis via Fast Flip-chip Power Grid Analysis via Locality and Grid Shell”, Eli Chiprout, Locality and Grid Shell”, Eli Chiprout, ICCAD’04.ICCAD’04.

To construct local grids focus on details of To construct local grids focus on details of local regions. Abstract local regions. Abstract far awayfar away regions of regions of the grid.the grid.

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Locality ExampleLocality Example

10 X 8 Grid10 X 8 Grid

Fix Violation

s Locally

Fix Violation

s Locally

Abstract

away far off grid regio

ns

Abstract

away far off grid regio

ns

Power Grid Abstraction

Each branch 1 ohmEach branch 1 ohm Loaded with 1mALoaded with 1mA

Vspec = 0.9VVspec = 0.9V

VDD pads (1V )VDD pads (1V )

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Locally Regular/Globally Locally Regular/Globally IrregularIrregular

Globally regular gridGlobally regular grid Over design of the gridOver design of the grid

Globally irregular/locally regular gridGlobally irregular/locally regular grid Efficient use of wire area Efficient use of wire area Reduced # of optimizable parametersReduced # of optimizable parameters

High High

Med Low

High High

Med Low

High High

Med Low

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Power Grid Design Power Grid Design ProcedureProcedure

Recursive bipartitioning heuristic based on notion of locality

Abstraction of grids in partitions

Coarse grid representation initially

Post processing step to maximize wire alignment

Divide the chip area into partitions

Design local grids in the partitions

Macromodeling technique by M. Zhao et al, DAC’00

Iterative refinement of grid

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Recursive Bipartitioning Recursive Bipartitioning MethodMethod

Divide and conquerDivide and conquer approachapproach Solve a local power grid design problem in each stepSolve a local power grid design problem in each step

1 2 3

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2k

2K+1

-1

Vertical, horizontal Vertical, horizontal partition wirepartition wire

Active partitionsActive partitions

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Recursive Bipartitioning Recursive Bipartitioning MethodMethod

Level-1 Partition Level-2 Partition

Level-2 PartitionLevel-k Partition

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First level of partitioningFirst level of partitioning

Construct macromodels for the two partitionsConstruct macromodels for the two partitions),( SA

SVAI p

Port Nodes

),( 22 SA),( 11 SA

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First level of partitioningFirst level of partitioning Stamp the macromodels in the global MNA system Stamp the macromodels in the global MNA system Solve each partition by hierarchical analysisSolve each partition by hierarchical analysis For violations in a partition, fix it For violations in a partition, fix it locallylocally

bXM

Speed up in circuit analysis stepSpeed up in circuit analysis step Use very thick wires for initial partition levelsUse very thick wires for initial partition levels In subsequent partition levels In subsequent partition levels refine the gridrefine the grid by reducing the wire by reducing the wire

widthwidth

),( 22 SA ),( 22 SA),( 11 SA bXM

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Second level of Second level of partitioningpartitioning

Rip up the grid in left partitionRip up the grid in left partition Add a horizontal partition wireAdd a horizontal partition wire

Leave the grid in the right partition intact, seen as an abstractionLeave the grid in the right partition intact, seen as an abstraction Construct a refined grid in the top-left and bot-left partitions by theConstruct a refined grid in the top-left and bot-left partitions by the

hierarchical design methodologyhierarchical design methodology

Use the power grid constructed at the first levelUse the power grid constructed at the first level

),( 33 SA

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Second level of Second level of partitioningpartitioning

Requirements for power grid constructed in new active Requirements for power grid constructed in new active partitionspartitions IR drop and EM constraints met in the active partitionsIR drop and EM constraints met in the active partitions Maintain correctness of the power grid in the right partitionMaintain correctness of the power grid in the right partition

Solve new global system M X=bSolve new global system M X=b Compare old and new port voltages of the right partitionCompare old and new port voltages of the right partition If Max( New_port_voltage – Old_port_voltage) > If Max( New_port_voltage – Old_port_voltage) > єє (e.g., 1% VDD) (e.g., 1% VDD)

Power grid in right partition is disturbed Power grid in right partition is disturbed

Add more wires in the active partitions and repeat the design procedure Add more wires in the active partitions and repeat the design procedure

γ

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Make nextpartitions

Decr width by γ

Decr pitch by β

Detect violations

Recursive bipartitioning Recursive bipartitioning algorithmalgorithm

),( 22 SA),( 11 SASolve by hierarchical analysis

Makemacro

Makemacro

Decr width by γ

Make nextpartitions

Check neighbor port voltages

Port voltage change > є ?

Post processing to align wiresDone

Repeat

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Recursive bipartitioning Recursive bipartitioning algorithmalgorithm

A breakdown scenarioA breakdown scenario Min pitch violationMin pitch violation Grid refinement doesn’t Grid refinement doesn’t

workwork

Grids in neighboring Grids in neighboring partitions disturbedpartitions disturbed

Can’t be fixed by adding Can’t be fixed by adding wires in active partitionswires in active partitions

Traverse to the inactive Traverse to the inactive partitions and add more partitions and add more wireswires

Adversely affects the Adversely affects the runtime of the procedureruntime of the procedure

Empirically a rare event if Empirically a rare event if γγ is [ 0.65,1 ) is [ 0.65,1 )

Make_macromodels( );Solve_grid( );If(violations in one or both partitions) Decr wire pitch of violating partition;

Check_neighbor_grids( );If(port nodes of neighbor grids perturbed) Decr wire pitch of active partition;

If (Pitch of the active partition < min_pitch) Min pitch violation;

γ

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Post processing stepPost processing step

At the end of design the wires might be misaligned due to different wire At the end of design the wires might be misaligned due to different wire pitches in adjacent partitionspitches in adjacent partitions

Superimpose a uniform and continuous virtual gridSuperimpose a uniform and continuous virtual grid Pitch of the virtual grid is chosen to be the minimum pitch of all partitionsPitch of the virtual grid is chosen to be the minimum pitch of all partitions Move the real power grid wires to the nearest vacant position on the Move the real power grid wires to the nearest vacant position on the

virtual gridvirtual grid Perform a complete simulation by hierarchical analysis after the wire Perform a complete simulation by hierarchical analysis after the wire

movementsmovements Add more wires if required on the virtual grid place holdersAdd more wires if required on the virtual grid place holders

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Experimental SetupExperimental Setup InputInput

Floorplans with functional block current estimatesFloorplans with functional block current estimates Power pad locations and numberPower pad locations and number

Grids constructed for power delivery to 2cm X 2cm chipGrids constructed for power delivery to 2cm X 2cm chip Vdd=1.2V, Vspec=1.08 VVdd=1.2V, Vspec=1.08 V Sheet resistivity, current density, min pitch for 130nm Sheet resistivity, current density, min pitch for 130nm

techtech Flip-chip (FC) Flip-chip (FC) 400-600 power pads 400-600 power pads Wire-bond(WB)Wire-bond(WB)200-300 pads located at the periphery200-300 pads located at the periphery Initial wire width 60-100 µm, k=7 levels of partitioningInitial wire width 60-100 µm, k=7 levels of partitioning γγ in (0.65,1] , in (0.65,1] , ββ in (0.5,1], in (0.5,1], єє=15mv=15mv OutputOutput

A non-uniform power grid that meets the IR drop and EM A non-uniform power grid that meets the IR drop and EM constraintsconstraints

Wire width at the end of design is 2-6 µm Wire width at the end of design is 2-6 µm

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Experimental ResultsExperimental Results

CktCkt# of # of

BlocBlocksks

# of # of NodesNodes

( in ( in millions)millions)

Wire AreaWire Area Run TimeRun Time

(10(10-2 -2 cmcm22) ) (sec)(sec)

FCFC WBWB FCFC WBWB FCFC WBWB

pg-1pg-1 1717 1.56 1.56 1.631.63 8.128.12 8.528.52 443443 661661

pg-2pg-2 1717 1.19 1.19 1.221.22 7.837.83 8.168.16 517517 787787

pg-3pg-3 1212 1.26 1.26 1.381.38 7.217.21 7.547.54 653653 839839

pg-4pg-4 1616 1.051.05 1.211.21 6.886.88 7.387.38 617617 842842

pg-5pg-5 2020 1.22 1.22 1.341.34 7.047.04 8.068.06 572572 805805

pg-6pg-6 2424 1.141.14 1.191.19 7.227.22 7.867.86 683683 935935

pg-7pg-7 2020 1.641.64 1.701.70 8.528.52 10.210.222

431431 692692

pg-8pg-8 2222 1.291.29 1.361.36 8.408.40 9.929.92 452452 671671

Power grids > 1M nodes designed in 7-12 mins for FC and 11-16 mins for WBPower grids > 1M nodes designed in 7-12 mins for FC and 11-16 mins for WB Wire bond designs are suboptimal due to absence of locality propertyWire bond designs are suboptimal due to absence of locality property

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Experimental ResultsExperimental Results Proposed method compared with a previous Proposed method compared with a previous

workwork K. Wang and M. M SadowskaK. Wang and M. M Sadowska, “On-chip , “On-chip

Power Supply Network Optimization using Power Supply Network Optimization using Multigrid-based Technique”, DAC’04Multigrid-based Technique”, DAC’04

Multigrid method based on mapping from Multigrid method based on mapping from original space to a reduced spaceoriginal space to a reduced space

Originalmesh

Originalmesh

Reducedmesh

Reducedmesh

Optimizationengine

Optimizationengine

MultigridReduction

Backmapping

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Experimental ResultsExperimental Results

0.8

0.820.84

0.860.88

0.9

0.920.94

0.960.98

1

Ckt-1 Ckt-2 Ckt-3 Ckt-4 Ckt-5 Ckt-6

Proposed Method

Multigrid Method

% Saving in power grid wire area

7%-12% reduction in wire area over the multigrid-based method

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Experimental ResultsExperimental Results Constraints in the multigrid-based methodConstraints in the multigrid-based method

All rows (columns) of wires are constrained to All rows (columns) of wires are constrained to have the same widthhave the same width

Wastage of wiring resourcesWastage of wiring resources

Current Densities

High High

Med Low

High High

Med Low

High High

Med Low

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Experimental ResultsExperimental Results

0.9

0.95

1

1.05

1.1

1.15

Ckt-1 Ckt-2 Ckt-3 Ckt-4 Ckt-5 Ckt-6

Proposed Method

Multigrid Method

Runtime comparison of the two power grid design methods

Runtime is of the same order for the two methods

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SummarySummary A novel and efficient power grid design A novel and efficient power grid design

procedure proposedprocedure proposed Use notion of locality in grid designUse notion of locality in grid design Accuracy is maintained by using circuit analysis Accuracy is maintained by using circuit analysis

step in the inner loopstep in the inner loop Circuit analysis is made efficient by the use of Circuit analysis is made efficient by the use of

Grid abstractions Grid abstractions Coarse initial grid models followed by successive grid Coarse initial grid models followed by successive grid

refinementsrefinements Considerably fast power grid design method with Considerably fast power grid design method with

efficient wire area utilizationefficient wire area utilization

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THANKS !!!THANKS !!!