EECS373Fall2016HW1answers

1. A B C (A’+B) (C+A) (A+B’)*(C+A) 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1

B A C A

2. A B S0 Z 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 B S0 Z A S0

EECS 373 Winter 2016 HW1 answers 1

A B C (A+B’) (C+A) (A+B’)*(C+A) 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

2

A B S0 Z 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

3:

A B CIN COUT S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

B

S0

A

S0

Z

A B CIN A B A CIN B CIN

S

Cout

A

B

C

A

4a:

One interesting question about the answer below is “do I really need all these parentheses? And that’s a tricky question. In general you can often avoid them (the last two in this case, but not the first). Take

a look at http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Appendices/op_prec.html to see the

order of precedence.

You could also, in this case, use logical (&&, ||, !), rather than bitwise (&, |, ~) operators. Either would

be acceptable here (though I strongly prefer bitwise for logic like this). Using them interchangeably

would be inappropriate (though still work).

x Based on that order of precedence, why might mixing logical and bitwise operators be a really

bad idea even when using single-bit values? Also, why isn’t there a logical XOR/XNOR?

assign X=~(A&B) | (A&~C) | (B^C);

4b:

assign Z=(Se & B) | (~Se & A);

5a:

There are some better ways to write this, but here we are following the syntax in the sample code. You

could, for example, put the inputs and outputs in the module interface

(http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_modules.pdf has a

few good example).

module MUX21 (A,B,S,Z); input A,B,S; output Z; wire Z; assign Z=(B&S) | (A&~S);

endmodule

5b: There are a number of ways to instantiate modules. The way we generally list parameters is by in 270 is “by order” or “implicitly”. There are other options, and in EECS 470 we usually use “by name” which works a lot better in general (though it is more verbose) and is almost a requirement when you have a really large number of parameters (say 6+?). See http://www.asic-world.com/verilog/syntax2.html for a nice bit of coverage on this issue. (And by the way, asic-world is a really nice site for learning Verilog, highly recommended). Here I’m doing it by order. Also note, I’m selecting A[S] here, the homework didn’t specify which input to select based on S…

module add_2bit (A, S, Z); input [3:0] A; input [1:0] S; output Z; wire Z, tmp1, tmp2; MUX21 M1(A[3],A[2], S[0], tmp1); MUX21 M2(A[1],A[0], S[0], tmp2); MUX21 M3(tmp1, tmp2,S[1], Z);

endmodule

6: Note, that in this case, X must be a reg, not a wire… always @* X=~(A&B) | (A&~C) | (B&C); 7:

Clock D Q Q’

8:The reset part here caused people a lot more grief than was intended. A number of you came up with really cool ways of handling the reset signal. The intent was to just use a flip-flop with a reset. A number of you came up with some very impressive and creative solutions while using only full-adders and flip-flops without a reset. 9a: 3 bits used, the minimum would be 2. 9b: The assign statement version is a lot shorter, but harder to get and much harder to manipulate if the state machine needs minor changes. On the whole, the case-statement version is strongly preferred—less error-prone, easier to debug and easier to modify.

Clock

Q0 A

S B

Cout Cin

D flip-flop D Q C QB

R

1

0 D flip-flop

D Q C QB

R

A S

B Cout

Cin

Q1

0

Reset

10:

11: Consider a D flip-flop with inputs “D” and “clock” and output “Q” as shown on the right. It is positive-edge triggered.

x Set-up time is the time before a positive edge of the clock where D must be unchanging. This is tsu in the diagram below.

x Hold time is the time after a positive edge of the input clock where D must be unchanging. This is thd in the diagram below.

Zero

out=0000

Two

out=0010

One

out=0001

Three

out=0101

in

in’ 1

1

in’

in

1

1

D flip-flop D Q clock

12ai: A tri-state device is a device that is capable of driving either a “1” (high), “0” (low) or “HiZ” (High impedance). HiZ is a state where the device isn’t actually driving a signal onto the wire. It is, in effect electrically disconnected from the wire. 12aii: A would drive a “1”, the other devices would need to drive HiZ. 12aiii: It’s not clear, but something bad. Potentially you could fry some transistors (or even the wire?) by creating a very low resistance path between power and ground (thus lots of current, thus lots of power, thus smoking the device). It could also just get hot or do something somewhat less spectacular. 12aiv: We don’t know. “1”, “0” and “HiZ” are all wrong. HiZ is especially wrong. Having HiZ as an input is basically leaving the wire to float, and thus the output is unknown.

12bi: An open-collector is one where the output either connects to ground or it connects to nothing. Imagine having a bunch of these devices all connected to a wire. If any one of them connect to ground, the wire is at ground. But if none of them do, the wire will float (HiZ). Now if we add a pull-up resistor, the “float” result (when no device connects to ground) will be end up as a “1” because the

resistor will pull the output high. 12bii: A would drive nothing onto the bus and everyone else would too. The pullup resistor would bring the wire to a “1” 12biii: A would drive a “0” and everyone else should drive nothing (though in fact it doesn’t matter what they drive). That would pull the wire to “0”. (Note: for 12bii and iii it can be unclear exactly what “need to drive” means. It could be the drive on the wire (the “open collector”) or it could be the base (“IC Output”). If the base, for ii every device would need to have a “0” applied for ii, and for iii the driving device would have to put a “1” on the base and it wouldn’t matter what the rest did.)