1 2-hardware design basics of embedded processors
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2-Hardware Design Basics of Embedded Processors
2
Outline
Introduction Combinational logic Sequential logic Custom single-purpose processor design RT-level custom single-purpose processor design
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Introduction
Processor Digital circuit that performs a computation
tasks Controller and datapath General-purpose: variety of computation tasks Single-purpose: one particular computation
task Custom single-purpose: non-standard task
A custom single-purpose processor may be
Fast, small, low power But, high NRE, longer time-to-market, less
flexible
Microcontroller
CCD preprocessor
Pixel coprocessorA2D
D2A
JPEG codec
DMA controller
Memory controller ISA bus interface UART LCD ctrl
Display ctrl
Multiplier/Accum
Digital camera chip
lens
CCD
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CMOS transistor on silicon
Transistor The basic electrical component in digital systems Acts as an on/off switch Voltage at “gate” controls whether current flows from source to
drain Don’t confuse this “gate” with a logic gate
source drainoxidegate
IC package IC channel
Silicon substrate
gate
source
drain
Conductsif gate=1
1
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CMOS transistor implementations
Complementary Metal Oxide Semiconductor
We refer to logic levels Typically 0 is 0V, 1 is 5V
Two basic CMOS types nMOS conducts if gate=1 pMOS conducts if gate=0 Hence “complementary”
Basic gates Inverter, NAND, NOR
x F = x'
1
inverter
0
F = (xy)'
x
1
x
y
y
NAND gate
0
1
F = (x+y)'
x y
x
y
NOR gate
0
gate
source
drain
nMOS
Conductsif gate=1
gate
source
drain
pMOS
Conductsif gate=0
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Basic logic gates
F = x yAND
F = (x y)’NAND
F = x yXOR
F = xDriver
F = x’Inverter
x F
F = x + yOR
F = (x+y)’NOR
x F
x
yF
Fx
y
x
yF
x
yF
x
yF
F = x yXNOR
Fyxx
0y0
F0
0 1 01 0 01 1 1
x0
y0
F0
0 1 11 0 11 1 1
x0
y0
F0
0 1 11 0 11 1 0
x0
y0
F1
0 1 01 0 01 1 1
x0
y0
F1
0 1 11 0 11 1 0
x0
y0
F1
0 1 01 0 01 1 0
x F0 01 1
x F0 11 0
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Combinational logic design A) Problem description
y is 1 if a is to 1, or b and c are 1. z is 1 if b or c is to 1, but not both, or if all are 1.
D) Minimized output equations
00
0
1
01 11 10
0
1
0 1 0
1 1 1
abcy
y = a + bc
00
0
1
01 11 10
0
0
1 0 1
1 1 1
z
z = ab + b’c + bc’
abc
C) Output equations
y = a'bc + ab'c' + ab'c + abc' + abc
z = a'b'c + a'bc' + ab'c + abc' + abc
B) Truth table
1 0 1 1 11 1 0 1 11 1 1 1 1
0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 1 0
00 0 0 0
Inputsa b c
Outputsy z
E) Logic Gates
abc
y
z
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Combinational components
With enable input e all O’s are 0 if e=0
With carry-in input Ci
sum = A + B + Ci
May have status outputs carry, zero, etc.
O =I0 if S=0..00I1 if S=0..01…I(m-1) if S=1..11
O0 =1 if I=0..00O1 =1 if I=0..01…O(n-1) =1 if I=1..11
sum = A+B (first n bits)carry = (n+1)’th bit of A+B
less = 1 if A<B equal =1 if A=Bgreater=1 if A>B
O = A op Bop determinedby S.
n-bit, m x 1 Multiplexor
O
…S0
S(log m)
n
n
I(m-1) I1 I0
…
log n x n Decoder
…
O1 O0O(n-1)
I0I(log n -1)
…
n-bitAdder
n
A B
n
sumcarry
n-bitComparator
n n
A B
less equal greater
n bit, m function
ALU
n n
A B
…S0
S(log m)
n
O
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Sequential components
Q = 0 if clear=1, I if load=1 and clock=1, Q(previous) otherwise.
Q = 0 if clear=1, Q(prev)+1 if count=1 and clock=1.
clear
n-bitRegister
n
n
load
I
Q
shift
I Q
n-bitShift register
n-bitCounter
n
Q
Q = lsb - Content shifted - I stored in msb
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Sequential logic design
A) Problem Description
You want to construct a clock divider. Slow down your pre-existing clock so that you output a 1 for every four clock cycles
0
1 2
3
x=0
x=1x=0
x=0
a=1 a=1
a=1
a=1
a=0
a=0
a=0
a=0
B) State Diagram
C) Implementation Model
Combinational logic
State register
a x
I0
I0
I1
I1
Q1 Q0
D) State Table (Moore-type)
1 0 1 1 11 1 0 1 11 1 1 0 0
0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 1 0
00 0 0 0
InputsQ1 Q0 a
OutputsI1 I0
1
0
0
0
x
Given this implementation model Sequential logic design quickly reduces to
combinational logic design
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Sequential logic design (cont.)
00
1
Q1Q0 I1
I1 = Q1’Q0a + Q1a’ + Q1Q0’
0 1
1
1
010
00 11 10 a 01
0
0
0
1 0 1
1
00 01 11 a
1
10 I0 Q1Q0
I0 = Q0a’ + Q0’a0
1
0 0
0
1
1
0
0
00 01 11 10
x = Q1Q0
x
0
1
0
a
Q1Q0
E) Minimized Output Equations F) Combinational Logic
a
Q1 Q0
I0
I1
x
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HDL based design (review examples)
1. D_Latch
2. Greatest common divisor circuit (GCD)
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1-D_Latch: VHDL module examples--D_latch.vhd
library IEEE;use IEEE.STD_LOGIC_1164.all;
ENTITY D_latch IS PORT ( d,clk : IN STD_LOGIC;
q : OUT STD_LOGIC);END D_latch;
ARCHITECTURE concurrent OF D_latch ISSIGNAL qwire,qb : STD_LOGIC;SIGNAL sb,rb,db: STD_LOGIC;
BEGIN sb <= d nand clk; rb <= not (d) nand clk; qwire <= sb nand qb; qb <= rb nand qwire; q<=qwire;END concurrent;
ARCHITECTURE behaviour OF D_latch ISBEGIN Process (d,clk)
variable qwire,qb : STD_LOGIC;variable sb,rb,db: STD_LOGIC;BEGIN
sb := d nand clk; rb := not (d) nand clk; qwire := sb nand qb; qb:= rb nand qwire; q<=qwire; END Process;END behaviour;
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1-D_Latch: VHDL module examplesARCHITECTURE behaviour2 OF D_latch ISBEGIN Process (d,clk)
variable qwire,qb : STD_LOGIC;variable sb,rb,db: STD_LOGIC;BEGIN
if (clk='1') then q<=d; end if; END Process;END behaviour2;
- - test file (tD_latch.vhd)library IEEE;use IEEE.STD_LOGIC_1164.all;
entity DlatchTB isend DlatchTB;
Architecture TB_arch of DlatchTB is component D_latch port (d,clk: in STD_LOGIC; q: out STD_LOGIC); end
component;signal dT,clkT, qT: STD_LOGIC;begin
U1: D_latch port map (dT, clkT, qT);process begin
report "Begining test bench for D latch" severity note;dT<='0'; clkT<='0'; wait for 10 ns;dT<='0'; clkT<='1'; wait for 10 ns;dT<='1'; clkT<='1'; wait for 10 ns;
end process;end TB_arch;
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2- Greatest common divisor circuit (GCD)
continually subtracting the smaller of the two numbers, A or B, from the largest.
Stop when the smallest =0
file: gcd_test_data.txt 21 49 7 25 30 5 19 27 1 40 40 40
file: gcd_test_data_hex.txt 15 31 7 19 1E 5 19 27 1 28 28 28
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Greatest common divisor circuit (GCD): C code
#include <stdio.h>
main () {
int A_in, B_in, A, B, Swap, Y, Y_Ref;
FILE *file_pointer;
file_pointer = fopen("gcd_test_data.txt", "r");
while (!feof(file_pointer)) {
fscanf (file_pointer, "%d %d %d\n", &A_in, &B_in, &Y_Ref);
A = A_in; B = B_in;
if (A != 0 && B != 0) {
while (B != 0) {
while (A >= B) {
A = A - B;
}
Swap = A; A = B;B = Swap;
}
}
else A = 0;
Y = A; //should be equal to Y_Ref
}
}
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Greatest common divisor circuit (GCD): Verilog module
module GCD_ALG(A_in,B_in,Y);
parameter Width = 8;
input [Width-1:0] A_in, B_in;
output [Width-1:0] Y;
reg [Width-1:0] A, B, Swap, Y;
always @(A_in)// or B) begin
begin
A = A_in; B = B_in;
if (A != 0 && B != 0)
while (B != 0) begin
while (A >= B) A = A - B;
Swap = A; A = B; B = Swap;
end
else
A = 0;
Y = A;
end
endmodule
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Greatest common divisor circuit (GCD): Verilog modulemodule test_GCD; // Test GCD algorithmparameter GCD_tests = 4;parameter Width = 8;reg [Width-1:0] A_in, B_in, Y_Ref;integer N;integer SimResults;reg [Width-1:0] AB_Y_Ref_Arr[1:GCD_tests*3];wire [Width-1:0] Y;
GCD_ALG U0 (A_in,B_in,Y);
initial $monitor (" GCD: A=%d B=%d Y=%d. Y should be %d", A_in, B_in, Y, Y_Ref);
initial begin $readmemh("gcd_test_data_hex.txt", AB_Y_Ref_Arr); SimResults = $fopen("gcd_simres.txt"); // Open simulation results file for (N=0; N<GCD_tests; N=N+1) begin A_in = AB_Y_Ref_Arr[(N*3)+1]; B_in = AB_Y_Ref_Arr[(N*3)+2]; Y_Ref =AB_Y_Ref_Arr[(N*3)+3]; #10; $fdisplay (SimResults, " GCD: A=%d B=%d Y=%d. Y should be %d", A_in, B_in, Y, Y_Ref); end $fclose (SimResults); $finish;endendmodule
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Greatest common divisor circuit (GCD): VHDL moduleENTITY GCD IS
PORT( A_in,B_in : IN integer range 0 to 15;
Y : OUT integer range 0 to 15 );
END GCD;
ARCHITECTURE behaviour OF GCD IS
BEGIN Process (A_in,B_in) variable A, B, Swap: integer range 0 to 15; BEGIN A := A_in;B := B_in; for i in 0 to 15 loop if (A /= 0 and B /= 0) then if (A>=B) then A := A - B; else Swap:= A; A := B; B := Swap; end if; else A:=0; end if; end loop; Y<=A; END Process;END behaviour;