1. 2 electronics beyond nano-scale cmos shekhar borkar intel corp. july 27, 2006
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Electronics Beyond Electronics Beyond Nano-scale CMOSNano-scale CMOS
Shekhar Borkar Shekhar Borkar
Intel Corp.Intel Corp.
July 27, 2006July 27, 2006
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OutlineOutlineEvolution of Electronics to CMOSEvolution of Electronics to CMOSThe three tenetsThe three tenetsTechnology outlookTechnology outlookChallengesChallengesPotential solutionsPotential solutionsSummarySummary
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Evolution of ElectronicsEvolution of Electronics0
1
1850 1875 1900 1925 1950 1975 2000 2025
MechanicalMechanical
Electro-MechanicalElectro-Mechanical
Electronic-VTElectronic-VT
BipolarBipolar
NMOSNMOS
CMOS……. ?CMOS……. ?
All cross-road technologies show1. Gain2. Signal/Noise3. Scalability
All cross-road technologies show1. Gain2. Signal/Noise3. Scalability
PerformanceEnergyPrice/Performance
PerformanceEnergyPrice/Performance
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The Three TenetsThe Three Tenets
GainGainInput Output
Energy
(1)
Signal/Noise
Signal/NoiseInput Output
(2)
Scalability, in some shape or form
(3)
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Electro-Mechanical scaling—Electro-Mechanical scaling—RelaysRelays
1928, Otis Elevator
7
Vacuum TubesVacuum Tubes
1930’s
1920’s
1950’s & 60’s
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SemiconductorsSemiconductors
The first transistor
The first integrated circuit 4004 Pentium® 4
9
1.E-21
1.E-18
1.E-15
1.E-12
1.E-09
1.E-06
1.E-03
1.E+00
1940 1960 1980 2000 2020
Cu
bic
Met
er
Vacuum tube
Transistor
NMOS
CMOS
Benefits of ScalingBenefits of Scaling
1.E-11
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1940 1960 1980 2000 2020
Del
ay (
Sec
) Vacuum tube
Transistor
NMOS
CMOS
1.E-161.E-141.E-121.E-101.E-081.E-061.E-041.E-021.E+00
1940 1960 1980 2000 2020
Jou
les
Vacuum tube
Transistor
NMOS
CMOS
1.E-061.E-051.E-041.E-031.E-021.E-011.E+001.E+011.E+02
1940 1960 1980 2000 2020
Co
st (
$)
Vacuum tube
Transistor
NMOS
CMOS
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Technology OutlookTechnology OutlookHigh Volume High Volume ManufacturingManufacturing
20042004 20062006 20082008 20102010 20122012 20142014 20162016 20182018
Technology Node Technology Node (nm)(nm)
9090 6565 4545 3232 2222 1616 1111 88
Integration Integration Capacity (BT)Capacity (BT)
2 4 8 16 32 64 128 256
Delay = CV/I Delay = CV/I scalingscaling
0.70.7 ~0.7~0.7 >0.7>0.7 Delay scaling will slow downDelay scaling will slow down
Energy/Logic Op Energy/Logic Op scalingscaling
>0.35>0.35 >0.5>0.5 >0.5>0.5 Energy scaling will slow downEnergy scaling will slow down
Bulk Planar CMOSBulk Planar CMOS High Probability Low ProbabilityHigh Probability Low Probability
Alternate, 3G etcAlternate, 3G etc Low Probability High ProbabilityLow Probability High Probability
VariabilityVariability Medium High Very HighMedium High Very High
ILD (K)ILD (K) ~3~3 <3<3 Reduce slowly towards 2-2.5Reduce slowly towards 2-2.5
RC DelayRC Delay 11 11 11 11 11 11 11 11
Metal LayersMetal Layers 6-76-7 7-87-8 8-98-9 0.5 to 1 layer per generation0.5 to 1 layer per generation
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Si Substrate
Metal Gate
High-kTri-Gate
S
G
D
III-V
S
Carbon Nanotube FET
50 nm
35 nm
30 nm
SiGe S/D
Strained Silicon
SiGe S/D
Strained Silicon
90 nm65 nm
45 nm32 nm
20042006
20082010
2012+
Technology Generation
20 nm 10 nm
5 nm5 nm
5 nm
Nanowire
Manufacturing Development Research
CMOS Research Continues…CMOS Research Continues…
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CMOS—Cross Road?CMOS—Cross Road?Cross Road False AlarmsCross Road False Alarms
1 1 Short Channel EffectsShort Channel Effects Device EngineeringDevice Engineering
0.5 0.5 InterconnectsInterconnects More metals, CuMore metals, Cu
Low K ILDLow K ILD
130 nm130 nm SD LeakageSD Leakage Leakage control, Leakage control, avoidance, avoidance, tolerancetolerance
65 nm65 nm Gate LeakageGate Leakage Hi-K + Metal GateHi-K + Metal Gate
22 nm22 nm LithographyLithography EUV, Self assemblyEUV, Self assembly
…… …… ……
< 1.5nm< 1.5nm SD TunnelingSD Tunneling ??
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What’s in sight after CMOS?What’s in sight after CMOS?
Which technology shows gain?Which technology shows gain?Satisfactory signal to noise ratio?Satisfactory signal to noise ratio?
– At room temperature?At room temperature?
Scalability in some shape or form?Scalability in some shape or form?–Performance, Energy, CostPerformance, Energy, Cost
Research must continue to find oneResearch must continue to find oneThen it will take 10-15 years to matureThen it will take 10-15 years to matureUntil then…Until then…
CMOS will continue…CMOS will continue…CMOS will continue…CMOS will continue…
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……But With Challenges!But With Challenges!
0
50
100
150
200
250H
ea
t F
lux
(W
/cm
2)
Heat Flux (W/cm2)—Vcc variation
40
50
60
70
80
90
100
110
Te
mp
era
ture
(C
)
Temp Variation & Hot spots
10
100
1000
10000
1000 500 250 130 65 32
Technology Node (nm)
Mea
n N
um
ber
of
Do
pan
t A
tom
s
Random Dopant Fluctuations
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm
193nm193nm248nm248nm
365nm365nm LithographyLithographyWavelengthWavelength
65nm65nm90nm90nm
130nm130nm
GenerationGeneration
GapGap
45nm45nm32nm32nm
13nm 13nm EUVEUV
180nm180nm
Source: Mark Bohr, Intel
Sub-wavelength Lithography
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Yesterday’s Freelance LayoutYesterday’s Freelance Layout
Vss
Vdd
OpIp
Vss
Vdd
Op
No layout restrictionsNo layout restrictionsNo layout restrictionsNo layout restrictions
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Transistor Orientation RestrictionsTransistor Orientation Restrictions
Vss
Vdd
OpIp
Vss
Vdd
Op
Transistor orientation restricted to improve Transistor orientation restricted to improve manufacturing controlmanufacturing control
Transistor orientation restricted to improve Transistor orientation restricted to improve manufacturing controlmanufacturing control
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Op
Vss
Vdd
Ip
Vss
Vdd
Op
Transistor Width QuantizationTransistor Width Quantization
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Today’s Unrestricted Today’s Unrestricted RoutingRouting
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Future Metal RestrictionsFuture Metal Restrictions
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ReliabilityReliability
Soft Error FIT/Chip (Logic & Mem)
0
50
100
150
Re
lati
ve
~8% degradation/bit/generation
Time dependent device degradation
0
1
1 2 3 4 5 6 7 8 9 10
Time
Ion
Re
lati
ve
Burn-in may phase out…?
1
10
100
1000
10000
180 90 45 22
Jo
x (
Re
lati
ve
)Hi-K?
?
Extreme device variations
0
50
100
100 120 140 160 180 200
Vt(mV)
Re
lati
ve
Wider
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Implications to ReliabilityImplications to Reliability
Extreme variations (Static & Dynamic) Extreme variations (Static & Dynamic) will result in unreliable componentswill result in unreliable components
Impossible to design reliable system Impossible to design reliable system as we know todayas we know today–Transient errors (Soft Errors) Transient errors (Soft Errors)
–Gradual errors (Variations)Gradual errors (Variations)
–Time dependent (Degradation)Time dependent (Degradation)
Reliable systems with unreliable components Reliable systems with unreliable components ——Resilient Resilient ArchitecturesArchitectures
Reliable systems with unreliable components Reliable systems with unreliable components ——Resilient Resilient ArchitecturesArchitectures
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Implications to Design & TestImplications to Design & Test
Design with regular fabricDesign with regular fabricOne-time-factory testing will be outOne-time-factory testing will be outBurn-in to catch chip infant-mortality Burn-in to catch chip infant-mortality
will not be practicalwill not be practicalTest HW will be part of the designTest HW will be part of the designDynamically self-test, detect errors, Dynamically self-test, detect errors,
reconfigure, & adaptreconfigure, & adapt
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In a Nut-shell…In a Nut-shell…
100 Billion
Transistors
100 Billion
Transistors
100 BT integration capacity
Billions unusable (variations)
Some will fail over time
Yet, deliver high performance in the power & Yet, deliver high performance in the power & cost envelopecost envelope
Yet, deliver high performance in the power & Yet, deliver high performance in the power & cost envelopecost envelope
Intermittent failures
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Recipe for ResiliencyRecipe for Resiliency
1.1. DetectDetect
2.2. IsolateIsolate
3.3. ConfineConfine
4.4. ReconfigureReconfigure
5.5. Recover & adaptRecover & adapt
1.1. CircuitCircuit
2.2. FirmwareFirmware
3.3. PlatformPlatform
4.4. SoftwareSoftware
5.5. ApplicationApplication
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Resiliency with ReconfigurationResiliency with Reconfiguration
Dynamic on-chip testingDynamic on-chip testing Performance profilingPerformance profiling Spare hardwareSpare hardware Binning strategyBinning strategy Dynamic, fine grain, Dynamic, fine grain,
performance and power performance and power managementmanagement
Coarse-grain redundancy Coarse-grain redundancy checkingchecking
Dynamic error detection & Dynamic error detection & reconfiguration reconfiguration
Decommission aging HW, Decommission aging HW, swap with spareswap with spare
Dynamically…Dynamically…1.1. Self test & detectSelf test & detect2.2. Isolate errorsIsolate errors3.3. ConfineConfine4.4. Reconfigure, andReconfigure, and5.5. AdaptAdapt
Dynamically…Dynamically…1.1. Self test & detectSelf test & detect2.2. Isolate errorsIsolate errors3.3. ConfineConfine4.4. Reconfigure, andReconfigure, and5.5. AdaptAdapt
CC
CC
CC
CC
CC
CC
CC
CC
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Why Bother?Why Bother?
$1
$10
$100
$1,000
$10,000
$100,000
1960 1970 1980 1990 2000 2010
Lit
ho
To
ol
Co
st (
$K)
G. MooreISSCC 03
Litho Cost
$1
$10
$100
$1,000
$10,000
1960 1970 1980 1990 2000 2010
Fab
Co
st (
$M)
www.icknowledge.com
FAB Cost
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1960 1970 1980 1990 2000 2010
$/T
ran
sist
or
$ per Transistor
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1960 1970 1980 1990 2000 2010
$/M
IPs
$ per MIPS
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SummarySummary
Three tenets: Gain, Signal/Noise, Three tenets: Gain, Signal/Noise, ScalabilityScalability
Nothing on the horizon satisfies themNothing on the horizon satisfies themResearch must continue to find oneResearch must continue to find oneBut until then, CMOS rulesBut until then, CMOS rulesSeveral challenges lay ahead, but when Several challenges lay ahead, but when
have they not?have they not?