1 1998 morgan kaufmann publishers interfacing processors and peripherals
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11998 Morgan Kaufmann Publishers
Interfacing Processors and Peripherals
Mainmemory
I/Ocontroller
I/Ocontroller
I/Ocontroller
Disk Graphicsoutput
Network
Memory– I/O bus
Processor
Cache
Interrupts
Disk
21998 Morgan Kaufmann Publishers
I/O Devices
Device Behavior Partner Data rate (KB/sec)Keyboard input human 0.01Mouse input human 0.02Voice input input human 0.02Scanner input human 400.00Voice output output human 0.60Line printer output human 1.00Laser printer output human 200.00Graphics display output human 60,000.00Modem input or output machine 2.00-8.00Network/LAN input or output machine 500.00-6000.00Floppy disk storage machine 100.00Optical disk storage machine 1000.00Magnetic tape storage machine 2000.00Magnetic disk storage machine 2000.00-10,000.00
31998 Morgan Kaufmann Publishers
Input/Output
• Very diverse devices
– behaviour (i.e., input vs. output)
– partner (who is at the other end?)
– data rate
• Important but neglected
– difficulties in assessing and designing I/O systems have often relegated I/O to second class status
41998 Morgan Kaufmann Publishers
Input/Output
• I/O design affected by performance, expandability, resilience, etc.
• I/O System performance depends on:– CPU– memory system (caches, main memory)– buses– I/O controller– I/O device– I/O software (operating system)
• Performance metrics:– throughput: I/O bandwidth– response time: latency
51998 Morgan Kaufmann Publishers
I/O Example: Disk Drives
To access data:— seek: position head over the proper track ( 6 ms)— rotational latency: wait for desired sector ( 4 ms) — transfer: one or more sectors ( 15 MB/s)
Platter
Track
Platters
Sectors
Tracks
61998 Morgan Kaufmann Publishers
Buses
• Shared communication link (one or more wires)
• Types of buses:– processor–memory (short, high speed, custom design)– backplane (high speed, often standardised, e.g., PCI)– I/O (lengthy, different devices, standardised, e.g., SCSI)
• Synchronous– use a clock and a synchronous protocol, fast and small– every device must operate at same rate– wait states possible– clock skew requires the bus to be short
• Asynchronous– doesn’t use a clock– uses handshaking
71998 Morgan Kaufmann Publishers
Bus Design
• Difficult– may be a bottleneck– length of the bus– number of devices– tradeoffs (buffers for higher bandwidth increase latency)– support for many different devices– cost
81998 Morgan Kaufmann Publishers
Bus Structures
Processor MemoryBackplane bus
a. I/O devices
Processor MemoryProcessor-memory bus
b.
Busadapter
Busadapter
I/Obus
I/Obus
Busadapter
I/Obus
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Bus Structures
Processor MemoryProcessor-memory bus
c.
Busadapter
Backplanebus
Busadapter
I/O bus
Busadapter
I/O bus
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Synchronous Bus Transfer Example: Read
T1 T2 T3
Clock
Addresslines Memory address
Datalines memory
Data acceptedby processor
AS
R/W
Data from
Fromprocessor
Bi-directional
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Synchronous Bus Transfer Example: Write
T1 T2 T3
Clock
Addresslines Memory address
Datalines
AS
R/W
Data from processor
Fromprocessor
Bi-directional
121998 Morgan Kaufmann Publishers
Synchronous Write with a Wait State
T1 T2 T3Clock
Addresslines
Memory address
Datalines
AS
R/W
Data from processor
Fromprocessor
Bi-directional
WAIT
Tw
WAIT checkedby processor
Frommemory
131998 Morgan Kaufmann Publishers
Asynchronous Handshaking Example
• A device requests a word from the memory
• Three control lines
– ReadReq: indicates a read request for memory
– DataRdy: indicates the word is ready on the data lines
– Ack: acknowledges the Req or Rdy signal of the other party
141998 Morgan Kaufmann Publishers
Asynchronous Handshaking Waveforms
DataRdy
Ack
Data
ReadReq 1
3
4
5
7
642 2
address data
151998 Morgan Kaufmann Publishers
Controlling Bus Access
• A bus master controls access to the bus
– it initiates and controls all bus requests
– the slave responds to requests
• Single bus master
– the processor
• Multiple bus masters
– bus arbitration
161998 Morgan Kaufmann Publishers
Bus Arbitration
• daisy chain arbitration
– bus granted in priority order
– a grant line runs through the devices
• centralized, parallel arbitration
– centralised arbiter chooses from among requesting devices
– e.g., PCI
• distributed arbitration by self-selection
– each requesting device makes a request on the bus and determines
independently who has the highest priority
– e.g., NuBus used in Macintosh
• distributed arbitration by collision detection
– each device independently requests the bus, collisions are detected
– e.g., Ethernet
171998 Morgan Kaufmann Publishers
Operating system
• Responsibilities of the OS arise from
– I/O system is shared by multiple programs
– I/O systems often use interrupts
– low-level control of an I/O device is complex: concurrent events, detailed
requirements
• Functions the OS must provide
– protection, by maintaining user rights
– abstractions for accessing devices
– interrupt handling
– equitable access to shared I/O resources
• Three types of communication
– OS gives commands to the devices
– devices notify the OS when operations are completed
– data transfer between memory and an I/O device
181998 Morgan Kaufmann Publishers
Giving Commands to I/O Devices
• Special I/O instructions specifying
– device number
– command word
• Memory-mapped I/O
– portions of the address space are assigned to I/O devices
– those addresses are used by the control, status and data registers of the devices
– reads and writes to those addresses are interpreted as commands to the I/O devices
– user programs are prevented from issuing I/O operations directly
191998 Morgan Kaufmann Publishers
Communicating with the Processor
• The OS needs to know when
– the I/O device has completed an operation
– the I/O operation has encounted an error
• Methods
– polling
– interrupt-driven I/O
• Polling
– the I/O devices put information in status registers
– the OS periodically checks the status registers
– simple: the processor is totally in control and does all the work
– consumes a lot of processor time
201998 Morgan Kaufmann Publishers
Communicating with the Processor
• Interrupt-driven I/O
– I/O interrupts are just like exceptions except:
• an I/O interrupt is asynchronous
• further information needs to be conveyed
– interrupts indicate to the processor that an I/O device needs attention
– user program progress is only halted but special hardware is needed to
• send a request (device)
• detect an interrupt (processor)
• save the CPU state during the interrupt service routine (processor)
211998 Morgan Kaufmann Publishers
Direct Memory Access
• External to the CPU
• Direct transfer of data to or from the memory without involving the
processor
• The DMA controller becomes the bus master and directs the reads and
writes
• Steps in a DMA transfer
– the processor supplies the identity of the device, the operation, the
memory address and the number of bytes
– the DMA controller completes the operation without bothering the
processor
– the DMA controller interrupts the processor to inform that the transfer
is complete