1-1 bard, gerstlauer, valvano, yerraballi ee 319k introduction to microcontrollers lecture 1:...
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1-1Bard, Gerstlauer, Valvano, Yerraballi
EE 319KIntroduction to Microcontrollers
Lecture 1: Introduction, Embedded Systems, Product
Life-Cycle, ARM Programming
1-2Bard, Gerstlauer, Valvano, Yerraballi
AgendaCourse Description
Book, Labs, EquipmentGrading CriteriaExpectations/ResponsibilitiesPrerequisites
Embedded SystemsMicrocontrollers
Product Life CycleAnalysis, Design, Implementation, TestingFlowcharts, Data-Flow and Call Graphs
ARM ArchitectureProgrammingIntegrated Development Environment (IDE)
1-3Bard, Gerstlauer, Valvano, Yerraballi
EE306 Recap: Digital Logic
Positive logic: Negative logic : True is higher voltage True is lower voltageFalse is lower voltage False is higher voltage
0 1.3 2.0 5 V
"0" Illegal "1"Digital
Analog
AND, OR, NOT Flip flops Registers
A ~A
74HC04
+3.3V
~An-type
p-type source
gateA
drain
drain
gate source
0 V active off +3.3V+3.3V off active 0V
A p-type n-type ~A
A01
~A 1 0
1-4Bard, Gerstlauer, Valvano, Yerraballi
EE302 Recap: Ohm’s Law
V = I * R Voltage = Current * Resistance
I = V / R Current = Voltage / Resistance
R = V / I Resistance = Voltage / Current
R = 1kBatteryV=3.7V
Resistor
I = 3.7mA
R
I
V
•P = V * I Power = Voltage * Current•P = V2 / R Power = Voltage2 / Resistance•P = I2 * R Power = Current2 * Resistance
1-5Bard, Gerstlauer, Valvano, Yerraballi
Embedded System
Embedded Systems are everywhere Ubiquitous, invisible Hidden (computer inside) Dedicated purpose
MicroProcessor Intel: 4004, ..8080,.. x86 Motorola: 6800, .. 6812,..
PowerPC ARM, DEC, SPARC, MIPS,
PowerPC, Natl. Semi.,… MicroController
Processor+Memory+I/O Ports (Interfaces)
communications
automotive
medical
appliances
consumer electronics
microcomputer
I/O Ports
Microcontroller Electrical,mechanical,
chemical,or
opticaldevices
Embedded system
Bus ADCAnalogsignals
LM3S or LM4F
DAC
Processor
RAM
ROM
1-6Bard, Gerstlauer, Valvano, Yerraballi
Embedded Systems
A reactive system continuouslyaccepts inputsperforms calculationsgenerates outputs
A real time system Specifies an upper bound on the time
required to perform the input/calculation/output in reaction to external events
1-7Bard, Gerstlauer, Valvano, Yerraballi
Microcontroller Processor – Instruction Set
CISC vs. RISC Memory
Non-Volatileo ROM o EPROM, EEPROM, Flash
Volatileo RAM (DRAM, SRAM)
Interfaces H/W: Ports S/W: Device Driver Parallel, Serial, Analog, Time
I/O Memory-mapped vs. I/O mapped
1-8Bard, Gerstlauer, Valvano, Yerraballi
Texas Instruments TM4C123
ARM Cortex-M4+ 256K EEPROM+ 32K RAM+ JTAG+ Ports+ SysTick+ ADC+ UART
GPIO Port D
GPIO Port A
ADC2 channels12 inputs
12 bits
PA7PA6
PA5/SSI0TxPA4/SSI0RxPA3/SSI0FssPA2/SSI0Clk
PA1/U0TxPA0/U0Rx
PC7PC6PC5PC4
PC3/TDO/SWOPC2/TDI
PC1/TMS/SWDIOPC0/TCK/SWCLK
PE5PE4PE3PE2PE1PE0
GPIO Port C
GPIO Port E
JTAG
FourSSIs
EightUARTs
PB7PB6PB5PB4PB3/I2C0SDAPB2/I2C0SCLPB1PB0
PD7PD6PD5PD4PD3PD2PD1PD0
PF4PF3PF2PF1PF0
GPIO Port B
FourI2Cs
USB 2.0
Cortex M4 Systick
NVIC
Two AnalogComparators
Advanced Peripheral Bus
TwelveTimers
Six64-bit wide
CAN 2.0
System Bus Interface
GPIO Port F
Advanced High Performance Bus
Two PWMModules
1-9
Done
• Hardware • Software
• Specifications • Constraints
Analyzethe
problem
RequirementsDesign
Constraints
Testing
• Block diagrams • Data flow graphs
Deployment
New requirementsNew constraints
Development
Bard, Gerstlauer, Valvano, Yerraballi
Product Life Cycle
Analysis (What?)Requirements ->
Specifications
Design (How?)High-Level: Block DiagramsEngineering: Algorithms,
Data Structures, Interfacing
Implementation(Real)Hardware, Software
Testing (Works?)Validation:CorrectnessPerformance: Efficiency
Maintenance (Improve)
1-10Bard, Gerstlauer, Valvano, Yerraballi
Data Flow Graph
Lab 8: Position Measurement System
PositionSensor
Voltage0 to +3V
ADChardware
ADCdriver
Sample0 to 4095
SysTickISR
Sample0 to 4095
SysTickhardware
LCDdisplay
LCDdriver
Fixed-point0 to 3.000
Position0 to 3 cm
1-11Bard, Gerstlauer, Valvano, Yerraballi
Call Flow Graph
Position Measurement System
main
SysTickhardware
SysTickinit
LCDhardware
LCDdriver
SysTickISR
ADChardware
ADCdriver
1-12Bard, Gerstlauer, Valvano, Yerraballi
Structured Programming
Common Constructs (as Flowcharts)
Fork
Join
Triggerinterrupt
Return from interrupt
main1
Init1
Body1
main2
Init2
Body2
main
Init
Body
Parallel Distributed Interrupt-driven concurrent
Block 1
Sequence Conditional While-loop
Block 2Block 1 Block 2 Block
1-13Bard, Gerstlauer, Valvano, Yerraballi
FlowchartToaster oven:
Coding in assembly and/or high-level language (C)
main
toast < desired
Output heatis on Too cold
Input fromswitch
Input toasttemperature
toast desired
StartNot pressed
Pressed
Output heatis off
Cook
return
Cook
1-14Bard, Gerstlauer, Valvano, Yerraballi
Flowchart Example 1.3. Design a flowchart for a system that performs two independent
tasks. The first task is to output a 20 kHz square wave on PORTA in real time (period is 50 ms). The second task is to read a value from PORTB, divide the value by 4, add 12, and output the result on PORTD. This second task is repeated over and over.
Clockvoid SysTick_Handler(void){ PORTA = PORTA^0x01;}
E
E
<
>
>
void main(void){unsigned long n; while(1){ n = PORTB; n = (n/4)+12; PORTD = n; }}
BCD
A
main
Input n fromPORTB
A
B
D
Cn = (n/4)+12
Output n toPORTD
PORTA =PORTA^1
1-15Bard, Gerstlauer, Valvano, Yerraballi
ARM Cortex M4-based System
DCode bus
ARM® CortexTM-Mprocessor
DataRAM
InstructionsFlash ROM
Inputports
Outputports
Microcontroller
ICode bus
Internalperipherals
PPB
System bus
AdvancedHigh-perfBus
ARM Cortex-M4 processor Harvard architecture
Different busses for instructions and data RISC machine
Pipelining effectively provides single cycle operation for many instructions
Thumb-2 configuration employs both 16 and 32 bit instructions
1-16Bard, Gerstlauer, Valvano, Yerraballi
ARM ISA: Thumb2 Instruction Set
Variable-length instructionsARM instructions are a fixed
length of 32 bitsThumb instructions are a fixed
length of 16 bitsThumb-2 instructions can be
either 16-bit or 32-bit Thumb-2 gives approximately 26%
improvement in code density over ARM
Thumb-2 gives approximately 25% improvement in performance over Thumb
1-17Bard, Gerstlauer, Valvano, Yerraballi
ARM ISA: Registers, Memory-mapR0R1R2R3R4R5R6R7R8R9R10R11R12
R13 (MSP)R14 (LR)R15 (PC)
Stack pointerLink register
Program counter
Generalpurposeregisters
TI TM4C123Microcontroller
256k FlashROM
32k RAM
I/O ports
Internal I/OPPB
0x0000.0000
0x0003.FFFF
0x2000.0000
0x2000.7FFF
0x4000.0000
0x400F.FFFF
0xE000.0000
0xE004.1FFF
Condition Code Bits IndicatesN negative Result is negativeZ zero Result is zeroV overflow Signed overflowC carry Unsigned overflow
1-18Bard, Gerstlauer, Valvano, Yerraballi
LC3 to ARM - Data MovementLEA R0, Label ;R0 <- PC + Offset to Label
ADR R0,Label or LDR R0,=Label
LD R1,Label ; R1 <- M[PC + Offset]
LDR R0,=Label ; Two steps: (i) Get address into R0LDRH R1,[R0] ; (ii) Get content of address [R0] into R1
LDR R1,R0,n ; R1 <- M[R0+n]
LDRH R1,[R0,#n]
LDI R1,Label ; R1 <- M[M[PC + Offset]]
; Three steps!!
ST R1,Label ; R1 -> M[PC + Offset]
LDR R0,=Label ; Two steps: (i)Get address into R0STRH R1,[R0] ; (ii) Put R1 contents into address in R0
STR R1,R0,n ; R1 -> M[R0+n]
STRH R1,[R0,#n]
STI R1,Label ; R1 -> M[M[PC + Offset]]
; Three steps!!
1-19Bard, Gerstlauer, Valvano, Yerraballi
LC3 to ARM – Arithmetic/Logic
ADD R1, R2, R3 ; R1 <- R2 + R3
ADD R1,R2,R3 ; 32-bit only
ADD R1,R2,#5 ; R1 <- R2 + 5
ADD R1,R2,#5 ; 32-bit only, Immediate is 12-bit
AND R1,R2,R3 ; R1 <- R2 & R3
AND R1, R2, R3 ; 32-bit only
AND R1,R2,#1 ; R1 <- Bit 0 of R2 AND R1, R2, #1 ; 32-bit only
NOT R1,R2 ; R1 -> ~(R2)
EOR R1,R2,#-1 ; -1 is 0xFFFFFFFF,
; so bit XOR with 1 gives complement
1-20Bard, Gerstlauer, Valvano, Yerraballi
LC3 to ARM – BranchesBR Target ; PC <- Address of Target
B Target
BRnzp Target ; PC <- Address of Target
B Target
BRn Target ; PC <- Address of Target if N=1
BMI Target ; Branch on Minus
BRz Target ; PC <- Address of Target if Z=1
BEQ Target
BRp Target ; PC <- Address of Target if P=1
No Equivalent
BRnp Target ; PC <- Address of Target if Z=0
BNE Target
BRzp Target ; PC <- Address of Target if N=0
BPL Target ; Branch on positive or zero (Plus)
BRnz Target ; PC <- Address of Target if P=0
No Equivalent
1-21Bard, Gerstlauer, Valvano, Yerraballi
LC3 to ARM – Subs,TRAP,Interrupt
JSR Sub ; PC <- Address of Sub, Return address in R7
BL Sub ; PC<-Address of Sub, Ret. Addr in R14 (Link Reg)
JSRR R4 ; PC <- R4, Return address in R7
BLX R4 ; PC <-R4, Return address in R14 (Link Reg)
RET ; PC <- R7 (Implicit JMP to address in R7)
BX LR ; PC <- R14 (Link Reg)
JMP R2 ; PC <- R2
BX R2 ; PC <- R14 (Link Reg)
TRAP x25 ; PC <- M[x0025], Return address in R7
SVC #0x25 ; Similar in concept but not implementation
RTI ; Pop PC and PSR from Supervisor Stack…
BX LR ; PC <- R14 (Link Reg) [same as RET]
1-22Bard, Gerstlauer, Valvano, Yerraballi
SW Development Environment
0x00000142 49120x00000144 68080x00000146 F040000F0x0000014A 6008
Start; direction register LDR R1,=GPIO_PORTD_DIR_R LDR R0,[R1] ORR R0,R0,#0x0F; make PD3-0 output STR R0, [R1]
Source code
Build Target (F7)
Download
Object code
Processor
Memory
I/O
SimulatedMicrocontroller
Address Data
Editor KeilTM uVision®
Processor
Memory
I/O
RealMicrocontroller
StartDebugSession
StartDebugSession