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    EECS 105 Fall 1998

    Lecture 9

    MOS Capacitor in Depletion

    Now we make VGB> VFB. Note that thermal equilibrium falls into this range of

    applied bias.

    Surface potential at oxide/silicon interface is now positive --> n-type

    (slightly, ns= 1013cm-3).

    (x)

    -tox

    Xd

    x-qNa

    -tox Xd x

    E(x)

    0

    0

    QG

    -tox Xd

    x

    (x)

    0s= 185 mV

    VGB+ n+

    -500 mV

    500 mV

    1 V

    chargedensity

    electricfield

    potentialVGB

    9

    EECS 105 Fall 1998

    Lecture 9

    The Threshold Voltage VTn

    Keep increasing VGB--> surface potential keeps increasing. At some point, the

    surface is n-type (i.e., we say that it isinverted)

    The gate-bulk potential at the onset of inversion is called the threshold voltage,

    VTn. To find the threshold voltage, we need to consider the electrostatics in

    depletion (no electrons at the surface at the onset of inversion) -- with the surface

    potential equal to the opposite of the bulk potential:

    s max, p=

    -toxXd,max

    x

    (x)

    0

    s,max= - p = 420 mV

    VTn + n+

    -500 mV

    500 mV

    1 V

    1.5 V

    Vox

    VB,max

    VTn- VFB

    - p

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    EECS 105 Fall 1998

    Lecture 9

    Threshold Voltage Expression

    We can solve for the threshold voltage:

    The drop across the depletion region is

    The drop across the oxide for VGB= VTnis

    Substituting for the bulk charge (found from the potential drop across the

    depletion region, we find

    VT

    VFB

    Vox VB max,+=

    VB max, s max, p p p 2p= = =

    Vox Eox tox

    QB max,ox

    ----------------------

    tox

    QB max,

    Cox

    ----------------------= = =

    VTn

    VFB

    2 p

    1

    Cox

    --------- 2qsN

    a2

    p( )+=

    EECS 105 Fall 1998

    Lecture 9

    The Inverted MOS Capacitor (VGB>VTn)

    We consider the surface potential as fixed (pinned) at s,max = - 2p

    Inversion charge QNat SiO2- silicon surface balances extra + charge on gate as

    VGBincreases

    - tox

    Xd,max x

    (x)

    0

    500 mV

    - 500 mV

    1.0 V

    1.5 V

    s,max = 420 mV

    Vox

    VGB- VFB

    2 p

    QN

    Cox

    VGB

    VTn

    ( )=

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    EECS 105 Fall 1998

    Lecture 9

    Charge Storage in the MOS Structure

    Three regions of operation:

    Accumulation: qG= Cox(vGB- vFB) ... parallel plate capacitor

    Depletion: qG= - qB(vGB), with the bulk (depletion) charge in the

    silicon being a nonlinear function of vGB

    Inversion: qG= - qN- qB,max, where qB,max= qB(vGB= VT) is thedepletion charge at the onset of inversion and

    Sketch of the gate charge as a function of gate-bulk voltage:

    qG[C/cm2]

    VGB[V]VFB VTn

    EECS 105 Fall 1998

    Lecture 9

    MOS Capacitance

    The capacitance of the MOS structure is defined as

    From sketch, determine the slope and plot as the capacitance

    Cdq

    G

    dvGB

    -------------

    VGB

    =

    C [C/cm2]

    VGB[V]VFB VTn

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    EECS 105 Fall 1998

    Lecture 9

    Physical Interpretation of MOS Capacitance

    Accumulation: parallel plate capacitor --> C= Cox

    Depletion: increment in gate charge is mirrored at bottom of depletion region, so

    capacitance model is Coxin series with the depletion region capacitance Cb

    Inversion: bulk charge is no longer changing with VGB--> an increment in

    gate charge is mirrored in the inversion layer under the gate.

    The capacitance is therefore the same as in accumulation --> C= Cox

    Cox

    ox

    tox

    --------=

    Cb

    s

    Xd

    ------=

    gate

    Si/SiO2 surface

    bulk

    Note thatXdisa function of VGB

    C Cox

    Cb

    =

    EECS 105 Fall 1998

    Lecture 9

    MOS Field Effect Transistors

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    deposited

    oxide

    field

    oxide

    n+ drain diffusion

    drain

    interconnect

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    p+

    [ p-type ]

    bulk

    interconnect

    Ldiff

    gate contact

    (a)

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

    ,

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    A

    drain

    contacts

    bulk

    contact

    n+polysilicon gate

    ,

    ,

    ,

    ,

    ,

    active area (thin

    oxide area)

    polysilicon gate

    contact

    metal

    interconnect

    n+source diffusion

    edge of

    active area

    , ,

    source

    interconnect

    (b)

    L

    n+polysilicon gate

    ,

    ,

    ,

    ,

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    ,

    ,

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    gate oxide

    gate

    interconnect

    source contacts

    drain

    interconnectsource

    interconnect

    A

    W

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    EECS 105 Fall 1998

    Lecture 9

    MOSFET Circuit Symbols

    Two complementary devices (each with two symbols): both are very useful

    p-substrate (n-type channel under gate oxide)

    n-substrate (p-type channel under gate oxide)

    Fourelectrical terminals: source (lowest potential for n-channel, highest for p-

    channel), drain, gate, and bulk.

    Basic concept: inversion layer (called the channel) formed under gate betweensource and drain enables drift current

    n+

    n+

    p Bulk or

    Body

    Drain

    Source

    Gate

    (a) n-channel MOSFET

    D

    G

    IDp

    B

    p+

    p+

    n Bulk or

    Body

    Drain

    Gate

    (b) p-channel MOSFET

    Source

    +

    _ VSG

    D

    S

    G

    +

    +

    _

    VGS

    IDn IDn

    B

    VSD>0

    VDS >0

    +

    _VBS

    +

    _VSB

    D

    GB

    S

    S S

    B

    D

    G

    IDp

    EECS 105 Fall 1998

    Lecture 9