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Abstract—This paper presents a transformerless static

synchronous compensator (STATCOM) system based on hybrid multilevel H-bridge converter with delta configuration. This hybrid multilevel STATCOM is characterized by per-phase series connection of a high-voltage H-bridge converter operating at fundamental frequency and a low-voltage H-bridge converter operating at 5 kHz without any other circuit for DC voltage control. A new control strategy is proposed in this paper with focus on DC voltage regulation. Clustered balancing control is realized by injecting a zero-sequence current to the delta-loop while individual voltage control is achieved by adjusting the fundamental content of AC quasi-square-waveform voltage of high-voltage converter. A downscaled experimental prototype rated at 100V and 3kVA is constructed in author’s laboratory. Experimental results show that the hybrid multilevel STATCOM performs satisfactory not only improving efficiency and waveform quality , but also compensating reactive power and negative-sequence current while maintaining DC voltage at the given value.

Index Terms—Cascade H-bridge, STATCOM, DC voltage control, hybrid multilevel.

I. INTRODUCTION ascaded H-bridge converter with equal DC voltage has

been widely used for STATCOM application because of natural modular and high-quality output spectrum [1-7]

[25]. Compared with diode-clamped converter and flying capacitor converter, cascaded single-phase H-bridge converter saves a large amount of clamped diodes and flying capacitors [8]. However, further improvement of power efficiency and waveform quality is expected of cascade H-bridge topology in high power application [9]. Traditionally, low-distorted AC voltage waveform is achieved by either increasing switching Sixing Du is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xi’an, Shaanxi, 15289367159, China (e-mail: [email protected]).

Jinjun Liu is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xi’an, Shaanxi, 029-82665223, China (e-mail: [email protected]).

Jiliang Lin is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xi’an, Shaanxi, 029-82665223, China (e-mail: [email protected]).

Yingjie He is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xi’an, Shaanxi, 029-82665223, China (e-mail:[email protected]).

frequency or increasing the cascaded number of modules, which bring high power loss or high cost to the STATCOM system. Fortunately, hybrid multilevel technology provides a good tradeoff between waveform quality and switching loss [9]. The important advantages of hybrid multilevel converters are as follows: increasing voltage levels of output waveform, improving AC current quality, reducing switching frequency resulting in low switching loss, as well as enhancing converter efficiency.

As the concept of “hybrid multilevel” was proposed in literature [10], great attentions have been paid to this field. In order to achieve hybrid multilevel, many approaches have been published in literatures [11-22] [26] [27]. A hybrid topology with the series connection of three-phase full-bridge converter (two-or three-level) and single-phase H-bridge converter is adopted by literature [11-16][26][27]. This topology effectively produces higher voltage levels compared with traditional ones with the same number of switches, but it is companied by a problem of DC voltage control. One popular method for capacitor voltage control is selecting switching states redundancy [11] [12] [13], which introducing another problem of uncertain switching frequency for relevant devices. To avoid the issue of DC voltage control, DC link of the hybrid topology is connected directly to expensive DC supplies such as battery, fuel cell and rectifier[14][15][26]. In [16], three-phase three-level converter is fed by rectifiers while the H-bridge converter uses a capacitor as a replacement of DC source for cost saving. Capacitor voltage and NPC voltage is regulated by adjusting common mode voltage. This control algorithm requires a large amount of real-time online calculation, which brings difficulty for STATCOM application. In [27], all the DC-link voltages are controlled purely by control algorithm. Reactive-power regulation is realized by adjusting DC voltages. However, this control method is based on steady state model and the dynamic performance is not discussed. Additionally, the capability of compensating unbalanced load is not mentioned either.

Moreover, hybrid multilevel topology based on cascaded single-phase H-bridge converter with unequal DC voltage is considered by [17-22]. Literatures [17] [18] describe a motor drive system based on hybrid multilevel H-bridge converters with unequal DC voltage supplies. The mentioned control method is not suitable for STATCOM system because the DC sources are replaced by capacitors in STATCOM system. Literatures [19] [20] [21] provide new solution with

A Novel DC Voltage Control Method for STATCOM Based on Hybrid Multilevel

H-bridge Converter Sixing Du, Jinjun Liu, Senior Member, IEEE, Jiliang Lin, Yingjie He, Member, IEEE

C



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high-voltage converter fed by DC supplies and low-voltage converter fed by DC capacitor. In [19], diode-clamped H-bridge with multi-output boost rectifier functions as the high-voltage inverter. The utilization of clamped diode and rectifier increases the cost of whole system. In [20], DC voltage ratio of 4:2:1 is arranged to the series-connected H-bridge converters. The expensive isolated DC supplies are required for ratio-4 and ratio-2 converters. Fundamental frequency modulation is adopted by literature [21] for cascade hybrid H-bridge converters. In [21], selective harmonic elimination method is adopted for hybrid modulation and selecting switching redundant states is applied for capacitor voltage control. The quality of output voltage waveform is not good, which prevents this method for STATCOM application. Literature [22] proposes an active power filter system composed of three series-connected H-bridge converters with voltage ratio of 6:2:1.5, which is realized by control algorithm. However, DC voltage control strategy is not discussed in detail and three-phase performance is not verified by experiments.

Recently, some other interesting topologies have been published in [28]-[30]. In [28], a hybrid-source impedance networks with the DC-link of serious-connected z-sources is presented for enhancing the three-phase AC voltage levels, but it is not suitable for STATCOM application because of the utilization of large amount of DC sources. Literature [29] describes a multilevel circuit topology based on switched-capacitors and diode-clamped converters. The model related to switched-capacitor converters is given by literature [30]. This kind of converters can successfully produce high voltage levels and the issue with DC voltage balancing can be easily solved by choosing proper switching sequences. This structure requires a plenty of switching devices, so it haven’t widely accepted in medium-voltage application.

In this paper, the authors focused on the STATCOM application using hybrid multilevel converters. Delta-type cascaded Hybrid single-phase H-bridge topology is preferred because of modularity and simplicity. This paper proposed a new DC voltage control strategy for those hybrid multilevel converters. Clustered balancing control is achieved by injecting zero-sequence current to the delta-loop and the individual voltage control is realized by trimming the fundamental content of quasi-square-wave voltage of high-voltage converters. Compared with other hybrid multilevel approaches, this control strategy along with the STATCOM system has the advantages of fast-speed response to load change, accurate unbalanced load compensation, none auxiliary circuit for DC-links, less on-line calculation, specific unequal DC voltage regulation, as well as certain but unequal switching frequencies. The experiment results obtained from the downscaled prototype confirm the merits.

II. CONFIGURATION OF THE 100-V 3-kVA STATCOM SYSTEM

Fig 1 shows the configuration of a three-phase STATCOM rated at 100-V and 3-kVA, which is based on hybrid cascade

single-phase H-bridge cells. TABLEⅠsummarizes the circuit parameters. The cascade number of 2=N is assigned to the prototype because of the restriction of the author’s laboratory condition, resulting in 6 converter cells in total. In each phase cluster, one single-phase H-bridge cell is controlled as a high-voltage converter with DC-link voltage of 110V, and the other single-phase H-bridge cell acts as a low-voltage converter with DC-link voltage of 65V. The explanation of this arrangement is described in next section. Each cell is equipped with an isolating electrolytic capacitor with a capacitance value of 9400 μ F. No auxiliary circuit is connected to the six split DC capacitors except for six voltage sensors. An ac inductor is also required for each cluster to support the difference between the sinusoidal source voltage and the AC PWM voltage of cluster, and it also makes contribution in filtering out switch ripples caused by high-frequency modulation.

(a) Hardware of experimental STATCOM

ACL ACL ACL

sL

sR sR sR

MC1 MC1 MC1

MC2 MC2 MC2

cui cvi cwi

iuv ivv iwv

1cuv

2cuv

C

C

C

C

C

C

1cvv

2cvv

1cwv

2cwv

Fig 1. 100-V 3-kVA downscaled STATCOM. (a) Experimental hardware view. (b) Configuration of experimental system.

In experiment, switching frequencies of 50 Hz and 5 kHz are

assigned to high-voltage converter and low-voltage converter respectively. The constant DC voltages are achieved purely by control algorithm. This design is reasonable to verify the improvement of output voltage waveform and the performance



3

of the 100-V 3-kVA STATCOM system, because these special characteristics mainly relay on control strategy.

TABLE Ⅰ. Circuit parameters in fig 1

Nominal line-to-line rms voltage scasbcsab vvv ,, 100 V

Power rating P 3kVA AC inductor

ACL 6mH

Starting resistor sR 51 Ω

Back ground inductance sL 0.3mH

DC voltage for cell u1,v1,w1 111 ,, cwcvcu VVV 110V

DC voltage for cell u2,v2,w2 222 ,, cwcvcu VVV 65V

DC capacitor C 9400 μ F Switching frequency for cell u1,v1,w1 50Hz

PWM carrier frequency for cell u2,v2,w2 5000Hz

sL ACL

FPGA(PWM)

PT

PLL A/D

DSP

HybridH-bridge

converters

3

3 3 3 6

12

624

100V,50Hz

Fig 2. Fully digital control system for 100-V 3-kVA STATCOM

As is shown in fig.2, this experimental system is totally

controlled by a fully digital controller using a 32-bit digital signal processor (DSP) and field-programmable gate arrays (FPGA). Most of the calculation is dealt with by the DSP chip and the hybrid modulation strategy is implemented on FPGA chip. The gating signals for all the switching devices are generated by the hybrid modulation, which matches the 10-kHz sample frequency well.

Hybrid modulation shown in fig. 3 includes two parts: fundamental modulation and PWM modulation. The fundamental modulation could be simply described as: when the sinusoidal command is higher than a threshold value of cmpV , the high-voltage converter output positive voltage; as

the sinusoidal command is lower than the negative threshold value of cmpV− , the high-voltage converter output negative

voltage; if the sinusoidal command is in the range between cmpV− to cmpV , the high-voltage converter outputs zero. The

remaining part of sinusoidal command and the quasi-square-waveform voltage is the comand voltage for low-voltage converter. It is modulated by single-polar PWM modulation technology with the carrier frequency of 5 kHz. Based on this modulation strategy, an AC waveform with higher voltage levels is produced. It brings the advantages of improving output quality, keeping high equivalent switching frequecy, and reducing power loss.

iuv

cmpV

cmpV−tω

tω

tω

tω

u

0

u

0

0

0

1cuV

1cuV−

2cuV−

2cuVu

u1iuv

2iuv

π π2

π π2

π π2

π π2

Fig 3. Diagram for hybrid modulation

III. MATHEMETIC ANALYSIS OF CAPACITOR VOLTAGE CONTROL

A. Fundamentals of circuit operation In each cluster, the high-voltage converter output

quasi-square-waveform while the low-voltage converter output the remaining part between sinusoidal command and the quasi-square-waveform shown in fig.4. Therefore, low-frequency contents in total AC voltage are completely eliminated. The total AC voltage only includes fundamental component and harmonic components around switching frequency. Three-phase smooth sinusoidal currents are guaranteed because the high-frequency components can be easily filtered by interface inductors. The sharp change of load can be well followed by dynamically trimming the sinusoidal command voltage, which ensures the fast-speed response.

As the issue with DC voltage control is also very crucial for safe operation. DC voltage control strategy is also investaged in this paper. As is shown in fig.4, a fundamental-frequency zero-sequence current is suggested to the delta-loop for balancing of DC voltages among three phases. This clustered balancing method enables the STATCOM system to compensating unbalanced load. Moreover, unequal DC voltages of high-voltage converter and low-voltage converter are achieved by the effert of individual voltage control, which suggests a small trim to the fundamental contents of quasi-square-waveform voltage of high-voltage converter for



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active-power redistribution between high-voltage and low-voltage converters. In the whole process, the low-voltage converter always compensates the remaining part to match the sinusoidal command. Additionally, the sum of all capacitor voltages is regulated by the algorithm of overall voltage control.

1iuv2iuv

2ivv

sav

1ivv

2iwv

1iwvsbv

scv

iuv

ivv

iwv

sav

sbv

scv

oi

Fig 4. Three-phase equivalent circuit

B. Injection of zero-sequence current for clustered balancing control The command zero-sequence current with the symbols of oI

and oϕ could be written as: )sin( ooo tIi ϕω += (1)

Where oI and oϕ are the magnitude and original phase angle respectively. The average power redistributed by zero-sequence current is expressed as:

)3

2cos(2

1

)3

2cos(2

1

)cos(2

1

πϕ

πϕ

ϕ

−=⋅=

+=⋅=

=⋅=

∫

∫

∫

+

+

+

oTst

tos

oscas

oca

oTst

tos

osbcs

obc

oTst

tos

osabs

oab

IVdtiv

Tp

IVdtiv

Tp

IVdtiv

Tp

(2)

Where sV is magnitude of line-to-line grid voltage; sT is a line period. sabv , sbcv , scav are the three-phase line-to-line voltage. The sum of the three equations in (2) equals to zero, which indicates that zero-sequence current just causes the redistribution of active power among three clusters without any influence on total active power. The redistributed power could be used for canceling that caused by unbalanced compensating current, as well as for providing proper amount of power for balancing of DC voltages among three clusters. Therefore, the average power could be expressed as:

cancaoca

bcnbcobc

abnaboab

ppp

ppp

ppp

Δ+=

Δ+=

Δ+=

(3)

Where, terms of nabp , nbcp , ncap are used for power cancellation and terms of abpΔ , bcpΔ , capΔ are used for balancing of DC voltages among clusters. For simplification, the clustered balancing control considers a cluster of series-connected converters as one equivalent single-phase H-bridge converter. The mathematic relationship between the clustered capacitor voltage and active power is calculated by:

c

cucucucuab R

vVdt

dvVCp

⋅⋅+⋅=Δ

2 (4)

Where cR is the equivalent parallel resistance of u-phase cluster, which represents the power loss of u-phase converters. Equation (5) gives the transfer function, which is obtained by applying Laplace transformation to (4). According to (5), the regulator for clustered balancing control could be designed.

cucuab

cuvp VsRCV

Rp

vG

2+=

Δ= (5)

In practice, the amount of active power redistributed by zero-sequence current is calculated by close-loop based regulator. Once the required power is determined, the command zero-sequence current can be obtained by solving equation (2). The magnitude oI and original phase angle oϕ are derived by:

)]2

1(3

1[tan

)2(31)(2

1

22

oab

obco

obcoaboabs

o

pp

pppV

I

⋅+−=

⋅++=

−ϕ (6)

C. Trimming fundamental content of quasi-square-waveform for individual voltage control As the clustered DC voltage are controlled and maintained,

the individual control become necessary because of the different power loss between high-voltage converter and low-voltage converter. Due to the symmetry of structure and parameters among the three phases, u-phase cluster was taken as an example for individual control analysis.

As is shown in fig.5, the fundamental voltage and input current of u-phase cluster could be assumed as:

)sin( iuiuiu tVv ϕω −= (7) )cos( cuccu tIi ϕω −= (8)

During one line period, the average power absorbed by the high-voltage converter could be calculated as:

)2

sin()sin(2

)(1

1

2/2/3

2/2/3 12/2/

2/2/ 11

aiucuccu

W

W cucuW

W cucus

iu

WIV

dtiVdtiVT

p aiu

aiu

aiu

aiu

ϕϕπ

πϕ

πϕ

πϕ

πϕ

−⋅⋅=

⋅+⋅= ∫∫++

−+

++

−+

(9)



5

t

i/u

0

iuϕ

2/2/ aiu W−+πϕ

2/2/ aiu W++ πϕ

iuv

cuicuϕ

cuϕπ +2/πϕ +iu

cmpV

Fig.5 Mathematic analysis for individual control

Where, 1cuV is the high-voltage DC-link; cI is the magnitude

of input current; cuϕ is the original phase angle referring to the pure reactive current, which is introduced to represent the active power absorbed by high-voltage converter; iuϕ is also a original phase angle respecting to the source voltage; aW is the pulse width of the quasi-square-waveform voltage of high-voltage converter. Equation (9) implies that the active power of high-voltage converter is affected by 1cuV , cI , cuϕ ,

iuϕ and aW . Actually, cI and cuϕ are decided by the reference current. Therefore, iuϕ and aW are the only factors that could be used for adjusting DC voltage of high-voltage converter. In this paper, the adjustment of both iuϕ and aW is preferred, which is realized by trimming the modulated waveform along the direction of input current cui .

As is shown in fig.5, the mathematic relationship between threshold value cmpV and pulse width aW could be expressed

as:

⎪⎩

⎪⎨⎧

=−+

=−

22

)sin(

0

0

aiu

cmpiuiuW

t

VtV

ωϕπϕω

(10)

By solving equation (10), the result is obtained by:

iu

cmpiuaV

VVW22

)2

sin(−

= (11)

Substituting (11) into (9), average power obtained by the high-voltage converter can be rewritten by:

iu

cmpiuiucuccuiu V

VVIVp

22

11 )sin(2 −−⋅⋅= ϕϕ

π (12)

The average power calculated by the modulated waveform is expressed as:

)sin(21)(1*

1 iucuciuTt

t cuius

iu IVdtivT

p s ϕϕ −⋅⋅=⋅= ∫+

(13)

The relationship between the average power absorbed by the high-voltage converter and the power calculated by the

modulated waveform is got by:

2

22

1*1

1 4

iu

cmpiucu

iu

iuvalue

V

VVV

p

pC

−==

π (14)

iuϕ

2/2/ aiu W−+ πϕ

2/2/ aiu W++ πϕ

iuv

cuicuϕ

cuϕπ +2/πϕ +iu

cmpV

iuv′

θ

Fig. 6 The modulation of the high-voltage converter for DC voltage control According to (14), the average power absorbed by

high-voltage converter could be easily obtained by calculating the modulated waveform. In order to control the capacitor voltage of high-voltage converter, the modulated waveform can be changed as:

)cos()sin( cuciuiucuiuiu tIetVievv ϕωϕω −⋅Δ+−=⋅Δ+=′ (15)

Where, eΔ is the trimming amplitude along the direction of input current. The modulated waveforms before and after change are shown in fig. 6. And then, the power calculated by the modulated waveform is obtained by:

2*1

*1 2

1)(1ciu

Tt

t cuius

iu IepdtivT

ps

⋅Δ+=⋅′= ∫+′ (16)

Based on (14), the average power absorbed by high-voltage converter is rewritten as:

valueciuiuvalueiu CIeppCp ⋅⋅Δ+=⋅=′ ′ 21

*11 2

1 (17)

Therefore, the change of power for high-voltage converter could be obtained:

2

22

12

12

iu

cmpiucuciu

V

VVVIep

−⋅⋅Δ=Δ

π (18)

The mathematic relationship between the power and the capacitor voltage is calculated by:

RvV

dtdvVCp cucucu

cuiu111

112 ⋅⋅+⋅=Δ (19)

Where R is the equivalent parallel resistance of DC capacitor. The transfer function is obtained by applying Laplace transformation to (18) and (19).

2

2 2

2

221

+⋅

⋅−

=Δ

=RCs

IR

V

VV

ev

G c

iu

cmpiucuvh

π (20)

When the clustered DC voltage and the high-voltage DC-link



6

are regulated, the low-voltage DC-link would be automatically maintained at the expected value because it equals to the difference between the clustered DC voltage and the high-voltage DC-link. According to (20), the individual voltage control algorithm is designed.

D. Design of DC capacitor voltages In each phase cluster, the high-voltage converter and

low-voltage converter complement each other to produce the sinusoidal command voltage. Therefore, the low-voltage DC-link illustrated in fig.7 must be higher than the difference of sinusoidal command and quasi-square-waveform to guarantee the safe operation. Taking u-phase cluster for an example, the constraint can be described as:

⎪⎪⎩

⎪⎪⎨

⎧

<=<−=+<<

22

211

21*

1

cucmpx

cucmpcux

cucucu

VVVVVVVVVVV

iu

(21)

Where, 1cuV is the high-voltage DC-link; 2cuV is the

low-voltage DC-link; *iu

V is the magnitude of the sinusoidal

command; cmpV is a constant threshold value. Inequality (21)

could be rewritten as:

⎪⎪⎩

⎪⎪⎨

⎧

<<−⋅<

+<<

221

21

21*

12

cucmpcucu

cucu

cucucu

VVVVVV

VVVViu

(22)

cmpV

1cuV

21 cucu VV +2cuV

21 cux VV <

22 cux VV <

cmpV−

1cuV−

21 cucu VV −−

0

*iuv

2/3π2/π

Fig. 7 Principle for DC voltage decision Based on (22), the reference value can be assigned as

VVcu 1101 = , VVcu 652 = and VVcmp 55= . This voltage ratio

of 21 : cucu VV is close to 2:1, but there is a small margin of VVV cucu 102/21 =− . This small margin is essential for individual voltage control. As a result, nine voltage levels of 0V, ±45V, ±65V, ±110V, ±175V are produced by each cluster. Although unequal steps exist, the output spectrum is still improved compared with the traditional 5-level waveform.

IV. CONTROL STRATEGY Fig 8 shows a block diagram of the control algorithm

proposed in this paper. The whole control algorithm consists of four parts, namely, decoupled current control, overall voltage control, clustered balancing control and individual voltage control.

lailbilci

drefi

qrefi

qd −

qd −

dcrefi

refdcV _

1cuv2cuv1cvv2cvv1cwv2cwv

sabvsbcvscav

cuicvicwi

sdvsqv

diqi

oi*iu

v*iv

v

*ov

1iuv2iuv1ivv2ivv1iwv2iwv

*di

*qi

*iw

v

Fig 8. Block diagram of the total control scheme for 100-V 3-kVA STATCOM

A. Decoupled current control Referring to fig 1, the set of voltage-current equation can be

obtained as follows:

iwscacwLcw

AC

ivsbccvLcv

AC

iusabcuLcu

AC

vviRdt

diL

vviRdt

diL

vviRdt

diL

−=+

−=+

−=+

(23)

Where LR is the equivalent series resistance (ESR) of the inductor. Applying the qd − transformations (23), the equations in qd − axis are derived:

iqsqqLdACq

AC

idsddLqACd

AC

vviRiLdt

diL

vviRiLdt

diL

−=+⋅+

−=+⋅−

ω

ω (24)

The proportional and integral (PI) regulators with parameters of ipk and iik are introduced for close-loop current control.

Parameters of ipk and iik are given in Table-II. The command

voltages in d -axis and q -axis are given by:

))((

))((

*

*

qqii

ipsqdACiq

ddii

ipsdqACid

iis

kkviLv

iis

kkviLv

−+−+⋅−=

−+−+⋅=

ω

ω (25)

Here, di and qi are the feed back currents in d -axis and

q -axis respectively. *di and *

qi are the d -axis and q -axis

reference currents. The three-phase command voltages *iuv , *

ivv



7

and *iwv can be obtained by applying the inverse qd −

transformations to idv and iqv as shown in fig 9.

sdv

sqv

*di

*qi

di

qiACLω

ACLω

idv

iqv

*iu

v

*iv

v

*iw

v

qd −

Fig 9. Block diagram of decoupled control

Command current generating algorithm intended for detecting reactive and negative-sequence load current includes two parts, reactive current algorithm and the negative-sequence current algorithm. These two parts are all based on qd − transformations and moving average low-pass filter (LPF). The main difference between them is that the negative-sequence current algorithm needs to change the position of b -phase current and c -phase current when applying qd − transformations. As is shown in fig 10, the upper algorithm is for reactive current detection and the lower algorithm is for negative-sequence current detection. The three-phase line current *

lai , *lbi , *

lci ought to be transformed into phase current because of the delta configuration of the three clusters. Fig 11 shows the diagram for this transformation. One of the solutions as described in (26), is preferred because of its independence from the zero-sequence current [23].

3/)(

3/)(

3/)(

**

**

**

lalcvref

lclbwref

lblauref

iii

iii

iii

−−=

−−=

−−=

(26)

qd −qd −

qd −qd −qd −

Cac

ulat

ion

(Eq.

20)

+

+

++

+

lailbilci

+drefi

qrefi

*lai

*lbi

*lci

urefivrefiwrefi

Fig 10. Block diagram of command current generating algorithm

*lai

*lbi

*lci

urefi

vrefi

wrefi

Fig 11. Diagram for the transformation from line current to phase current

B. overall voltage control

+−

dcrefiskk vivp /+−

refdcV _

sumdcv _ Fig 12. Block diagram of overall voltage control.

Fig 12 shows the overall voltage control diagram. refdcV _ is

the reference value for the sum of all the dc capacitors’ voltage. sumdcv _ acts as the feedback, which is obtained by summing

up all the dc capacitors’ voltage. PI regulator is preferred for overall control. The regulator design process for vpk and vik is

similar to literature [24]. The output of PI regulator is the active component of command current.

C. Clustered balancing control.

orefi *ou

tωsin tωcos

ioi

oabp

obcp

avedcv _

cuv

cvv

iok

Fig 13. Clustered balancing control among the three clusters by introducing a zero-sequence current, where each of the three clusters is considered as

single-phase H-bridge converters. Fig 13 shows the block diagram of clustered balancing

control. Two PI regulators with constant parameters are adopted for calculating the amount of power for redistribution. The reference zero-sequence current is synthesized based on equation (1) (6). Referring to (3) (5), the close-loop control is formed in fig.14. Where cuV is the total DC voltage of u-phase

cluster at steady state operating point; ∧cuv is the small voltage

change around cuV .

cucu VsRCVR

2+sk

k oiop +

∧cuv

avedcv _ cuvΔ

cuv

cuVoabp

nabp

abpΔ

Fig 14. Block diagram of clustered balancing control

The closed-loop transfer function is obtained by:

oiopcucu

oiop

avedc

cu

RksRkVsRCV

RksRkv

v+++

+=

)2(2_ (27)

Based on (27), the parameters of opk and oik for PI

regulators are designed and the design processing can be found in the literature [24]. The parameters are given in Table-II.



8

D. Individual voltage control.

refcuv _1

1cuvcui

1cuV

cmpV

iuv

1iuveΔ

2uS

1uS

+−

++

+

−2iuv

Fig 15. Individual voltage control, taking u -phase cluster for example. Fig 15. shows the block diagram of the individual voltage

control. Let 1cuuΔ be the difference between the reference voltage and the capacitor voltage of high-voltage converter:

1_11 curefcucu vvv −=Δ (28)

After introducing the proportional regulator pk , the close-loop control based on (20) is formed in fig.16. Where

∧1cuv is the small voltage change around 1cuV .

2

2

1

21

2

22

+⋅⋅⋅

−

sRCVIVR

V

VV

cu

ccu

iu

cmpiu

πpk

∧1cuvrefcuv _1 1cuvΔ

1cuv

1cuV

eΔ

Fig 16. Block diagram of individual voltage control The closed-loop transfer function is obtained by:

42 21

2

_1

1

++=

cpvaluecu

cvaluep

refcu

cu

IkRCsRCV

ICRkv

v (29)

Based on (29), the regulator pk is designed and the design

processing can be found in the literature [24].

TABLE II. CONTROL GAINS AND PARAMETERS Symbols Experiment Symbols Experiment

vpk 0.1A/V vik 0.3A/V

ipk 25V/A iik 166V/A

opk 0.3A/V oik 1.5A/V

iok 2V/A pk 0.5A/V

V. EXPERIMENT RESULTS

(CH1: source voltage, sabv ; CH2: output voltage of u-phase cluster iuv ; CH3:

output voltage of cell u2 2iuv ; CH4: output voltage of cell u1 1iuv ) Fig 17. Experiment waveforms testing for the hybrid modulation

(a)

(CH1: source voltage sav ; CH2: STATCOM line-current cai (1A/10mV);

CH3: capacitor voltage 2cuv ; CH4: capacitor voltage 1cuv )

(b)

(CH1: capacitor voltage 1cvv ; CH2: capacitor voltage 2cvv ; CH3: capacitor

voltage 2cuv ; CH4: capacitor voltage 1cuv ) Fig 18. Experiment waveforms testing for individual balancing control with

high-DC link-voltage 110V and low-DC link-voltage 65V Fig.17 shows the experiment results verifying the effect of

hybrid modulation. As the DC voltage of the high-voltage converter maintains at 110V and those of the low-voltage converter stays at 65V, 9-level voltage waveform is produced. The voltage steps of 45V and 65 are close to each other, so it



9

looks like a 7-level voltage waveform. The quasi-square-waveform voltage of the high-voltage converter and the 3-level PWM-waveform voltage of low-voltage converter are also generated as expected. This hybrid modulation scheme is effectiveness in both of producing high-quality low-harmonic output voltage and reducing the power loss of high-voltage converters

Fig 18. shows the experiment waveforms in capacitive operation at *q =-2.2kVA. At the beginning of the experiment, individual voltage control is not applied while other controls remain active. The DC voltages of both the high-voltage converter and the low-voltage converter could not maintain at the given values. After a short time period of 20 seconds, the individual voltage control is enabled and the two DC voltage waveforms return to the given values quickly. Because the scope is limited to 4 channels, only the DC-link voltages of u-phase cluster and v-phase cluster are shown in fig.18 (b). This experiment verifies that the individual voltage control is effective for regulating individual DC voltages.

(a)

(CH1: source voltage sav ; CH2: capacitor voltage 2cuv ; CH3: STATCOM

line-current cai (1A/10mV); CH4: capacitor voltage 1cuv )

(CH1: capacitor voltage 2cuv ; CH2: capacitor voltage 2cvv ; CH3: capacitor

voltage 1cvv ; CH4: capacitor voltage 1cuv ) Fig 19. Experiment waveforms testing for clustered balancing control

Fig.19 shows the experiment waveforms for testing clustered

balancing control. At the beginning of the experiments, clustered balancing control is intentionally disabled while other controls are still enabled. The waveforms of DC voltages show clearly as four different curves in fig.19(b), and the DC

voltages of three clusters is not maintained at the given values. After a short time period of 20 seconds, the clustered balancing control is triggered and the 4 curves converge as two quickly. The experiment verifies that the clustered balancing control is effective for balancing DC voltages among three clusters.

(CH1: source voltage sabv ; CH2: output voltage iuv ; CH3: STATCOM

phase-current cui (1A/10mV); CH4: reactive power *q (kVA/div)) Fig 20. Experiment waveforms in a transient state from inductive to

capacitive operation at 2.2kVA. The dynamic performance of the hybrid multilevel

STATCOM is also tested. Fig 20 shows the experiment waveforms in a transient state from inductive to capacitive operation from *q =-2.2kVA to 2.2kVA with a sharp change. Dynamic response is very fast. During the transient state, whole system works well with 9-level output voltage. Note that a small degree of distortion exist in the STATCOM phase-current cui . The explanation is that cui is clustered current which includes the distorted circulation current. It does not affect the line current because the circulating current is not injected to the network.

Fig 21. Confirms the compensation effectiveness when the three-phase load is balanced. As is shown in fig.21 (a), the STATCOM system is enabled for 100ms. During this interval, the RL load is sufficiently compensated. After compensation, source side current keeps in phase with source voltage. Fig.21 (b) shows that when the STATCOM system is in run mode, DC voltage is maintained at the given value and the fast response is ensured. Phase B and C have the same compensation effect, but only A-phase curves are demonstrated due to the limitation of 4 channels of the scope.

Fig 22. Confirms the effect of unbalanced load compensation. As is shown in fig 22(a), a great difference exists in the magnitudes of the STATCOM current. Because of the limitation of scope, only the current of cai and cbi are shown. During the compensating process, the dc mean voltage of capacitors stays at the reference value of 110V and 65V respectively in fig22 (b). In order to compensate unbalanced load, the STATCOM output unbalanced line current to network while a zero-sequence current is produced by the clustered balancing control to keep the equal DC voltages of the three clusters. After compensation, the source side currents have the same magnitude and keep in phase with the grid voltages



10

respectively in fig 22(c). The power quality is greatly improved with the power factor being unit.

(a)

(CH1: source voltage sav ; CH2: source side current sai (1A/10mV); CH3:

load current lai (1A/10mV); CH4: STATCOM line-current cai (1A/10mV))

(b)

(CH1: source voltage sav ; CH2: capacitor voltage 2cuv ; CH3: capacitor

voltage 1cuv ; CH4: STATCOM line-current cai (1A/10mV)) Fig 21. Experiment waveforms verifying the effect of compensating balance

load.

(a)

(CH1: source voltage sav ; CH2: STATCOM line-current cbi (1A/10mV);

CH3: source side current sai (1A/10mV); CH4: STATCOM line-current

cai (1A/10mV))

(b)

(CH1: capacitor 2cuv ; CH2: capacitor voltage 1cuv ; CH3: STATCOM

line-current cbi (1A/10mV); CH4: STATCOM line-current cai (1A/10mV))

(c)

(CH1: source voltage sav ; CH2: source current sbi (1A/10mV); CH3: source

current sai (1A/10mV); CH4: STATCOM line-current cai (1A/10mV)) Fig 22. Experiment waveforms verifying the effect of compensating serious

unbalance load.

(CH1: source voltage sav ; CH2: output voltage iuv ; CH3: capacitor 1cuv ;

CH4: STATCOM line-current cai (1A/10mV)) Fig 23. Experiment waveforms confirm the control effect when source

voltage sag. Fig.23 confirms the effectiveness of DC voltage control

when source voltage sag happens. As is shown in fig.23, DC voltage keeps constant during the interval of source voltage sag, and the compensating current is not affected because of the source voltage feed forward. The DC voltage control method is effective when source voltage is either normal or sag.



11

VI. CONCLUSION This paper has analyzed the fundamentals of DC voltage

control based on cascaded hybrid multilevel H-bridge converters. And then, a hybrid modulation for hybrid multilevel converter has been proposed and the control algorithm has also been designed in details. The control scheme proposed in this paper is characterized by the capability of maintaining the unequal DC voltage at the given value without any additional circuit, as well as by the ability of compensating serious unbalanced load. This control strategy has taken full advantages of the available switching devices by operating the high-voltage device at low switching frequency and low-voltage device at high frequency. This control method along with the STATCOM system has the merits of producing high-quality output waveforms, reducing switching loss and improving whole system’s efficiency. Experimental results obtained from a 100-V 3-kVA laboratory downscaled model have verified the effect of DC voltage control, dynamic performance of compensating seriously unbalancing load.

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Sixing Du was born in Nanyang, Henan, China. He received the B.S. degree in electrical engineering from Taiyuan University of Science and Technology, Taiyuan, China, in 2009. And then, He received the M.S. degree in electrical engineering from Xi’an Jiaotong University in 2011, where he is currently working toward the Ph.D. degree in electrical engineering.

His main field of interest includes the hybrid multilevel, multilevel converter, power quality and the applications of power electronics in power systems.

LIU Jinjun (M’97-SM’10 ) received his B.S. and Ph.D. degrees in Electrical Engineering from Xi’an Jiaotong University (XJTU), China in 1992 and 1997 respectively.

He then joined the XJTU Electrical Engineering School as a teaching faculty. In 1998, he led the founding of XJTU/Rockwell Automation Laboratory and served as the lab director. From 1999 until early 2002, he was with the Center for Power Electronics Systems at Virginia Polytechnic Institute and State University, USA, as a visiting scholar. He then came back to XJTU and in late 2002 was promoted to a Full Professor and the head of the Power Electronics and Renewable Energy Center at XJTU. During 2005 to early 2010, He served as the Associate Dean for the School of Electrical Engineering at XJTU. Now he also serves as the Dean for Undergraduate Education at XJTU. He coauthored 3 books, published over 100 technical papers, holds 8 patents, and received several national, provincial or ministerial awards for scientific or career achievements and the 2006 Delta Scholar Award. His research interests are power quality control, renewable energy generation and utility applications of power electronics, and modeling and control of power electronic systems.

Dr. Liu is an AdCom member of the IEEE Power Electronics Society and serves as Region 10 Liaison. He also serves as an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS. He is an AdCom member and the Chair of Student Activities Committee for IEEE Xi’an Section. He is on the Executive Board and serving as a Deputy Secretary-General for the China Power Electronics Society, and also on the Executive Board and serving as a Deputy Secretary-General for the China Power Supply Society.

Jiliang Lin was born in Anhui Province,China in 1984. He received his B.S.from the Northeast Dianli University of Automation Engineering ,China in 2007. And is currently pursuing the M.S degree in the school of Electrical and Electronic Engineering, Xi’an Jiaotong University, Xi’an.

His research interest include power quality control, multilevel inverters and the applications of power electronics in power systems.

Yingjie He was born in Henan Province,China in 1978.He received his B.S,M.S.and Ph.D.from the Huazhong University of Science and Technology, China in 1999,2003,and 2007,respectively. From May 2007 until May 2009, he was with the Power Electronics and Renewable Energy Center at Xi’an Jiaotong University, China, as a Postdoctoral Research Scholar. He is currently a Lecturer at Xi’an Jiaotong University.

His research interest include power quality control, multilevel inverters and the applications of power electronics in power systems.

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equivalent

short time

source impedance

renewable

clustered

average power

unequal dc

clustered