08 expansion buses, cables & connectors
DESCRIPTION
08 Expansion Buses, Cables & ConnectorsTRANSCRIPT
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Revision no.: PPT/2K403/02
Expansion Buses,Cables & connectors
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Development of Expansion Buses
The CPU, Random Access Memory (RAM), keyboard,
network interface card (NIC), sound card, and so forthis
connected to the external data bus.
The CPU speeds continually increased as technology has
improved, the speeds of expansion cards has remained
relatively constant.
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Development of Expansion Buses (contd.)
It was not practical to redesign and replace every
expansion card each time a new processor was released.
To Overcome this problem the external data bus was
divided into two parts:
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Development of Expansion Buses (contd.)
System bus. This supports the CPU, RAM, and other
motherboard components and runs at speeds that support
the CPU.
Expansion bus. This supports any add-on devices by means
of the expansion slots and runs at a steady rate, based on
the specific bus design.
Dividing the bus enhances overall system efficiency.
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Development of Expansion Buses (contd.)
Interface Slots
Slots also termed as Buses.
Bus transports data among the processor and other components.
Bus is a complex combination of electrical CKTS called traces.
Bus includes assorted Microchips and the slots connectors in which we plug expansion CKT boards. Often called as
adapters or expansion cards.
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Development of Expansion Buses (contd.)
ISA(Industry Standard Architecture)Bus
8-bit industry standard architecture bus used on the original
8088 PC. It speed was 4.77Mhz.
In 1984, IBM released the AT (Advanced Technology) PC,
having Intel's 80286 16-bit processor.
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Development of Expansion Buses (contd.)
A new expansion bus was released that was compatible with
previously released devices.
It allowed insertion of either an 8-bit card or a 16-bit
card,which resulted in the standard 16-bit ISA slot. It ran at a
top speed of 8.33 MHz.
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Development of Expansion Buses (contd.)
Black in color Present in AT machine except for some of the Motherboards
series of 810 chipset and above.
It is 62+36=98 pins.
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Picture of isa bus
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Picture of isa bus (contd.)
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Picture of isa bus (contd.)
Problems with ISA Design
ISA Bus had two shortcomings:
1) Lack of Speed.
2) Compatibility Problems due to card design.
Micro channel architecture (MCA) bus It is a proprietary IBM PS/2 bus which had a width of 32 bits.
It top speed was at 10MHZ.
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Picture of isa bus (contd.)
It allowed self configuration of devices on the slot.
MCA devices has configuration disk which allows the automatic configuration of IRQ, I/O addresses and DMA channels.
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Picture of isa bus (contd.)
Problems with MCA design
It was not compatible with older ISA Cards.
It was more expensive than other cards.
EISA(Extended Industry Standard Architecture)
It supports 32 bit data transfer.
Permitted speeds from 8.33 to 20 MHz.
It is brown in colour.
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Picture of isa bus (contd.)
EISA is an improved variation of the ISA slot in which older ISA cards can be inserted.
It has a two-step design that uses a shallow set of pins to attach to ISA cards and a deeper connection for attaching
to EISA cards.
It is faster than ISA and MCA cards.
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Picture of isa bus (contd.)
It supports only those cards designed specifically to work with EISA slots.
It has 188 pins.
EISA cards in EISA slots could be configured only through jumper settings.
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Picture of isa bus (contd.)
EISA(Extended Industry Standard Architecture)
Cross Section of ISA and EISA bus
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Vesa (Video Electronics Standard Association)
It was basically designed for improving the performance of graphics adapter.
It Permitted speeds up to 33MHz.
It is Brown in color.
Present in AT 386, 486 Machines.
It consists of 112 pins
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Vesa (Video Electronics Standard Association) (contd.)
It supports 32 bit data transfer.
Cards designed for VESA Bus are connected directly to the
system-bus side of the PC's external data bus.
It provides two performance boosting features
Burst mode
Bus Mastering
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Vesa (Video Electronics Standard Association) (contd.)
In burst mode, VLB devices gain complete control of the
external data bus for up to four bus cycles, passing up to
16 bytes (128 bits) of data in a single burst.
Bus mastering allows the VLB controller to arbitrate data
transfers between the external data bus and up to three
VLB devices without assistance from the CPU.
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Vesa (Video Electronics Standard Association) (contd.)
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.
Vesa (Video Electronics Standard Association) (contd.)
-
Revision no.: PPT/2K403/02
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S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
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.
N
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.
Peripheral Component Interconnect
It supports 32 bit as well as 64 bit data transfer.
It permits speeds up to 38/48/66 MHz.
It latest speed goes up to 133 MHz
It consists of 120 pins
It is usually white in color.
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S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
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.
N
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p
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r
m
i
s
s
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n
.
Peripheral Component Interconnect (contd.)
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Revision no.: PPT/2K403/02
C
M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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h
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.
N
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p
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m
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n
.
Top View of PCI Slot
-
Revision no.: PPT/2K403/02
C
M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
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.
N
o
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p
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r
m
i
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s
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n
.
Top View of PCI Slot (contd.)
PCI design allows more than three slots.
The PCI bus has its own set of four interrupts, which are mapped to regular IRQs on the system.
If a PC has more than four PCI slots, some will be sharing interrupts and IRQs.
Auto configuration allows the BIOS to assign the IRQ linking the card to the system bus.
PCI cards have no switches or jumpers to set, speeding installation and preventing many hardware conflicts.
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Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
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.
N
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p
r
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r
m
i
s
s
i
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n
.
Top View of PCI Slot (contd.)
Data Transfer Rate of PCI Bus
-
Revision no.: PPT/2K403/02
C
M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
s
r
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s
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.
N
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p
r
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r
m
i
s
s
i
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n
.
Accelerated Graphics Port
Intel developed the Accelerated Graphics Port (AGP).
Memory allowing the system Ram to be used as graphics Ram.
It provides a direct path to the system memory for handling graphics. This procedure is referred to as Direct
Memory Execute (DIME).
AGP slots interface operate at minimum speed of 66 MHz.
Usually brown in color
-
Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
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.
N
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p
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m
i
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s
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n
.
Accelerated Graphics Port (contd.)
There are three modes of AGP 1x mode. 2x mode. 4x mode. It offers a maximum speed of 1066MBps.
-
Revision no.: PPT/2K403/02
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E
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2
0
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.
A
l
l
r
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g
h
t
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.
N
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m
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n
.
Accelerated Graphics Port (contd.)
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Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
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.
N
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.
Accelerated Graphics Port (contd.)
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Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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.
N
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.
Accelerated Graphics Port (contd.)
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Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
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t
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.
N
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n
. IEEE 1394 Fire Wire High-Performance Serial Interface
IEEE 1394, also known by its Apple trade name of Fire Wire.
Its high-speed serial interface allows up to 62 devices on a chain, at data transfer rates of up to 50 MB per second.
It offers several features such as hot swap capability (the ability to add and remove components while the machine is
running), small and inexpensive connectors, and a simple
cable design.
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Revision no.: PPT/2K403/02
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M
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I
N
S
T
I
T
U
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E
,
2
0
0
4
.
A
l
l
r
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g
h
t
s
r
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r
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.
N
o
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p
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n
. IEEE 1394 Fire Wire High-Performance Serial Interface (contd.)
Its isochronous transfer method (sending data at a constant
rate) makes it a natural for video products.
Supports data speeds as high as 1.2 Gbps
Viable option for connecting network cards, camcorders,
DVD, and other high-speed, high-volume device.
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Revision no.: PPT/2K403/02
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N
S
T
I
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U
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E
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2
0
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4
.
A
l
l
r
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g
h
t
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.
N
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p
r
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r
m
i
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s
i
o
n
.
Fire Wire Connector
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Revision no.: PPT/2K403/02
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S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
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.
N
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p
r
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m
i
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s
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n
.
Fire Wire Connector (contd.)
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Revision no.: PPT/2K403/02
C
M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
s
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r
v
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d
.
N
o
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t
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f
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m
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p
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r
m
i
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n
.
Universal Serial Bus
The USB port is a thin slot,located near the keyboard.
USB supports isochronous (time-dependent) and
asynchronous (intermittent) data transfers.
Isochronous connections transfer data at a guaranteed
fixed rate of delivery.
Asynchronous data can be transferred whenever there is no
isochronous traffic on the bus.
-
Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
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.
N
o
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p
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m
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s
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n
.
Universal Serial Bus (contd.)
Easy to use for end user
Single model for cabling and connectors
Electrical details isolated from end user e.g bus terminations.
Self identifying peripherals,automatic mapping of function to driver,and configuration
Dynamically attachable and reconfigure.
Support for upto 127 physical devices.
Allows compound devices.
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Revision no.: PPT/2K403/02
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S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
s
r
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d
.
N
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m
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n
.
Universal Serial Bus (contd.)
It provides 1.5 megabits per second (Mbps) asynchronous
transfer rate for devices, such as a mouse or keyboard,
that do not require a large amount of bandwidth.
It provides 12 Mbps isochronous transfer rate for high-
bandwidth devices such as modems, speakers, scanners,
and monitors.
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Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
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s
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r
v
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d
.
N
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a
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p
r
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r
m
i
s
s
i
o
n
.
Universal Serial Bus (contd.)
The guaranteed data-delivery rate provided by isochronous
data transfer is required to support the demand of
multimedia applications and devices.
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Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
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g
h
t
s
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.
N
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p
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m
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s
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n
.
Picture of Universal Serial Bus Cable
-
Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
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s
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r
v
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d
.
N
o
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e
p
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r
m
i
s
s
i
o
n
.
Configuring Expansion Cards
I/O Addresses
The bus system establishes a connection between the CPU and
expansion devices and provides a path for the flow of data.
In order to communicate each device is to be assigned a
unique I/O address.
CPU must identify the device before any data is placed on the
bus.
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0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
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p
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d
,
s
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d
o
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m
a
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l
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Configuring Expansion Cards (contd.)
Each device responds to unique, built-in patterns or code which allows the direct communication between the CPU and
device.
All devices must have an I/O address, and no two devices can have overlapping ranges.
Basic devices on the address list have preset I/O addresses that cannot be changed.
Other devices must be assigned to the open addresses, and they must be configured at installation.
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
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r
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p
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u
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d
,
s
t
o
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d
o
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e
m
a
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l
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Configuring Expansion Cards (contd.)
The following table lists standard PC I/O port address assignments.
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Revision no.: PPT/2K403/02
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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p
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d
,
s
t
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d
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m
a
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Configuring Expansion Cards (contd.)
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Revision no.: PPT/2K403/02
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S
T
I
T
U
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E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
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r
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p
r
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u
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d
,
s
t
o
r
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d
o
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m
a
i
l
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Configuring Expansion Cards (contd.)
I/O addresses have 16 bits; they are displayed with a hexadecimal number.
By convention, the lead 0 is dropped (because all I/O addresses have it).
Hexadecimal I/O addresses must use capital letters; they are case-sensitive.
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0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
e
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p
r
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u
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d
,
s
t
o
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d
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m
a
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Managing I/O Addresses
Devices assigned overlapping I/O addresses usually do not respond to commands and stop functioning.
A modem will dial but not connect; a sound card will start to play but will stop; a mouse pointer will appear but the
mouse will not move.
They usually appear immediately after a new device is installed.
The best way to prevent I/O address overlaps is to document all I/O addresses.
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
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r
i
a
l
m
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,
s
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d
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m
a
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d
w
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h
o
u
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t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request
Controlling the communication flow is interruption.
Every CPU has a wire called the interrupt (INT) wire.
On applying the voltage, the CPU interrupts what it is doing and attends to the device.
The CPU has only one INT wire and must handle many peripheral devices.
A chip called the 8259 chip, is present on the system to help the CPU detect which device is asking for attention.
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Revision no.: PPT/2K403/02
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
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e
r
i
a
l
m
a
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,
s
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d
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m
a
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d
w
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
Every device that needs to interrupt the CPU is provided
with a wire called an IRQ
If a device needs to interrupt the CPU, it goes through the
following steps:
The device applies voltage to the 8259 chip through its IRQ
wire.
The 8259 chip informs the CPU, by means of the INT wire, that
an interrupt is pending.
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
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t
o
f
t
h
i
s
m
a
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r
i
a
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m
a
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,
s
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d
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m
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w
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h
o
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t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
The CPU uses a wire called an INTA (interrupt acknowledge) to
signal the 8259 chip to send a pattern of 1s and 0s on the
external data bus. This information conveys to the CPU which
device is interrupting.
The CPU knows which BIOS to run.
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Revision no.: PPT/2K403/02
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I
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
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t
o
f
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h
i
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m
a
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m
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,
s
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d
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m
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w
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h
o
u
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t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
8088 computers used only one 8259 chip which limited
these computers to using only eight available IRQs.
Two IRQ were fixed for keyboard and system timer.
The remaining six wires were available for use by other
devices.
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Revision no.: PPT/2K403/02
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2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
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f
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h
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m
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,
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m
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e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
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Revision no.: PPT/2K403/02
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S
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I
T
U
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E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
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f
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h
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m
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m
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h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
Two 8259 chips were used to add 8 more available IRQs.
Since the CPU has only one IRQ wire, one of the IRQs is
used to cascade the two 8259 chips together which gives a
total of 15 available IRQs.
When a device is cascaded, this means that data is passed
through a common path between two devices, usually on to
another destination.
-
Revision no.: PPT/2K403/02
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S
T
I
T
U
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E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
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m
a
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a
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m
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d
,
s
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d
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m
a
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t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
-
Revision no.: PPT/2K403/02
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I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
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r
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a
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m
a
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d
,
s
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d
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m
a
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w
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h
o
u
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t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
IRQ 9 is directed to the old IRQ 2 wire. Any older device
designed to run on IRQ 2 will now run on IRQ 9.
Three IRQs are hardwired (0system timer, 1keyboard
controller, and 8real-time clock).
-
Revision no.: PPT/2K403/02
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I
N
S
T
I
T
U
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E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
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p
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d
,
s
t
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d
o
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m
a
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d
w
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h
o
u
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t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
Four IRQ assignments which are not usually used by any
other device except these devices such as (6floppy disk
controller, 13math coprocessor, 14primary IDE
[Integrated Device Electronics] controller, and 15
secondary IDE controller).
-
Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
e
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p
r
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d
u
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d
,
s
t
o
r
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d
o
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e
m
a
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l
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
Four IRQs default to specific types of devices such as IRQ
3COM2 and COM4, 4COM1 and COM3, 5LPT2, and 7
LPT1.
The rest (IRQs 2/9, 10, 11, and 12) are not specific and are
available for use.
The following table provides typical IRQ assignments.
-
Revision no.: PPT/2K403/02
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S
T
I
T
U
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E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
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p
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d
,
s
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d
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m
a
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d
w
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Interrupt Request (contd.)
-
Revision no.: PPT/2K403/02
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M
S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
e
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p
r
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d
u
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d
,
s
t
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e
d
o
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m
a
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l
e
d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Setting IRQs
IRQs can be set using hardware, software, or a combination
of both.
To ensure that no two devices share the same IRQ is to
document the IRQs for each device you install in a
computer and file that documentation.
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Revision no.: PPT/2K403/02
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S
I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
e
r
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p
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d
u
c
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d
,
s
t
o
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d
o
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e
m
a
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Setting IRQs (contd.)
Direct Memory Access
The CPU moves a lot of data, using considerable CPU power
and time which is a waste of the CPU's resources and time.
A DMA chip move all the data passing from peripherals to RAM
and vice versa.
-
Revision no.: PPT/2K403/02
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I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
r
t
o
f
t
h
i
s
m
a
t
e
r
i
a
l
m
a
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b
e
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p
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u
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d
,
s
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d
o
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m
a
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d
w
i
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h
o
u
t
t
h
e
p
r
i
o
r
p
e
r
m
i
s
s
i
o
n
.
Setting IRQs (contd.)
Devices must be designed to take advantage of this chip.
Initially the DMA had four channels only because DMA was
used to transfer data between floppy disk drives and RAM.
Two DMA are cascaded, allowing a total of eight DMA
channel assignments.
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Revision no.: PPT/2K403/02
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I
N
S
T
I
T
U
T
E
,
2
0
0
4
.
A
l
l
r
i
g
h
t
s
r
e
s
e
r
v
e
d
.
N
o
p
a
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t
o
f
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i
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m
a
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m
a
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p
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p
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r
m
i
s
s
i
o
n
.
Setting DMA Channels
DMA can be set by means of either hardware or software.
If two devices share the same DMA channel and "talk" at
the same time, the computer will lock up.
The following table provides DMA channel assignments.
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.
N
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p
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r
m
i
s
s
i
o
n
.
Setting DMA Channels (contd.)
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N
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p
r
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r
m
i
s
s
i
o
n
.
Setting DMA Channels (contd.)
To ensure that no two devices share the same DMA is to document the DMA for each device you install in a
computer and file that documentation.
COM and Ports Port simply means a portal or two-way access.
COM ports for serial devices and LPT (line printer) ports for parallel devices.
The following table lists standard ports the I/O addresses and IRQ
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A
l
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r
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h
t
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.
N
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p
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r
m
i
s
s
i
o
n
.
Setting DMA Channels (contd.)
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N
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p
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r
m
i
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i
o
n
.
Installation Problems with COM Ports
A modem set to COMl has a IRQ 4.
A network card is installed in the same computer which has a default setting of IRQ4
Since the IRQ of the network card and the modem will conflict, the two devices would not work.
Change the IRQ on one of the devices and both the devices will start working.
The IRQ of the network card is changed since the modem is already installed and working.
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N
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p
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r
p
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r
m
i
s
s
i
o
n
.
COM Ports
IBM PCs were equipped with two serial ports: COMl, set to
IRQ4, and COM2, set to IRQ3.
Since limited number of IRQ addresses available,
additional COM ports would have to share IRQs with
existing ports.
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N
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r
m
i
s
s
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n
.
COM Ports (contd.)
COM3 shared the interrupt of COM1 (IRQ4), and COM4
shared the interrupt of COM2 (IRQ3).
COM3 was assigned I/O address 3E8-3EF, and COM4 was
assigned I/O address 2E8-2EF.
The IRQ could be shared since the two devices would not
communicates at the same time.
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m
i
s
s
i
o
n
.
LPT Ports
They allow parallel data connections.
The standard addresses are IRQ7 for LPT1 and IRQ5 for
LPT2.
Installing Expansion Cards
Insert a Plug and Play card into the proper type of expansion
slot and turn on the computer. Windows will find the card and
guide you through the setup.
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N
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p
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r
m
i
s
s
i
o
n
.
Cables and Connectors
Cables and connectors are important part of a computer.
Parallel Printer Cables
Parallel printer ports and cables are used to connect printers.
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p
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r
p
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r
m
i
s
s
i
o
n
.
Cables and Connectors (contd.)
A standard printer cable consists of a 36-pin Centronics
connector on the printer end and a standard 25-pin "D"
(male) on the computer end was invented by the centronics
corporation
A standard 25-pin "D" (female) connector found on the back
of the computer known as parallel port.
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.
Cables and Connectors (contd.)
Standard 25-pin D connector
Printers send information in one and both direction.
There are three bi directional standards used. They are:
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p
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r
m
i
s
s
i
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n
.
Cables and Connectors (contd.)
Bi-Tronics.
It was created by Hewlett-Packard.
It allows bi directional communication, allowing the printer to
send messages to the computer (out of paper, paper jam, and
so forth).
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N
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p
r
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r
p
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r
m
i
s
s
i
o
n
.
Cables and Connectors (contd.)
EPP (Enhanced Parallel Port).
It allows 2-MB-per-second data-transfer rates.
Bi directional 8-bit operation and addressing to support
multiple (daisy-chained) peripherals on a single computer.
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N
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p
r
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p
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r
m
i
s
s
i
o
n
.
Cables and Connectors (contd.)
ECP (Extended Capabilities Port).
It was developed by Hewlett-Packard and Microsoft.
It allows 2-MB-per-second data transfer and bi directional 8-
bit operation.
ECP supports CD-ROM drive and scanner connections, run
length encoded (RLE) data compression.
DMA support to increase transfer speed and reduce processor
overhead.
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N
o
p
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p
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r
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r
m
i
s
s
i
o
n
.
Cables and Connectors (contd.)
The Institute of Electrical and Electronic Engineers (IEEE)
developed a standardIEEE 1284for the standardization
of these ports.
IEEE 1284 Printer Modes
The following table describes various printing modes and their
capabilities.
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N
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p
r
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r
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e
r
m
i
s
s
i
o
n
.
Cables and Connectors (contd.)
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