06esl48 hdl lab2

CMR INSTITUTE FOF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

HDL LABORATORY REPORT

Name :

USN :

Sem/Sec :

http://results.vtu.ac.in/../vitavi.php

CMR INSTITUTE OF TECHNOLOGY

Department of Electronics & Communication

2010-11

LABORATORY CERTIFICATE

This is to certify that Mr. /Ms.

Bearing USN 1CR09EC has satisfactorily

completed the course of experiments in HDL

Laboratory (06ESL48) prescribed by VTU for 4th

semester BE Electronics & Communication course

in the laboratory of this college in the year

2010-2011.

DATE:

Signature of teachers in charge

Signature of HOD

ii

Contents

EXPT. NO.

NAME OF THE EXPERIMENTPAGE NO.

01

a) VHDL PROGRAM FOR AND GATE 01

b) VHDL PROGRAM FOR OR GATE 02

C) VHDL PROGRAM FOR NOT GATE 03

d) VHDL PROGRAM FOR XOR GATE 04

e) VHDL CODE FOR A NAND GATE 05

VERILOG CODE FOR ALL GATES 06

02 DECODER 2 – 4 08

03 ENCODER 8-3 09

04 PRIORITY ENCODER 11

05 a) 4:1 MULTIPLEXER 13

05 b) 8:1 MULTIPLEXER 15

06 a) 1:4 DEMULTIPLEXER 17

06 B) 1:8 DEMULTIPLEXER 19

07 BINARY TO GRAY CODE CONVERTER 22

08 ‘N’ BIT COMPARATOR. 24

09 a) FULLADDER 26

09 b) FULLADDER USING STRUCTURAL PROGRAMMING 28

10 32 BIT ALU 31

11 a) SR FLIP-FLOP 33

11 b) JK FLIP-FLOP 35

11 c) D FLIP-FLOP 37

11 d) T FLIP-FLOP 39

12 a) BINARY COUNTER WITH ASYNCHRONOUS RESET 41

12 b) BINARY COUNTER WITH SYNCHRONOUS RESET 43

12 c) BCD COUNTER WITH SYNCHRONOUS RESET 45

12 d) BCD COUNTER WITH ASYNCHRONOUS RESET 47

12 e) RANDOM SEQUENCE GENERATOR 49

INTERFACING PROGRAMMES13 KEY SCAN AND DISPLAY UNIT 52

14 ELEVATOR CONTROLLER 55

15 MESSAGE DISPLAY UNIT 58

16

a) DAC TO GENERATE A SQUARE WAVE4 60

b) DAC TO GENERATE AN UP GOING RAMP 62

c) DAC TO GENERATE A DOWNWARD RAMP 63

DELAY PROGRAM 65

iii

01 (A): VHDL PROGRAM FOR AND GATE:

Aim: To write a VHDL code to implement an AND gate.

Summary: The O/P of a 2 I/P AND gate is high iff both the inputs are high, else the O/P is low.

Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity andgate is Port ( a : in std_logic; b : in std_logic; c : out std_logic);end andgate;architecture Behavioral of andgate isbeginprocess(a,b)begin

c<= a and b;end process;end Behavioral;

RTL Schematic:

Truth Table:

a b c0 0 00 1 01 0 01 1 1

Wave form:

Result :- The truth table for AND gate is verified

1

01(b): VHDL PROGRAM FOR OR GATE:

Aim: To write a VHDL code to implement an OR gate.

Summary: The O/P of a 2 I/P OR gate is high if at least any one of the 2 inputs is high, else the O/P is zero.

Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity orgate is Port ( a : in std_logic; b: in std_logic; c : out std_logic);end orgate;architecture Behavioral of orgate isbegin c<=a or b;end Behavioral;RTL Schematic:

Truth Table:

A b c0 0 00 1 11 0 11 1 1

Wave form:

Result:- The truth table for OR gate is verified

2

1(c): VHDL PROGRAM FOR NOT GATE:

Aim: To write a VHDL code to implement an NOT gate.

Summary: The O/P of an inverter or NOT gate is the inverted version of the I/P .A logic 1 appears as logic 0 at the O/P and vice-versa.

Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity notgate isport ( a : in std_logic; b : out std_logic);end notgate;architecture Behavioral of notgate isbeginprocess(a)begin b<=not a;end process;end Behavioral;

RTL Schematic:

Truth Table:

a b0 11 0

Wave form:

Result:- The truth table for NOT gate is verified

3

1(d): VHDL PROGRAM FOR XOR GATE

Aim: To write a VHDL code to implement an XOR gate.

Summary: The O/P of XOR gate is high only if both the I/P values are different, else the O/P is low.

Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xor1 is Port ( a : in std_logic; b : in std_logic; c : out std_logic);end xor1;architecture Behavioral of xor1 isbegin

c <= a xor b;end Behavioral;RTL Schematic:

Truth Table:a b c0 0 00 1 11 0 11 1 0

Wave form:

Result:The truth table for XOR gate is verified

4

1(e): VHDL CODE FOR A NAND GATE:

Aim: To write a VHDL code to implement an NAND gate.

Summary: The O/P of a 2 I/P NAND gate is high if both the inputs are low, else the O/P is low.

Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity nandgate is Port ( a : in std_logic; b : in std_logic; c : out std_logic);end nandgate;architecture Behavioral of nandgate isbeginprocess(a,b)begin c<=not(a and b);end process;end Behavioral;

Truth Table:

a b C0 0 10 1 01 0 01 1 0

Wave form:

Result: The truth table for NAND gate is verified

5

VERILOG CODE FOR GATES

Aim: To write a VERILOG code to implement all GATES.

Program:module allgates(a, b, not1, or2, and3, nor4, nand5, xor6, xnor7); input a; input b; output not1; output or2; output and3; output nor4; output nand5; output xor6; output xnor7;

reg not1,or2,and3,nor4,nand5,xor6,xnor7; always @(a or b) begin not1=~(a); and3=a&b; or2=a|b; nand5=~((a)&(b)); nor4=~((a)|(b)); xor6=(a)^(b); xnor7=((a)^(b)); end

endmodule

Result: All gates is been verified by VHDL and Verilog code

6

02: DECODER 2 - 4

AIM: To design and implement 2:4 decoder.

VHDL PROGRAM:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODER2X4 is Port ( en : in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic_vector(3 downto 0));end DECODER2X4;

architecture Behavioral of DECODER2X4 is

beginprocess(s,en) begin

if(en='1')then case s is when "00" => y <= “0001” ; when "01" => y <= “0010” ; when "10" => y <= “0100” ;

when "11" => y <= “1000” ; when others=> null; end case; end if;

end process;end Behavioral;

VERILOG PROGRAM:-module decoder(a, en, y); input [1:0] a; input en; output [3:0]y;

reg[3:0]y; always @(en or a) begin if(!en) y=4'b0000; else case(a) 2'b00:y=4'b0001; 2'b01:y=4'b0010; 2'b10:y=4'b0100; 2'b11:y=4'b1000; default:y=4'b0000; endcase end

endmodule

7

IC DIAGRAM:

INETRNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSEN S(1) S(0) Y(3) Y(2) Y(1) Y(0)0 X X X X X X1 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0

WAVEFORMS:

RESULT: The 2:4 decoder has been successfully designed and implemented.

8

03 ENCODER 8-3AIM:

To design and implement a 8:3 encoder.

VHDL PROGRAM:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encoder8_3 is Port ( en : in std_logic; a : in std_logic_vector(7 downto 0); y : out std_logic_vector(2 downto 0));end encoder8_3;architecture Behavioral of encoder8_3 isbegin

process(a,en) begin

if(en='1')then case a is when"10000000" => y <="111”;

when"01000000"=> y <="110" ; when"00100000"=>y<=”101”; when”00010000”=>y<=”100”;

when"00001000"=>Y<=”011”; when"00000100"=>y<=”010”;

when"00000010"=>y<=”001”; when"00000001"=>y<=”000”; when others=>null;

end case; end if;end process;

end Behavioral;

VERILOG PROGRAM:-module encoder(en, ain, yout); input en; input [7:0] ain; output [2:0] yout;

reg[2:0]yout; always @(en or ain) begin if(!en) yout=3'b0; else case (ain) 8'b00000001:yout=3'b000; 8'b00000010:yout=3'b001; 8'b00000100:yout=3'b010; 8'b00001000:yout=3'b011; 8'b00010000:yout=3'b100; 8'b00100000:yout=3'b101; 8'b01000000:yout=3'b110; 8'b10000000:yout=3'b111; default:yout=3'b000; endcase end endmodule

9

IC DIAGRAM:

WAVEFORMS:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSEN A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0) Y(2) Y(1) Y(0)0 X X X X X X X X X X X1 0 0 0 0 0 0 0 1 0 0 01 0 0 0 0 0 0 1 0 0 0 11 0 0 0 0 0 1 0 0 0 1 01 0 0 0 0 1 0 0 0 0 1 11 0 0 0 1 0 0 0 0 1 0 01 0 0 1 0 0 0 0 0 1 0 11 0 1 0 0 0 0 0 0 1 1 01 1 0 0 0 0 0 0 0 1 1 1

RESULT:- The 8:3 encoder has been successfully designed and implemented.

10

04 - PRIORITY ENCODERAIM: To design and implement the priority encoder


entity priorencoder is Port ( en : in std_logic; a : in std_logic_vector(7 downto 0); y : out std_logic_vector(2 downto 0));end priorencoder;

architecture Behavioral of priorencoder is

beginprocess(a,en) begin

if(en='1')then case a is when"1-------" =>y<="111"; when"01------" =>y<="110"; when"001-----" =>y<="101"; when"0001----" =>y<="100"; when"00001---" =>y<="011"; when"000001--" =>y<="010"; when"0000001-" =>y<="001"; when"00000001" =>y<="000"; when others=>null; end case; end if;


VERILOG PROGRAM:-module priorityencoder(en, a, y); input en; input [7:0] a; output [2:0] y;

reg[2:0]y; always@(a,en) begin if(!en) y=3'b0; else case(a) 8'b00000001:y=3'b000; 8'b0000001x:y=3'b001; 8'b000001xx:y=3'b010; 8'b00001xxx:y=3'b011; 8'b0001xxxx:y=3'b100; 8'b001xxxxx:y=3'b101; 8'b01xxxxxx:y=3'b110; 8'b1xxxxxxx:y=3'b111; default y=3'b0; endcase end

endmodule

11

IC DIAGRAM

WAVEFORMS: -

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUT OUTPUTA(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0) B(2) B(1) B(0)

0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 - 0 0 10 0 0 0 0 1 - - 0 1 00 0 0 0 1 - - - 0 1 10 0 0 1 - - - - 1 0 00 0 1 - - - - - 1 0 10 1 - - - - - - 1 1 01 - - - - - - - 1 1 1

RESULT: The priority encoder has been designed successfully and implemented

12

05 (a) - 4:1 MULTIPLEXER AIM:

To design and implement a 4:1 multiplexer.

VHDL PROGRAM:


entity mux4_1 is Port ( en : in std_logic; y : out std_logic; a : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0));end mux4_1;

architecture Behavioral of mux4_1 isbegin

process (a,s,en) begin

if(en='1') then case s is when"00"=>y<=a(0); when"01"=>y<=a(1); when"10"=>y<=a(2); when"11"=>y<=a(3); when others => null; end case;end if;


VERILOG PROGRAM :-

module mux(y,s,a,en);output y;input[3:0]a;input[1:0]s;reg y;input en;always@(s,en) beginy=1’b0;if(en==1) begincase (s)2’b00:y=a[0];2’b01:y=a[1];2’b10:y=a[2];2’b11:y=a[3];default:y= 1'b0;endcaseendendendmodule

13

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSEn s(1) s(0) y0 X X X1 0 0 a(0)1 0 1 a(1)1 1 0 a(2)1 1 1 a(3)

WAVEFORMS:

RESULT: The 4:1 multiplexer has been successfully designed and implemented.

14

05(b):- 8:1 MULTIPLEXER

AIM:- To design and implement the 8:1 multiplexer.

VHDL PROGRAM:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux8_1 is Port ( a : in std_logic_vector(7 downto 0); s : in std_logic_vector(2 downto 0); y : out std_logic; en : in std_logic);end mux8_1;architecture Behavioral of mux8_1 isbegin

process(a,s,en) begin

if(en='1')then case s is when"000"=>y<=a(0); when"001"=>y<=a(1); when"010"=>y<=a(2);

when"011"=>y<=a(3); when"100"=>y<=a(4); when"101"=>y<=a(5); when"110"=>y<=a(6); when"111"=>y<=a(7); when others => null; end case; else null; end if;


VERILOG PROGRAM:-module mux(en, a, sel, y); input en; input [7:0] a; input [2:0] sel; output y;

reg y; always @(en or a) begin if(!en) y=1'b0; else case(sel) 3'b000:y=a[7]; 3'b001:y=a[6]; 3'b010:y=a[5]; 3'b011:y=a[4]; 3'b100:y=a[3]; 3'b101:y=a[2]; 3'b110:y=a[1]; 3'b111:y=a[0]; endcase end endmodule

16

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

E S2 S1 S0 y 1 0 0 0 i (0) 1 0 0 1 i (1) 1 0 1 0 i (2) 1 0 1 1 i (3) 1 1 0 0 i (4) 1 1 0 1 i (5) 1 1 1 0 i (6) 1 1 1 1 i (7) 0 x x x 0

WAVEFORMS:

RESULT:

The 8:1 multiplexer was successfully designed and implemented.

17

6(a): 1:4 DEMULTIPLEXER

AIM:To design and implement a 1:4 demultiplexer

VHDL PROGRAM:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux 1_4 is Port ( a : in std_logic; en : in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic_vector(3 downto 0));end demux 1_4;

architecture Behavioral of demux 1_4 is

beginprocess(a,s,en) begin

if(en='1')then case s is when "00"=>y(0)<=a;y(1)<='0';y(2)<='0';y(3)<='0'; when "01"=>y(0)<='0';y(1)<=a;y(2)<='0';y(3)<='0'; when "10"=>y(0)<='0';y(1)<='0';y(2)<=a;y(3)<='0'; when "11"=>y(0)<='0';y(1)<='0';y(2)<='0';y(3)<=a; when others=> null; end case; end if;


VERILOG PROGRAM:-module dmux(a,en,y,s);input a,en;input[1:0] s;output[3:0] y;reg[3:0 ]y;always@(a,s,en)beginif(!en)y=4’b0000;elsecase (s)2’b00:beginy[3]=a;y[2:0]=3’b000;end2’b01:beginy[2]=a;y[3]=1’b0;y[1:0]=2’b00;end2’b10:beginy[1]=a;y[3:2]=2’b00;y[0]=1’b0;end2’b11:begin

18

y[0]=a;y[3:1]=3’b000;endendcaseendendmodule

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:-

EN A S(1) S(0) Y(3) Y(2) Y(1) Y(0)0 X X X X X X X1 1 0 0 0 0 0 11 1 0 1 0 0 1 01 1 1 0 0 1 0 01 1 1 1 1 0 0 0

WAVEFORMS:

RESULT: The 1:4 demultiplexer has been successfully designed and implemented

19

6(b): 1:8 DEMULTIPLEXER

AIM:To design and implement a 1:8 demuliplexer.

VHDL PROGRAM:


entity demux 1_8 is Port ( a : in std_logic; en : in std_logic; s : in std_logic_vector(2 downto 0); y : out std_logic_vector(7 downto 0));end demux 1_8;

architecture Behavioral of demux 1_8 is

beginprocess(a,s,en) begin

if(en='1')then case s is when"000"=>y(0)<=a;y(1)<='0';y(2)<='0';y(3)<='0';

y(4)<='0';y(5)<='0';y(6)<='0';y(7)<='0';

when"001"=>y(0)<='0';y(1)<=a;y(2)<='0';y(3)<='0'; y(4)<='0';y(5)<='0';y(6)<='0';y(7)<='0';

when "010"=>y(0)<='0';y(1)<='0';y(2)<=a;y(3)<='0'; y(4)<='0';y(5)<='0';y(6)<='0';y(7)<='0';

when "011"=>y(0)<='0';y(1)<='0';y(2)<='0';y(3)<=a; y(4)<='0';y(5)<='0';y(6)<='0';y(7)<='0';

when "100"=>y(0)<='0';y(1)<='0';y(2)<='0';y(3)<='0'; y(4)<=a;y(5)<='0';y(6)<='0';y(7)<='0';

when "101"=>y(0)<='0';y(1)<='0';y(2)<='0';y(3)<='0'; y(4)<='0';y(5)<=a;y(6)<='0';y(7)<='0';

when "110"=>y(0)<='0';y(1)<='0';y(2)<='0';y(3)<='0'; y(4)<='0';y(5)<='0';y(6)<=a;y(7)<='0';

when "111"=>y(0)<='0';y(1)<='0';y(2)<='0';y(3)<='0'; y(4)<='0';y(5)<='0';y(6)<='0';y(7)<=a;

when others=> null; end case; end if;


20

VERILOG PROGRAM:- module demux(a, en, sel, y); input a; input en; input [2:0] sel; output [7:0] y;

reg[7:0]y; always@(a,en,sel) begin if(!en) y=8'b00000000; else case(sel) 3'b000:begin y[0]=a; y[7:1]=7'b0000000; end 3'b001:begin y[0]=0; y[1]=a; y[7:2]=6'b0000000; end 3'b010:begin y[1:0]=2'b00; y[2]=a; y[7:3]=5'b00000; end 3'b011:begin y[2:0]=3'b000; y[3]=a; y[7:4]=4'b0000; end 3'b100:begin y[3:0]=4'b0000; y[4]=a; y[7:5]=3'b000; end 3'b101:begin y[4:0]=5'b00000; y[5]=a; y[7:6]=2'b00; end 3'b110:begin y[5:0]=6'b000000; y[6]=a; y[7]=0; end 3'b111:begin y[6:0]=7'b0000000; y[7]=a; end endcase

end endmodule

21

INTERNAL DIAGRAM:

IC DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSEN A S(2) S(1) S(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)0 X X X X X X X X X X X X1 1 0 0 0 0 0 0 0 0 0 0 11 1 0 0 1 0 0 0 0 0 0 1 01 1 0 1 0 0 0 0 0 0 1 0 01 1 0 1 1 0 0 0 0 1 0 0 01 1 1 0 0 0 0 0 1 0 0 0 01 1 1 0 1 0 0 1 0 0 0 0 01 1 1 1 0 0 1 0 0 0 0 0 01 1 1 1 1 1 0 0 0 0 0 0 0

WAVEFORMS:

RESULT: The 1:8 demultiplexer has been successfully designed and implemented.

22

(07):- BINARY TO GRAY CODE CONVERTER.

AIM: To design a binary to gray code converter.

VHDL PROGRAM:


entity bin2gray is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0));end bin2gray;

architecture Behavioral of bin2gray is

beginprocess(b) begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end process;

end Behavioral;

VERILOG PROGRAM :-

module bintogray(a, b); input [3:0] a; output [3:0] b;

reg[3:0]b; always @(a,b) begin b[3]=a[3]; b[2]=a[3]â[2]; b[1]=a[2]â[1]; b[0]=a[1]â[0]; end endmodule

IC DIAGRAM:

23

INTERNAL DIAGRAM:

TRUTH TABLE:

B(3) B(2) B(1) B(0) G(3) G(2) G(1) G(0)0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 0 1 1 1 11 0 1 1 1 1 1 01 1 0 0 1 0 1 01 1 0 1 1 0 1 11 1 1 0 1 0 0 11 1 1 1 1 0 0 0

WAVEFORMS:

RESULT:

Binary to Gray code conversion has been successfully designed and implemented

24

08 – ‘N’ BIT COMPARATOR.

AIM:To design and implement an N bit comparator.

VHDL PROGRAM:


entity comp_N isgeneric (N : integer :=7); Port (a,b : in std_logic_vector(7 downto 0); Alb,Agb,Aeb : out std_logic);end comp_N;

architecture Behavioral of comp_N is

beginprocess(a,b)beginif (a<b) then Alb <=’1’ ;else Alb <=’0’;end if;if (a>b) then Agb <=’1’ ;else Agb <=’0’;end if;if (a=b) then Aeb <=’1’ ;else Aeb <=’0’;end if;end process;end Behavioral;

VERILOG PROGRAM:-

module comparator(a, b, q1, q2, q3); input [7:0] a; input [7:0] b; output q1; output q2; output q3;

reg q1,q2,q3; always@(a,b) begin if(a>b) q1=1; else q1=0; if(a<b) q2=1; else q2=0; if(a==b) q3=1; else q3=0; end

endmodule

25

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTNUMBER A NUMBER B R

1000 0000 0000 0000 1001000 0000 1000 0000 0100000 0000 1000 0000 001

WAVEFORMS:

RESULT:The 8 bit comparator has been successfully designed and implemented.

26

09(A): FULLADDERAIM:

To design and implement a fulladder.

VHDL PROGRAM:


entity fulladder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; so : out std_logic; co : out std_logic);end fulladder;

architecture Behavioral of fulladder is

beginso<=a xor b xor c;co<=(a and b) or (b and c) or (c and a);

end Behavioral; architecture dataflow of fulladder isbegin so<=a xor b xor c; co<=(a and b) or (b and c) or (c and a);end dataflow;

VERILOG PROGRAM:-

module fulladder(a, b, c, s, ca); input a; input b; input c; output s; output ca;

reg s; reg ca; always@(a,b,c) begin s=a^(b^c); ca=((a^b)&c)|(a&b); end

endmodule

27

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSA b C C(0) S(0)0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

WAVFORMS:

RESULT: The full adder has been successfully designed and implemented.

28

09(b): FULLADDER using STRUCTURAL PROGRAMMING

AIM: To design and implement a full-adder using structural programming.

VHDL PROGRAM:


entity fullstru isPort ( a,b : in std_logic;c : in std_logic;s : out std_logic;ca : out std_logic);end fullstru;

architecture structural of fullstru iscomponent xor2 isport (p,q:in std_logic;r: out std_logic);end component;component and2 isport(m,n:in std_logic;o: out std_logic);end component;component or2 isport(h,i:in std_logic;j:out std_logic);end component;signal x,y,z:std_logic;beginu1:xor2 port map(a,b,x);u2:and2 port map(a,b,y);u3:xor2 port map(x,c,s);u4:and2 port map(x,c,z);u5:or2 port map(z,y,ca);

end structural;

AND2 is:entity and2 is Port ( m : in std_logic; n : in std_logic; o : out std_logic);end and2;

architecture Behavioral of and2 isbegin

o<=m and n;end Behavioral;

29

OR2 is:entity or2 is Port ( h : in std_logic; i : in std_logic; j : out std_logic);end or2;

architecture Behavioral of or2 isbegin

j<=h or i;end Behavioral;

XOR2 is:entity xor2 is Port ( p : in std_logic; q : in std_logic; r : out std_logic);end xor2;architecture Behavioral of xor2 isbegin

r<= p xor q;end Behavioral;

Structural (verilog)

module fa(a,b,c,s,ca); input a; input b; input c; output s; output ca; wire s1,c1,c2; xor#s(s1,a,b); xor#s(s,s1,c); and#s(s1,c2,c); and#s(c1,a,b); or#s(ca,c1,c2); endmodule

IC DIAGRAM:

30

INTERNAL DIAGRAM:

TRUTH TABLE:

A B CIN SOUT COUT0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

WAVEFORMS:

RESULT: The full-adder is successfully designed and implemented.

31

(10) – 32 BIT ALU

AIM: To design and implement an 32 bit ALU

VHDL PROGRAM:


entity alu is Port ( opc : in std_logic_vector(2 downto 0); a : in std_logic_vector(2 downto 0); b : in std_logic_vector(2 downto 0); q : out std_logic_vector(2 downto 0));end alu;

architecture Behavioral of alu is

begin process(a,b,opc)

begin case opc is

when"000"=>q<="000";when"001"=>q<=a-b;when"010"=>q<=a+b;when"011"=>q<=a xor b;when"100"=>q<=a and b;when"101"=>q<=a or b;when"110"=>q<= not a;when"111"=>q<="111";when others=>null;

end case;end process;

end Behavioral;

VERILOG:-module alu(opc, a, b, q); input [2:0] opc; input [5:0] a; input [5:0] b; output [5:0] q;

reg[5:0]q; always@(a,b,opc) begin case(opc[2:0]) 3'b000:q=000; 3'b001:q=a+b; 3'b010:q=a-b; 3'b011:q=a&b; 3'b100:q=a|b; 3'b101:q=a^b; 3'b110:q=~a; 3'b111:q=~(a&b); endcase end

endmodule

32

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

OPCODE OPERATION INPUTS OUTPUTA B

000 Reset 101 001 000001 Sub 101 001 100010 Add 101 001 110011 Xor 101 001 100100 And 101 001 001101 Or 101 001 101110 Comp 101 001 100111 set 101 001 111

WAVEFORMS:

RESULT: The ALU has been successfully designed and implemented.

33

11 (a): SR FLIP-FLOP

AIM:To design and implement a SR flip-flop.

VHDL PROGRAM:


entity srff is Port ( s : in std_logic; r : in std_logic;

clk:in std_logic; q : inout std_logic; qn : out std_logic:='1');end srff;

architecture Behavioral of srff is

begin

process(clk) begin if(clk='1' and clk'event) then

if(s='0'and r='0') then q<=q; elsif(s='0' and r='1')then q<='0'; elsif(s='1' and r='0')then q<='1'; elsif(s='1' and r='1')then q<='Z'; end if; end if;

end process;qn <=not q;

end Behavioral;

VERILOG PROGRAM:-

module srflipflop(clk, sr, q, qn); input clk; input [1:0] sr; output q; output qn;

reg q,qn; always@(posedge clk) begin case(sr) 2'b00:q=q; 2'b01:q=0; 2'b10:q=1; 2'b11:q=~q; endcase qn=~q; end

34

endmodule

IC DIAGRAM:

INTERNAL DAIGRAM:

TURTH TABLE:

S R Q QN0 0 q qn0 1 0 11 0 1 01 1 invalid invalid

WAVEFORM:

35

RESULT: The SR flip-flop is successfully designed and implemented

36

11 (b): JK FLIP-FLOP

AIM:To design and implement a JK flip-flop.

VHDL PROGRAM:


entity jkff is Port ( j : in std_logic; k : in std_logic; sn : in std_logic; rn : in std_logic; clk : in std_logic; q : inout std_logic; qn : out std_logic);end jkff;architecture Behavioral of jkff isbegin

process(clk,rn,sn) begin

if(clk='1' and clk'event)then if(rn='0')then q<='0';

elsif(sn='0')then q<='1'; else q<=(j and (not q))or((not k)and q);

end if; end if;

end process;qn<= not q;

end Behavioral;

VERILOG PROGRAM:-module jkflipflop(clk, jk, q, qn); input clk; input [1:0]jk; output q; output qn;

reg q,qn;

always@(posedge clk) begin case(jk)

2'b00:q=q; 2'b01:q=0; 2'b10:q=1; 2'b11:q=~q ; endcase qn=~q; end

endmodule

37

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSCLK SN RN J K Q QN

1 0 1 X X 0 11 1 0 X X 1 01 1 1 0 0 Q QN1 1 1 0 1 0 11 1 1 1 0 1 01 1 1 1 1 QN Q

IC DIAGRAM:

WAVEFORMS:

RESULT:The JK flip-flop has been successfully designed and implemented.

38

11 (c): d FLIP-FLOP

AIM:To design and implement a synchronous d flip-flop.

VHDL PROGRAM:


entity dff is Port ( clk : in std_logic; reset : in std_logic; din : in std_logic;

dout :inout std_logic; ndout : out std_logic);end dff;

architecture Behavioral of dff isbegin

process(clk,reset) begin if(clk='1' and clk'event)then if(reset='1')then dout<='0'; else dout<=din; end if; end if; end process; ndout<=not dout;

end Behavioral;

VERILOG PROGRAM:-

module dflipflop(clk, d, q, qd); input clk; input d; output q; output qd;

reg q,qd; always@(clk) begin if(clk==1) begin q=d; qd=~q; end else begin q=0; qd=~q; end end

endmodule

39

TRUTH TABLE:

INPUTS OUTPUTSCLK RESET DIN DOUT NDOUT

0 X X X X1 1 X 0 11 0 1 1 01 0 0 0 1

IC DIAGRAM:

INTERNAL DIAGRAM:

WAVEFORMS:

RESULT: The synchronous d flip-flop has been successfully designed and implemented.

40

11 (d): t FLIP-FLOP

Experiment 10(d):AIM:

To design and implement a synchronous t flip-flop.

VHDL PROGRAM:


entity tff is Port ( t : in std_logic; clk : in std_logic; qn : inout std_logic; q : out std_logic:='1');end tff;

architecture Behavioral of tff is

beginprocess(clk,t) begin

if(clk='1' and clk'event)then if(t='1')then

q<= not qn; end if; end if;

end process; end Behavioral;

VERILOG PROGRAM :-

module dflipflop(clk, t, q, qt); input clk; input t; output q; output qt; reg q,qt;initial q=1’b01;begin

always@(clk,t) begin if(clk==1) begin

if(t==1) qt=~q;

q=~q end else q=qt; qt=~q; end end

endmodule

41

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSCLK T Q QN

0 X X X1 0 Q QN1 1 QN Q

WAVEFORMS:

RESULT: The synchronous t flip-flop has successfully designed and implemented.

42

12(a) - BINARY COUNTER WITH ASYNCHRONOUS RESET

AIM:To design and implement a binary counter with asynchronous reset.

VHDL PROGRAM:


entity binsync is Port ( clk : in std_logic; reset : in std_logic; q : out std_logic_vector(3 downto 0); c : out std_logic);end binsync;

architecture Behavioral of binsync issignal count:std_logic_vector(3 downto 0):="0000";begin

process(clk,reset) begin

if(reset='1')then count<="0000"; elsif(clk='1' and clk'event)then

count<=count+"0001"; end if; if(count="1111")then

c<='1'; else c<='0';

end if; end process; q<=count; end Behavioral;

VERILOG PROGRAM:module binasyncvr(clk, reset, count); input clk; input reset; output [3:0] count;

reg[3:0]count; always @(reset or clk) begin if(reset) count=4'b0000; else if(clk) if(count==4'b1111) count=4'b0000; else count=count+1; end

endmodule

43

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSCLK RESET CO COUNT(3) COUNT(2) COUNT(1) COUNT(0)

0 1 0 0 0 0 01 1 0 0 0 0 01 0 0 0 0 0 11 0 0 0 0 1 01 0 0 0 0 1 11 0 0 0 1 0 01 0 0 0 1 0 11 0 0 0 1 1 01 0 0 0 1 1 11 0 0 1 0 0 01 0 0 1 0 0 11 0 0 1 0 1 01 0 0 1 0 1 11 0 0 1 1 0 01 0 0 1 1 0 11 0 0 1 1 1 01 0 0 1 1 1 11 0 1 0 0 0 0

WAVEFORMS:

RESULTS: The binary counter with asynchronous reset has been successfully designedand implemented

44

12(b): BINARY COUNTER WITH SYNCHRONOUS RESETAIM:

To design and implement a binary counter with synchronous reset.

VHDL PROGRAM:


entity binasync is Port ( clk : in std_logic; reset : in std_logic; q : out std_logic_vector(3 downto 0); c : out std_logic);end binasync;

architecture Behavioral of binasync issignal count:std_logic_vector(3 downto 0):="0000";begin

process(clk,reset) begin

if(clk='1' and clk'event)then if(reset='1')then count<="0000"; else count<=count+"0001"; end if; end if;if(count="1111")then count<=”0000”;

end if; end process; q<=count; end Behavioral;

VERILOG PROGRAM:module binsyncvr(clk, reset, count); input clk; input reset; output [3:0] count;

reg[3:0] count; always @(reset or clk) begin if(reset==1) count=4'b0000; else if(clk) count=count+1; end

endmoduleIC DIAGRAM:

45

INTERNAL DIAGRAM:

TRUTH TABLE:INPUTS OUTPUTS

CLK RESET CO COUNT(3) COUNT(2) COUNT(1) COUNT(0)0 1 0 0 0 0 01 1 0 0 0 0 01 0 0 0 0 0 11 0 0 0 0 1 01 0 0 0 0 1 11 0 0 0 1 0 01 0 0 0 1 0 11 0 0 0 1 1 01 0 0 0 1 1 11 0 0 1 0 0 01 0 0 1 0 0 11 0 0 1 0 1 01 0 0 1 0 1 11 0 0 1 1 0 01 0 0 1 1 0 11 0 0 1 1 1 01 0 0 1 1 1 11 0 1 0 0 0 0

WAVEFORMS:

RESULT: The binary counter with synchronous reset has been successfully designed and implemented.

46

12(c): BCD COUNTER WITH SYNCHRONOUS RESET

AIM:To design and implement a BCD counter with synchronous reset.

VHDL PROGRAM:


entity bcdsync is Port ( clk : in std_logic; reset : in std_logic; q : out std_logic_vector(3 downto 0); c : out std_logic);end bcdsync;

architecture Behavioral of bcdsync issignal count:std_logic_vector(3 downto 0);begin

process(clk,reset)begin if(clk='1'and clk'event)then if(reset='1')then count<="0000";c<='0'; elsif(count="1001")then count<="0000";c<='1'; else count<=count+"0001";c<='0'; end if; end if;end process;q<=count;

end Behavioral;VERILOG PROGRAM:

module bcdsync_v(clk,reset,count);input clk,reset;output[3:0] count;reg[3:0] count;initial count=4’b0000;always @(posedge(clk))

beginif(clk)if(reset)count=4’b0000;else if(count==4’b1001)count=4’b0000;elsecount=count+1;end

endmodule

47

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:


0 1 0 0 0 0 01 0 0 0 0 0

1 0 0 0 0 0 11 0 0 0 0 1 01 0 0 0 0 1 11 0 0 0 1 0 01 0 0 0 1 0 11 0 0 0 1 1 01 0 0 0 1 1 11 0 0 1 0 0 01 0 0 1 0 0 11 0 1 0 0 0 0

WAVEFORMS:

RESULTS: The BCD counter with synchronous reset has been successfully designed and implemented.

48

12(d): BCD COUNTER WITH ASYNCHRONOUS RESETAIM

To design and implement a BCD counter with asynchronous reset.

VHDL PROGRAM:


entity bcdasync is Port ( clk : in std_logic; reset : in std_logic; q : out std_logic_vector(3 downto 0); c : out std_logic);end bcdasync;

architecture Behavioral of bcdasync issignal count:std_logic_vector(3 downto 0);begin

process(clk,reset)beginif(reset='1')then count<="0000";c<='0'; elsif(clk='1'and clk'event)then if(count="1001")then count<="0000";c<='1'; else count<=count+"0001";c<='0'; end if; end if;end process;q<=count;

end Behavioral;

VERILOG PROGRAM:module bcdasyncvr(clk, reset, cout); input clk; input reset; output [3:0] cout;

reg[3:0]cout; always@(reset or clk) begin if(reset==1) cout=4'b0000; else if(clk) if(cout==4'b1001) cout=4'b0000; else cout=cout+1; end

endmodule

IC DIAGRAM:

49

INTERNAL DIAGRAM:

TRUTH TABLE:


0 1 0 0 0 0 01 0 0 0 0 0

1 0 0 0 0 0 11 0 0 0 0 1 01 0 0 0 0 1 11 0 0 0 1 0 01 0 0 0 1 0 11 0 0 0 1 1 01 0 0 0 1 1 11 0 0 1 0 0 01 0 0 1 0 0 11 0 1 0 0 0 0

WAVEFORMS:

RESULTS: The BCD counter with synchronous reset has been successfully designed and implemented.

50

12(e): RANDOM SEQUENCE GENERATORAIM:

To design and implement a random sequence generator.


entity rsg is Port ( clk : in std_logic; q : out std_logic_vector(2 downto 0));end rsg;

architecture Behavioral of rsg is signal state:std_logic_vector(2 downto 0):="000";begin

process(clk) begin if(clk='1' and clk'event)then

case state is when"000"=> state<="010"; when"010"=> state<="001"; when"001"=> state<="101"; when"101"=> state<="110"; when"110"=> state<="111"; when"111"=> state<="110"; when others=>null;end case;

end if;end process;q<=state;

end Behavioral;VERILOG PROGRAM:module rsgvr(clk, clr, q); input clk; input clr; output [2:0] q;

reg[2:0]q; always @(posedge clk) begin if(clr==0) begin case(q) 3'd0:q=3'd2; 3'd2:q=3'd1; 3'd1:q=3'd5; 3'd5:q=3'd7; 3'd7:q=3'd0; endcase end else q=3'b000; end

endmodule

51

IC DIAGRAM:

INTERNAL DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTSA B C A+ B+ C+0 0 0 0 0 10 0 1 0 1 10 1 1 1 0 11 0 1 1 1 01 1 0 0 0 00 0 0 0 0 1

WAVEFORMS:

RESULT: The random sequence generator has been successfully designed and implemented.

52

INTERFACING PROGRAMMES

53

13: KEY SCAN AND DISPLAY UNITAIM:

To design and implement key scan and display unit.

VHDL PROGRAM:

entity keypress is Port ( pkeyret : in std_logic_vector(3 downto 0); pkeyscn : out std_logic_vector(3 downto 0);

pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pledind : out std_logic_vector (7 downto 0); pclk100K : in std_logic);

end keypress;

architecture behavioral of keypress is

signal skeyval : integer range 0 to 15;signal skeyhit : std_logic; signal skeyscn : std_logic_vector(3 downto 0);signal sclkdiv : std_logic_vector(7 downto 0);signal skeyclk : std_logic;

begin-- process keypressprocess(pkeyret)begincase pkeyret is

when "1110" => skeyhit <= '1';when "1101" => skeyhit <= '1';when "1011" => skeyhit <= '1';when "0111" => skeyhit <= '1';when others => skeyhit <= '0';


-- process keyvalprocess(skeyhit)begin

if( rising_edge(skeyhit)) thenif(skeyscn = "1110" and pkeyret = "1110")

then skeyval <= 0;elsif(skeyscn = "1110" and pkeyret = "1101")









then skeyval <= 9;

54

elsif(skeyscn = "1011" and pkeyret = "1011") then skeyval <= 10;






end if;end if;

end process;

-- process clk divider--process(pclk100k)begin

if( rising_edge(pclk100k)) thensclkdiv <= sclkdiv+1;

end if;

skeyclk <= sclkdiv(6);end process;

-- process for kexy scan clkscanprocess(pclk100k)

beginif(rising_edge(pclk100k)) then

if skeyscn = "1110" then skeyscn <= "1101";elsif skeyscn = "1101" then skeyscn <= "1011";elsif skeyscn = "1011" then skeyscn <= "0111";

elsif skeyscn = "0111" then skeyscn <= "1110";else skeyscn <= "1110";end if;

end if;pkeyscn <= skeyscn;end process;

-- process display 7segprocess(skeyval)type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);constant segval : tseg7 :=

("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000111","1111111","1

101111","1110111","1111100","1011000","1011110","1111001","1110001"); begin

pdspseg <= segval(skeyval);pdspmux <= "1110";

end process;

-- process display ledindprocess(skeyval)type tled8 is array(0 to 15) of std_logic_vector (7 downto 0);constant led8val : tled8 :=

("00000000","00000001","00000010","00000100", "00001000","00010000","00100000","01000000", "10000000","00001001","00001010","00001011", "00001100","00001101","00001110","00001111");

begin

55

pledind <= led8val(skeyval);end process;

end behavioral;

IC DIAGRAM:

RESULT: The key press and display unit has been successfully designed and implemented.

56

14 : ELEVATOR CONTROLLERAIM:

To design and implement a elevator controller.VHDL PROGRAM:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBELE is Port ( pkeyret : in std_logic_vector(3 downto 0);

pkeyscn : out std_logic_vector(3 downto 0); pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pclk100K : in std_logic

);end TKBELE;

architecture behavioral of TKBELE is

signal scurflr,snxtflr,skeyflr : integer range 0 to 15;signal sdir, skeyhit : std_logic; signal skeyscn : std_logic_vector(3 downto 0);signal sclkdiv : std_logic_vector(15 downto 0);signal sflrclk,skeyclk : std_logic;

begin-- process keypressprocess(pkeyret)begincase pkeyret is

when "1110" => skeyhit <= '1';when "1101" => skeyhit <= '1';when "1011" => skeyhit <= '1';when "0111" => skeyhit <= '1';when others => skeyhit <= '0';


-- process keyvalprocess(skeyhit)begin

if( rising_edge(skeyhit)) thenif(skeyscn = "1110" and pkeyret = "1110")

then skeyflr <= 0;elsif(skeyscn = "1110" and pkeyret = "1101")








57




then skeyflr <= 11; elsif(skeyscn = "0111" and pkeyret = "1110")




then skeyflr <= 15;end if;

end if;end process;

-- process clk divider--process(pclk100k)begin

if( rising_edge(pclk100k)) thensclkdiv <= sclkdiv+1;

end if;

skeyclk <= sclkdiv(6);sflrclk <= sclkdiv(15);

end process;

-- process for key scan clkscanprocess(skeyclk)begin

if(rising_edge(skeyclk)) thenif skeyscn = "1110" then skeyscn <= "1101";elsif skeyscn = "1101" then skeyscn <= "1011";elsif skeyscn = "1011" then skeyscn <= "0111";elsif skeyscn = "0111" then skeyscn <= "1110";else skeyscn <= "1110";end if;

end if;pkeyscn <= skeyscn;

end process;

-- process floor motionprocess(sflrclk)begin

if(rising_edge(sflrclk)) thenif(not (skeyflr = scurflr) ) then

if(skeyflr > scurflr) then scurflr <= scurflr+1;else scurflr <= scurflr-1;

end if;end if;

end if;end process;

-- process display 7segprocess(scurflr)type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);constant segval : tseg7 :=

("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000111",

58

"1111111","1101111","1110111","1111100","1011000","1011110","1111001","1110001"); begin

pdspseg <= segval(scurflr);pdspmux <= "1110";

end process;

end behavioral;

IC DIAGRAM:

RESULT: The elevator controller has been successfully designed and implemented.

59

15: MESSAGE DISPLAY UNIT.AIM:

To design and implement a message display unit.

VHDL PROGRAM:

entity msgdsp isport(pdspseg :out std_logic_vector(6 downto 0);

pdspmux :out std_logic_vector(3 downto 0);pclk100k:in std_logic);

end msgdsp;

architecture Behavioral of msgdsp issignal sclkdiv :std_logic_vector(15 downto 0);signal sdspnum :integer range 0 to 15;signal sblkdly :integer range 0 to 2;signal sdspseq :std_logic_vector(2 downto 0);signal sdspmux : std_logic_vector(3 downto 0);signal smuxclk,sdspstp : std_logic;begin

--process clk dividerprocess(pclk100k)begin

if(rising_edge(pclk100k))thensclkdiv<=sclkdiv+1;

end if;

smuxclk<=sclkdiv(0);sdspseq(0)<=sclkdiv(1);sdspseq(1)<=sclkdiv(2);sdspseq(2)<=sclkdiv(3);sdspstp<=sclkdiv(15);

end process;

--process diplay numberprocess(sdspstp)begin

if(rising_edge(sdspstp))thenif(sdspnum=4 or sdspnum=8)then sblkdly<=sblkdly+1;

if(sblkdly=2)then sdspnum<=sdspnum+1;end if;

elsesdspnum<=sdspnum+1;sblkdly<=0;

end if;end if;

end process;

--process display mux process(sdspseq) begin if(sdspseq="000")then sdspmux<="1110";

elsif(sdspseq="010")then sdspmux<="1101"; elsif(sdspseq="100")then sdspmux<="1011"; elsif(sdspseq="110")then sdspmux<="0111";else sdspmux<="1111";end if;pdspmux<=sdspmux;

end process;

--process muxdisp

60

process(sdspmux)type tseg7 is array (0 to 15) of std_logic_vector(6 downto 0);constant segval : tseg7 :=

("0000000","0000000","0000000","0000000", "0111001","0110111","1110111","0110000",

"1111000","1101101","0000111","1011011", "0000000","0000000","0000000","0000000");begin

if(sdspmux="1110")then pdspseg<=segval(sdspnum);elsif(sdspmux="1101")then pdspseg<=segval(sdspnum+1); elsif(sdspmux="1011")then pdspseg<=segval(sdspnum+2); elsif(sdspmux="0111")then pdspseg<=segval(sdspnum+3); else pdspseg<="0000000";

end if;end process;

end Behavioral;

IC DIAGRAM:

RESULT: The message display unit has been successfully designed andimplemented.

61

16(A): DAC TO GENERATE A SQUARE WAVE.AIM:

To design and implement a DAC to generate a square wave.

VHDL PROGRAM:


-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity dac_sqwave isport (clk, reset: in std_logic;clk0 :inout Std_logic;Dac_out:out std_logic_vector (7 downto 0));end dac_sqwave;

architecture Behavioral of dac_sqwave is signal q: std_logic_vector (7 downto 0); signal clk1: std_logic_vector(15 downto 0):= "0000000000000000";begin process (clk) begin if rising_edge (clk) then clk1<= clk1 +1; end if; end process; clk0<= clk1 (3); process (reset, clk0) begin if (reset = '1') then q <="00000000"; elsif (clk0 ='1' and clk0'event) then q<=not q; end if; end process; dac_out <= q; end Behavioral;

IC DIAGRAM:

62

VHDL MODULE

CPLD

KC-9752

0800

0800

26 PIN CONNECTOR

DAC

D0

D1

D2

D3

D4D5

D6

D7

CLK

RESET

-12 +12 GND+5

GND

O/P TO CRO

DAC MODULE (0800)

RESULT:The DAC to generate square wave has been successfully designed and implemented.

63

16(B): DAC TO GENERATE AN UP GOING RAMP.AIM:

To design and implement DAC to generate an up going ramp.

VHDL PROGRAM:


entity dac_upramp is Port ( reset,clk : in std_logic; clk0:inout std_logic; DAC_out : out std_logic_vector(7 downto 0));end dac_upramp;

architecture Behavioral of dac_upramp issignal q: std_logic_vector(7 downto 0):="11111111"; signal clk1: std_logic_vector (7 downto 0):= "00000000"; begin process (clk)

begin if rising_edge(clk) then clk1 <= clk1 +1; end if; clk0 <= clk1 (2); end process; process(clk0 , reset) begin

if(reset = '1') then q<="00000000"; elsif(clk0'event and clk0 ='1') then q<= q+1;

end if; end process; DAC_out <= q; end Behavioral;

IC DIAGRAM:

RESULT:The DAC to generate the up going ramp has been successfully designed and implemented.

64

16(c): DAC to generate a downward ramp.AIM:

To design and implement a DAC to generate a downward ramp.

VHDL PROGRAM:


entity dac_dwramp1 is Port ( reset,clk : in std_logic; DAC_out : out std_logic_vector(7 downto 0));end dac_dwramp1; architecture Behavioral of DAC_dwramp1 is

signal q: std_logic_vector(7 downto 0):="00000000"; begin process(clk , reset) begin

if(reset = '1') then q<="00000000"; elsif(clk'event and clk ='1') then

q<= q+1;if(q="10011001") then q<="00000000" ;

end if; end if; end process; DAC_out <= q; end Behavioral;

IC DIAGRAM:

65

VHDL MODULE

CPLD

KC-9752

0800

0800

26 PIN CONNECTOR

DAC

D0

D1

D2

D3

D4D5

D6

D7

CLK

RESET

-12 +12 GND+5

GND

O/P TO CRO

DAC MODULE (0800)

RESULT:DAC to generate a down going ramp has been successfully designed and implemented.

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DELAY PROGRAM

Used for :JK Flip flop,T-flip flop, all counters and sequence generator programs.

signal clk1: std_logic_vector(15 downto 0):=”0000000000000000”;begin

if(rising _edge(clk))thenclk1<=clk1+1;end if;clk0<=clk1(2);

end process;

Instructions:

1) Include the above program after ‘architecture’.2) Declare “clk0: inout std_logic” in entity.3) Change ‘clk’ to’clk0’ in the original program.

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06esl48 hdl lab2

Documents

vhdl code

asynchronous

synchronous

bcd counter

binary counter

vhdl program

electronics

flip