06728720.pdf

1656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014

A Wide-Range Level Shifter Using a ModifiedWilson Current Mirror Hybrid Buffer

Shien-Chun Luo, Member, IEEE, Ching-Ji Huang, and Yuan-Hua Chu

AbstractWide-range level shifters play critical roles in ultra-low-voltage circuits and systems. Although state-of-the-art levelshifters can convert a subthreshold voltage to the standard supplyvoltage, they may have limited operating ranges, which restrictthe flexibility of dynamic voltage scaling. Therefore, this paperpresents a novel level shifter, of which the operating range is froma deep subthreshold voltage to the standard supply voltage andincludes upward and downward level conversion. The proposedlevel shifter is a hybrid structure comprising a modified Wilsoncurrent mirror and generic CMOS logic gates. The simulation andmeasurement results were verified using a 65-nm technology. Theminimal operating voltage of the proposed level shifter was lessthan 200 mV based on the measurement results. In addition to theoperating range, the delay, power consumption, and duty cycle ofthe proposed level shifter were designed for practical applications.

Index TermsCurrent mirror, dynamic voltage scaling, levelshifter, process variation, subthreshold circuit, standard celllibrary.

I. INTRODUCTION

D YNAMIC VOLTAGE SCALING (DVS) has been widelyused in digital processing elements for reducing energyconsumption, and aggressive voltage scaling has extended thevoltage range into the subthreshold region [1]. The ultra-lowpower consumption of subthreshold operations facilitates thedevelopment of crucial applications, such as ubiquitous sensorsand miniature health-care devices [2][4]. Near-thresholdoperations of processors and memories achieve the optimalenergy consumption [5], whereas subthreshold operationsfurther reduce power consumption, enabling the operationsof autonomous sensor nodes that rely on energy scavenging.However, from a system perspective, subthreshold operationsare limited to part of the digital processing elements. Othersystem components, such as the power management unit, radio,actuators, and sensors, have distinct constraints in the supplyvoltage [4], where sub-to-suprathreshold level conversion isusually unavoidable. General-purpose applications also requirewide-range level shifters (LSs) if a system involves at least oneaggressive DVS domain [6].Wide-range LSs receive ultra-low voltage signals and use the

weak drive current of pull-down networks (PDNs) to overcomethe leakage of weakly conducting pull-up networks (PUNs).

Manuscript received May 27, 2013; revised September 30, 2013; acceptedNovember 06, 2013. Date of publication January 29, 2014; date of currentversion May 23, 2014. This paper was recommended by Associate Editor M.Alioto.The authors are with Industrial Technology Research Institute, Hsinchu 300,

Taiwan (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2013.2295015

When input level is subthreshold, the conversion results of LSsare vulnerable and easily affected by process, voltage, and tem-perature variations. Therefore, several subthreshold LSs wereproposed to solve this problem [6][12]. Although these LSs canconvert a subthreshold voltage, critical problems occur whenusing them in general DVS applications.First, previous subthreshold LSs may exhibit timing issues

when the input and output levels are close. Ultra-low-voltage(ULV) processors and memories usually support subthresholdand suprathreshold operations for enabling energy and per-formance trade-offs. Both wide-range and close-range levelconversion are required to achieve this flexibility. When inputand output levels are close, previous subthreshold LSs mayhave considerable skews in rising and falling delays becausethe drive strength of the PUNs was reduced. Although weakpull-up strength is favorable when input level is low, the risingdelay increases considerably when the input level becomeshigh. Therefore, the operating range is confined.In addition to the operating range, bidirectional LSs are crit-

ical for DVS applications. The voltage difference between twoDVS domains can be either positive or negative; in other words,a cross-domain path may require upward and downward levelconversion [13]. Although a riskless solution may involve usinga constant-voltage interface (such as a share bus), supplied withthe highest voltage of the DVS range, this riskless architectureconsumes extra power on the interface. Therefore, LSs withbidirectional level conversion improve the energy efficiency ofthe interface; however, this is a challenge for subthreshold LSs.This paper presents a novel LS that uses a modified Wilson

current mirror hybrid buffer (MWCMHB). The proposedMWCMHB LS was designed for full-range and bidirectionallevel conversion. The term full range indicates that the min-imal operating voltage can be deep subthreshold, close to theminimal supply voltage of digital circuits, and themaximal oper-ating voltage is the standard supply voltage defined in a transistortechnology. In addition to the operating range, the delay, powerconsumption, and duty cycle of LSs were carefully considered.The energy efficiency of wide-range level conversion was ex-amined. The low slew rate of subthreshold signals may lead toa long transition period and consume high short-circuit power[14]. To reduce this power consumption, robust subthresholdLSs require amendments with proper voltage assignment.The remainder of the paper is organized as follows: Section II

introduces state-of-the-art subthresholdLSs and provides a com-parison of five features; Section III presents the novel LS andcomparisons; Section IVdiscusses the energy efficiency ofwide-range level conversion; Section V provides the simulation andmeasurement results; andfinally, SectionVI offers a conclusion.

1549-8328 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

LUO et al.: A WIDE-RANGE LEVEL SHIFTER USING A MODIFIED WILSON CURRENT MIRROR HYBRID BUFFER 1657

Fig. 1. Conventional and related level shifters using. (a) a cross-coupled (CC)structure; (b) a current mirror (CM); (c) a Wilson current mirror (WCM) [7]; (d)a two-stage cross-coupled structure (TSCC) [8]; (e) cross-coupled NOR gatesand part of a NOR gate (CCPNR) [6]; (f) a logic error correction circuit (LECC)[9]. The transistors labeled were set equal for fair structural comparisonsin Section III.B.

II. SUBTHRESHOLD LEVEL SHIFTER: SURVEYS ANDQUALITATIVE COMPARISONS

Subthreshold LSs are surveyed in this section. A conven-tional cross-coupled (CC) LS is a differential cascade voltageswitch logic (DCVSL) for raising a low voltage level, as shownin Fig. 1(a). The drive strength of NMOS transistors is enhancedto overcome the leakage of weakly conducting PMOS transis-tors. The operating range of CC LSs depends on the transistorthreshold voltage (Vt) and size; however, the operating range ofCC LSs is difficult to extend to the subthreshold region (withrespect to the NMOS Vt) because the NMOS drive strength de-creases exponentially. For converting a subthreshold voltage,CC LSs require an exponential increase in NMOS transistorsize, which is impractical.Fig. 1(b) shows a conventional LS that uses a basic current

mirror (CM). The conventional CM LS can convert a deep sub-threshold level because a high drain-to-source voltage of PMOStransistors facilitates the construction of a stable current mirror,which offers an effective on-off current comparison at the outputnode. However, a high amount of quiescent current occurs whenthe input voltage is suprathreshold. This high power consump-tion limits the use of the conventional CM LS.Several subthreshold LSs have been proposed to overcome

the aforementioned limits of conventional CC and CM LSs.Fig. 1(c) shows a CM-type LS that uses a Wilson current mirror

TABLE IQUALITATIVE COMPARISONS FOR SUBTHRESHOLD AND WIDE-RANGE LEVEL

CONVERSION

(WCM), which clamps the quiescent power consumption undera suprathreshold input [7]. Fig. 1(d) shows a two-stage CC LS(TSCC), of which the pull-up driving strength is reduced by aheader NMOS, which expands the convertible input voltage [8].Fig. 1(e) shows a CC-type LS (CCPNR), in which the outputstage is a part of the NOR gate fed by the primary input to ac-celerate the overall LS speed [6]. Fig. 1(f) is a CM-type LS thatuses a logic error correction circuit (LECC), which monitorsinput and output signals to create an implicit pulse; the outputupdates data during the pulse [9].Table I shows five qualities involved in using an LS in wide-

range DVS applications. The proposed LS satisfies all five qual-ities. Each quality and the comparison are described in the fol-lowing paragraphs, and comparisons of the quantitative delay,power consumption, and duty cycle are presented in Section III.1) Small area for subthreshold level conversionA conventional CC LS requires an exponential increase intransistor size to convert a subthreshold level, whereas thearea of a standard cell must be constrained. This qualitywas considered in recent works, and the subthreshold LSsreferred to satisfy this basic criterion.

2) Low power consumption in suprathreshold operationsHigh quiescent power consumption occurs in conventionalCM and LECC LSs when they receive a suprathresholdvoltage input. A CM LS has a high quiescent currentbecause of the bias currents. Conversely, an LECC LSmay have an excessively narrow LECC pulse to updatethe output, where the function fails, and a short-circuitpath draws a high quiescent current.

3) Balanced rising and falling delay in the operating rangeBalanced rising and falling delay ensures a 50% signal dutycycle. This criterion can be relaxed considering a long datapath or a low clock frequency. However, the duty cycleof the WCM LS is problematic when its input and outputlevels are close. Because of a weak PUN, theWCMLS hasa long rising delay, which is up to one hundred times longerthan the falling delay (Fig. 5). This severe signal skew isnot easily tolerated.

4) Size- & Vt-insensitivity to the operating rangeTransistor size and Vt may determine the operating rangeof LSs. Therefore, insensitivity to transistor size and Vtenables an LS to be applied to various technologies and to


tolerate process variations. Analytically, CM types are su-perior to CC types in achieving this objective; the analyseshave been presented in an earlier study [15]. For CC-typeLSs, the effective operating region usually depends on thetransistor Vt. For example, the TSCC LS is a dual-Vt de-sign, but some subthreshold LSs may use triple-Vt transis-tors [10], [11], and other LSs use thick oxide and zero-Vttransistors [16], [17]. In addition, LSs implemented usingSOI may use body ties [18]. However, because this workfocused on LS structure and used single-Vt transistors,only the TSCC LS was involved and adapted to a single-Vtversion for comparison. Additional details are provided inthe quantitative comparisons.

5) Bidirectional level conversionConventionally, bidirectional LSs are optional for power-management expansion [19]. Downward level conversioncan be realized using only an inverter, unless the signalskew is highly sensitive. A conventional CC LS also sup-ports bidirectional level conversion in the suprathresholdregion. However, full-range bidirectional level conversionis challenging. Pull-up and pull-down strength must be an-alyzed for all combinations of input and output levels. CC,TSCC, and CCPNR LSs have limited bidirectional regionsbecause of unbalanced pull-up and pull-down strength. TheWCM and LECC LSs are suggested only for upward levelconversion. Details of bidirectional level conversion areprovided in Section III.B.

III. PROPOSED LEVEL SHIFTING STRUCTURE ANDQUANTITATIVE COMPARISONS

A. Proposed Level Shifting StructureThe proposed MWCMHB LS is a hybrid structure com-

prising a modified Wilson current mirror and CMOS logicgates. The input and output levels range from a subthresholdvoltage to the standard supply voltage defined in a transistortechnology. Bidirectional level conversion is available; that is,input and output levels can be scaled independently.The proposed LS structure is illustrated with three circuit

blocks, as shown in Fig. 2. A modified Wilson current mirror(MWCM) is located in Block 1. When VDD1 is subthresholdand VDD2 is high, the MWCM structure balances the risingand falling delay at Node A, without losing the original staticbias that is favored in the WCM LS [7]. However, when theVDD1 and VDD2 levels are close, the MWCM encounters thesame problem as the WCM does: the cascode PMOS has in-sufficient drive currents and increases the rising delay. There-fore, in Block 3, a delay path is designed adaptively to reducethe rising delay and maintain a moderate duty cycle. An outputinverter offers sufficient drive strength, which is required in astandard cell design. Unlike the CCPNR LS [6], which has asimilar structure, the proposed LS uses a CM-type amplifier, abalancing delay path, and a complementary OR gate in Block 2.The CM-type structure provides a wide operating range, and thestacked PMOS transistors in the complementary OR gate limitthe leakage current.Table II presents the operating conditions of the proposed LS.

When VIN rises, the rising signal from Nodes A and B that

Fig. 2. Proposed MWCMHB level shifter.

TABLE IIOPERATING STATUS OF THE PROPOSED LEVEL SHIFTER

achieves the trip-point voltage more quickly triggers the rise ofVOUT. The rising signal at Node A achieves the trip point firstwhen VDD2 is higher than , where is a voltagedrop related to MWCM output (Node A). By contrast, the risingsignal at Node B reaches the trip point first when VDD2 is lowerthan . When VIN falls, voltages of Nodes A and Bmust be low to trigger a fall of VOUT. The falling signal at NodeA is slow because the NMOS length of MWCM is upsized toreduce mismatch. Therefore, the fall of VOUT waits the fallingsignal at Node A to reach the trip point. TheMWCM has similarrising and falling delays when VDD2 is considerably greaterthan VDD1. The two VDD1 inverters used long channel lengthto balance the rising and falling delay when VDD2 is less thanVDD1.The transistor Vt has a limited effect on the operating range

of the proposed LS, whereas all low-Vt transistors (LVTs) wereused for performance. Using LVTs reduces circuit delay andpower consumption. The reduction in delay is straightforward;the reduction in power consumption is related to the short-cir-cuit power, which is high when the input level is ultra-low andhas a slow slew rate. In detail, NMOS LVTs reduce the tran-sition time and short-circuit power consumption; PMOS LVTsreduce the rising delay and the voltage drop ; however, theleakage power increases.Fig. 3 shows four simulation waveforms of the proposed LS.

The input level is constant at 0.2 V; the output levels are 1.2 V,0.5 V, 0.4 V, and 0.3 V, as shown in Figs. 3(a)(d). The risingsignal at Node A triggers VOUT in the first three cases, whereasthe rising signal at Node B triggers VOUT in the last case. Thehigh level at Node A exhibits a 0.1-V drop, which is the .The high level at Node A is , which trigger the riseof VOUT in most cases. When VDD2 is low, a weak 1 stilltrigger the rise of VOUT. As shown in Fig. 3(d), a 0.2-V signal


Fig. 3. Simulation waveforms and corresponding power consumption breakdown: (a) 0.21.2 V, 338 nW; (b) 0.20.5 V, 3.08 nW; (c) 0.20.4 V, 1.71 nW; (d)0.20.3 V, 0.87 nW. Percentage labeled is the dynamic fraction of power consumption. Input signal frequency is 0.5 MHz.

at Node B triggers a 0.3-V output. The extra leakage caused bythe voltage drop is restricted by approximately 10 times in theNOR gate, which uses small PMOS and NMOS sizes. There-fore, the voltage drop has a limited effect on overall leakage.Details are later shown in Table III. The corresponding break-down of power consumption is shown in Figs. 3(a)(d). Theinput frequency is 0.5 MHz. The percentage of static power in-creases when the output level or input frequency decreases.

B. Characteristics and ComparisonsThis section presents comparisons of the delay, power, and

duty cycle of the proposed and reference LSs. The proposed andreference LSs were simulated using a 65-nm technology. TheVt of LVTs in this technology is approximately 0.4 V. For a faircomparison of circuit structure, the key transistors (labeledW/Lsize in Fig. 1) used the same Vt, width, and length. The Vt andsizes were assigned as follows:

LVT PMOS with m/ m, andLVT NMOS with m/ m.

Although each LS can be further optimized, the common sizehelped to simulate the operating region without interferencefrom the Vt or size. Transistors with a long channel length havea superior low-voltage ratio in this technology. Othertransistors in LSs were assigned as follows. The PMOS in themiddle of the WCM LS used LVT with m/0.06m. The NMOS header of the first stage of the TSCC LS useda standard Vt transistor (SVT) with m/0.1 m.Other transistors in the LECC LS were sized according to the

size multiplier suggested in [9]. The simulation environmentcontained a standard buffer at the output of the CC, CM, andWCMLSs, which had no drive stage. The delay and power con-sumption on this buffer reflected all the voltage drops or lowslew rates of the LS. The standard buffer consisted of two stan-dard inverters, which used LVTs with m,

m, and m. The proposed LS also used thisstandard inverter as the drive stage.Fig. 4 shows the normalized and average delay of each LS in

2D histograms. The normalized delay is a metric for surveyingthe circuit delay in a wide voltage range. The normalized targetis a standard FO4 buffer, and each LS loads the same capac-itance as the buffer. The lower voltage of the input and outputlevels supplies the buffer used for normalization; in other words,the upward and downward LS delays are normalized to VDD1and VDD2 buffer delays, respectively. The normalized delaymay be less than 1 because part of the LS is supplied with ahigh voltage. The supply voltage ranges from 0.1 V to 1.2 V forboth input and output levels, and the simulation condition is atthe typical (TT) corner and 25 C.Normalized-delay histograms present the coarse delay and

operating range of LSs. The proposed structure has full-rangeoperability with 1.7 buffer delays on average. The CC andCCPNR LSs have low latency within the operating range,while they are unable to convert a near- or sub-threshold VIN.The conventional CM LS has the same full-range operabilityas that of the proposed LS, with 1.2 buffer delays on average.The single-Vt TSCC LS has a moderate speed restricted to


Fig. 4. Normalized delay of full-range and bidirectional level conversion.

Fig. 5. Power consumption of full-range and bidirectional level conversion.

some VIN-VOUT combinations because the NMOS headerreduces the circuit speed. The WCM and LECC LSs have ahigh speed when receiving an ultra-low voltage; however, theyare excessively slow or fail when VOUT is less than VIN.Fig. 5 shows the corresponding power consumption of each

LS in 2D histograms. The input frequency is 20 kHz, whichis slow for simplifying the full-range comparisons. Therefore,the power consumption at high voltages is mainly caused byleakage currents. The proposed MWCMHB, CC, WCM, andCCPNR LSs have similar static power consumption in the op-erating region. The CC and CCPNR LSs have high power con-sumption around the boundary of the failure region. The con-ventional CM LS is known for the high quiescent current at asuprathreshold voltage. The LECC LS fails when VIN is highand thus consumes high static power. The dashed lines in Fig. 5indicate the failure region, where the power consumption isshown in case of any incorrect DVS operation.Table III shows details of the power consumption of the pro-

posed LS; these values were quantized in Fig. 5. The top column

of Table III lists the power consumption of the standard inverterfor reference. These power values are manly caused by leakagewhen VDD1 is higher than 0.3 V; the power consumption ofthe LS is approximately 2.33.5 times that of the standard in-verter when . A substantial power increase isobserved when converting deep subthreshold VDD1. This highpower consumption is caused by the slow input slew rate; thisproblem and solution are discussed later in Section IV.Fig. 6 shows the 2D duty-cycle histogram of each LS. The

duty cycle is equal to the smaller delay between rising andfalling delays divided by their sum. An ideal duty cycle is50%, whereas a moderate percentage is acceptable because ageneral clock period can be more than one hundred times theLS delay. The average duty cycle of the proposed LS is 36%.Fig. 6 labels a failure mark if the duty cycle is less than 1%.Therefore, WCM and LECC LSs have more failure blocks inthe duty-cycle histograms than in the delay histograms.The bidirectional level-conversion region can be analyzed ac-

cording to the normalized-delay histograms. A bidirectional LS


TABLE IIIPOWER CONSUMPTION DETAILS AND COMPARISONS (@20 KHZ)

Fig. 6. Duty cycle of full-range and bidirectional level conversion.

must have a symmetric operating region with respect to the 45diagonal as illustrated in Figs. 4 and 6. For example, the oper-ability region of the CC LS includes symmetric 0.6 V0.7 V and0.7 V0.6 V combinations. However, achieving bidirectionallevel conversion in the full range is challenging. As shown inFigs. 4 and 6, the proposed and CM LSs support full-range levelconversion; CC, CCPNR, and TSCC LSs have limited bidirec-tional level conversion range;WCM and LECC LSs support up-ward level conversion only.Based on Figs. 4, 5, and 6, a solution for constructing full-

range LSs is shown in Fig. 7: a combined structure consistingof different LSs that are complementary in the operating region(e.g., a CC-WCM combined LS). However, the overall powerconsumptionmust be considered if an LS fails in some operating

Fig. 7. An available full-range level shifter structure; overheads in power con-sumption and automatic selection (SEL) must be considered.

ranges. For example, if CC and WCM LSs are combined, thenhigh power consumption will occur around the failure boundaryof the CC LS. To prevent high power consumption in this case,automatic multiplexing and power-gating control can be used;however, a high overhead in circuit design and system controlis the drawback.


IV. ENERGY EFFICIENCY OFWIDE-RANGE LEVEL CONVERSIONThe energy efficiency of wide-range level conversion

requires a specific consideration of short-circuit power. Alow-voltage input signal has a slow slew rate, which increasesthe transition time and short-circuit power of the high-voltagepart of an LS. For the LSs that can convert subthreshold signals(MWCMHB, CM, WCM, LECC), the row of Vand the column of V in Fig. 5 show the powergradient is steep. This power consumption on the interfacedeteriorates the energy efficiency of a deep subthreshold core.To solve this problem, a robust subthreshold LS may be adaptedand cascaded into two stages. For clarity, simplified equationsof the energy consumption of an ULV core and its interface arepresented as follows:

(1)(2)(3)

represents the bit width of data, and is theenergy consumption for converting a bit from VDD1 to VDD2;this energy is the product of three elements: transition time

, average short-circuit current , and outputlevel VDD2. Subthreshold VDD1 leads to considerable powerconsumption because the reciprocal of is exponentialto VDD1. Dividing the level conversion into two steps mayreduce the overall energy consumption. If an intermediate,VDDM, is added, then the overall LS energy consumption willbecome

(4)

which is separated into two LS energy components and an en-ergy overhead related to voltage regulators. The two LS energyterms inside (4) are explicated as follows:

(5)

has a factor of VDDM in the numerator and a factorof in the denominator [20]. The first derivative of (4)with respect to VDDM can be used to determine the minimalenergy consumption. However, a quick solution can be deter-mined without calculation. When a subthreshold VDD1 and asuprathreshold VDD2 are considered, (5) implies that a near-threshold VDDM is an approximate solution for minimal en-ergy consumption. This occurs because increasing or decreasingVDDM results in an exponential growth in the first or secondterm, respectively. The simulation results rather than analyticalresults are discussed here for application purposes.Fig. 8 shows the post-layout simulation results of two

MWCMHB LSs that are cascaded with an intermediate VDDMlevel. In Fig. 8, the output level is 1.2 V, and the input period isequal to 100 FO4 VDD1 buffer delays. The input frequency is7 kHz at 0.1 V, 70 kHz at 0.2 V, 700 kHz at 0.3 V, and 7 MHzat 0.4 V. For every VDD1, VDDM is swept from VDD1 to 1.2V. All power-consumption curves are upward concave. The

Fig. 8. Power consumption of two cascaded MWCMHB LSs with an interme-diate VDDM level. The minimum point of each curve is magnified. The inputsignal period of each VDD1 curve is 100 VDD1 buffer delay.

Fig. 9. Normalized delay of two cascaded MWCMHB LSs with an interme-diate VDDM level. The normalization target is an FO4 VDD1 buffer delay.

minimal points are enlarged; the power saving is exponential. Anear-optimal VDDM may be arbitrarily set to a near-thresholdvalue higher than Vt ( V). When VDDM deviates fromnear-threshold voltages, the condition is similar to that of asingle-stage structure. Fig. 9 shows that the two-stage LS delayconverges after the near-threshold region, which indicates aslight delay overhead. For reference, a single-stage LS delaycan be implied at V because the second LSdelay is negligible.In summary, a cascaded LS structure with a near-threshold

intermediate level reduces power consumption exponentiallywhen the input level is deep subthreshold and the output levelis suprathreshold. Near-threshold circuits play critical roles inULV systems; they achieve the optimal energy consumptionand can act as intermediates between deep subthreshold andsuprathreshold circuits for reducing energy consumption. Al-though aforementioned power consumption may limit the real-istic operating range of LSs, subthreshold LSs remain necessarybecause DVS in the near-threshold region usually involves partof the subthreshold region. Full-range LSs also remain substan-tial because DVS systems require wide-range, flexible, and bidi-rectional level conversion. Moreover, an operating range widerthan the specification ensures signal integrity considering thesupply voltage fluctuation and process variations that affect theoperating range of LSs.

V. SIMULATION AND MEASUREMENT RESULTSThe proposed MWCMHB LS is a cell of a voltage-scalable

standard cell library; the area of is 4.2 m by 4 m, which isa double-height standard-cell layout, as shown in Fig. 10. The


Fig. 10. MWCMHB LS layout.

Fig. 11. Monte Carlo simulation results of MWCMHB LS.

default placement of the LS is a VDD2 domain. The area of theproposed LS approximates that of a generic flip-flop; generally,the area of LSs is small compared with multi-VDD cores andpower meshes. Increasing the current mirror area can reducemismatch, and the layout presented here was a trade-off resultconsidering functional robustness and cell area.Corners and random variations were considered in the char-

acterization. The minimal convertible voltage is less than 0.1 Vat all corners when VDD2 is greater than 0.4 V. The FS (FNSP)corner is the worst corner for the operating range. When VDD2is 0.3 V, the minimal convertible VDD1 is 0.18 V at the FScorner, while it is less than 0.1 V at the other four corners.Fig. 11 shows the cumulative distribution of the post-layout

Monte-Carlo (MC) simulation results, where VDD2 is 1.2 V.From to random variations were set in simulations topredict the LS delay and success rate of level conversion. TheMC simulations indicate that the robust operating range is

greater than 0.25 V, which is higher than those at the corners.The distance between 100% and the maximal percentage ofcurves indicates the failure percentage. The success rate ofMC simulations is 98%, 90%, and 52% when VDD1 is 0.25 V,0.2 V, and 0.15 V, respectively. The process control over randomvariation has a strong effect on the operating range.Test chips were fabricated using the 65 nm technology re-

ferred to in previous simulations. Fig. 12(a) shows the test cir-cuits, which consist of three delay paths with an identical inputand separate outputs. The delay paths are LS chains constructedby the proposed MWCMHB LSs. Fig. 12(b) shows the layoutof the test circuits, and Fig. 12(c) shows the photo of the testcircuits (part of a die). The notations of VDD were changed toVDDH and VDDL in the test circuits because VDDH must be

Fig. 12. Test circuits: (a) functional block diagram, (b) layout view, and (c)corresponding test circuits in the die photo.

no less than VDDL here. Each LS chain delay was designed asfollows:

(6)(7)

(8)

Di and Do are the input and output circuit delays, respectively.The input and output circuits of the three paths are identicaland supplied by a constant 1-V VIO. Unavoidable parasiticmismatch among paths can be neglected when measuringlow-voltage LS delay. D2 is a LS delay when the input andoutput levels are VDDH. D1 is the delay of two cascaded LSsthat have VDDH input, VDDL intermediate, and VDDH outputlevels. Therefore, D1 includes a downward and an upwardLS delays, which are difficult to separate further in this teststructure. Two phase differences were monitored: one phasedifference from Output Pads P2 to P1 and the other from OutputPads P2 to P3. The representative LS delay, D1, was obtainedusing the linear operations of (6), (7), and (8), where D2 andthe I/O related delay were canceled.Fig. 13(a) displays the simulated and measured D1, where

VDDH is constant at 1.2 V. The VDDL in this plot is boundedbecause the parasitic mismatch between Di and Do paths startedto interfere with the accuracy at VDDL above 0.7 V. Similarly,Fig. 13(b) displays the measured D1 delay when VDDH is 0.5V. An IC tester was used to sweep low-voltage VDDL in stepsof 5 mV. These measurement results indicate successful bidi-rectional level conversion because the delay path contained lowand high levels. The post-layout simulation results were ob-tained from the same phase-difference calculation. The mea-sured and simulated delays have a high correlation; however, themeasured delays are longer than simulated values at low VDDLvalues.Fig. 14 shows the histogram of the minimal convertible

VDDL respect to three VDDH values. The minimal VDDLis distributed from 0.145 V to 0.2 V among 17 test chips.The minimal VDDL of a test chip may decrease as VDDH


Fig. 13. Post-layout simulation and measurement results of D1 delay.

Fig. 14. Histogram of the minimal convertible VDDL.

Fig. 15. Power consumption of the INPUT-P3 delay path.

decreases. The middle of the distribution is 165 mV, which issimilar to the MC simulation results.A chip-on-board environment was set to the 18th test chip

for monitoring the power consumed by deep subthreshold levelconversion. The reason is that the test load board had an accu-racy problem to measure a low-frequency ( kHz) current. Alow frequency of 10 kHz was set to the test circuit, and Fig. 15shows the measurement results, of which the increase is rapidwhen VDDL is below 0.3 V.The power consumption of the entire test circuits was mea-

sured to compare with the simulation results; the purpose wasto obtain sufficient power consumption for reliable accuracy.Fig. 16 illustrates the simulated and measured power consump-tion of the entire test circuits, where VDDL and VDDH were

Fig. 16. Measured and simulated power consumption of the entire test circuits.The power consumption of the entire test circuits provides a reliable comparisonconsidering the measurement resolution of the IC tester.

set equal to simply the presentation. The measurement resultsin Fig. 16 were aggregated from the tester. In each category,17 thin bars are corresponding power consumption of the 17test chips, and a solid point indicates the value obtained frompost-layout simulations. Fig. 16 shows that the measured powerhas a high correlation to the simulation results. The measuredpower is expected to be higher due to the leakages of the I/Opads and load board. The supply voltages covered from sub-threshold to suprathreshold regions; the measurement results in-dicate that the simulated power consumption can be valid in awide voltage range.

VI. CONCLUSIONA novel full-range level shifter was proposed for aggres-

sive DVS applications. The delay, power consumption, andduty cycle of the proposed level shifter were verified for thefull-range operability. The short-circuit power of convertingdeep subthreshold signals was noted and can be solved byinserting a near-threshold supply voltage. Various simulationsand measurements validated the proposed design. The minimalconvertible voltage was less than 300 mV from the statisticalsimulations and less than 200 mV according to the measure-ment results.


ACKNOWLEDGMENTThe authors would like to express their gratitude toMr.W.-D.

Hsieh for his technical support of IC test system and chip mea-surement.

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Shien-Chun Luo (S06M11) received the B.S. de-gree in electronics engineering from National ChiaoTung University, Hsinchu, Taiwan, in 2004 and thePh.D. degree in electrical engineering from NationalChung Kung University, Tainan, Taiwan, in 2011.He joined Industrial Technology Research Institute

(ITRI), Taiwan, in 2011 and is currently an engineerof Division for Biomedical and Industrial IC Tech-nology. His research interests include low-power de-sign and energy-efficient circuits and systems.

Ching-Ji Huang received the M.S. degree inelectronics engineering from National CentralUniversity, Jung-Li, Taiwan, in 2003.In 2004, he joined Industrial Technology Research

Institute (ITRI), Taiwan, as a design engineer.His research interests include analog behavioralmodels for system verification, ESD protectioncircuit design, and standard cell library design andcharacterization.

Yuan-Hua Chu received the B.S. degree in elec-trophysics and the M.S. degree in electronicsengineering from National Chiao Tung University,Hsinchu, Taiwan, in 1981 and 1983, respectively.He is now with the Biomedical and Industrial IC

Technology Division, Information and Communica-tions Research Laboratories (ICL), Industrial Tech-nology Research Institute (ITRI), as a technical di-rector. His research interests include low-power cir-cuits, design methodology, and design automation.

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