061213iedm_liu.pdf

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Advanced FinFET CMOS Technology:

TiN-Gate, Fin-Height Control and

Asymmetric Gate Insulator Thickness 4T-FinFETs

Y. X. Liu, T. Matsukawa, K. Endo, M. Masahara, K. Ishii ,

S. O’uchi, H. Yamauchi, J. Tsukada, Y. Ishikawa and E. Suzuki

National Institute of

Advanced Industrial Science and Technology ( AIST)

Japan

1IEDM-2006

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2IEDM-2006

Outline

• Background and motivation• Precise Si-fin fabrication by a wet process

• TiN-gate FinFET CMOS with symmetrical Vth

• Asymmetric gate oxide thickness 4T-FinFETs

• Fin-height controlled FinFET CMOS

• Conclusion

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Background and motivation

3IEDM-2006

2005 2010 2015 20200

10

20

30

40

50

Year

P h y s i c a l L

g [ n m ]

ITRS2005 for HP

Planar Bulk CMOS

UTB FD SOI CMOS

DG or Multi-gate CMOS

• Continuous scaling-down is difficult in planar bulk CMOS.• Double-gate MOSFET is the ultimate MOS device.

B O X

G

X2008

2011

S

G S C E s u p p r e s s i o n

G

BOX

S D

S D

BOX

S

D

G

Lg = 5 nm

Lg = 10 nm

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Requirements and challenges

4IEDM-2006

(1) Ultra-thin and uniform Si-fin fabrication

(2) Correct setting of Vth for NMOS and PMOS

metal gatefluctuated

BOX

heavy doping

rough Si-fin

BOX

uniform Si-fin

• Ultra-thin and uniform Si-fin

• Smooth surface and damage-free

• Poor reproducibility

• Rough surface and damage

• Mobil ity degradation

• Vth fluctuation

• Correct Vth

by gate work function

• Non-doped channel

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5IEDM-2006

(3) Dynamic Vth control for power management

Symmetric tox 4T-FinFET

(4) Current matching for FinFET CMOS

PMOSNMOS PMOSNMOS

• Multi-fins for PMOS

due to small eff • Large area penalty

• Higher fin for PMOS to

match current• Small area penalty

BOX

G1 G2

tox1 = tox2

Asymmetric tox 4T-FinFET

G1 G2

tox1 < tox2

Id

Vg1

Id

Vg1

Vg2 Vg2

Poor S-slope Good S-slope

BOX

Hfin

I d

Weff = 2Hfin

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6IEDM-2006

Outline




• Fin-height controlled CMOS

• Conclusion

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Precise Si-fin fabrication by a wet process

7IEDM-2006

( 1 1 0 )

< 1 1 2 >

fin-mask Si-fin

TMAHSi-fins

400 nm

RIE WET< 1 1

2 >

(110)SOI ( 1

1 1 )

BOX

Substrate500 nm

267 nm

16 nm

• The channel surface of the Si-fin by the wet process is much

smoother than that by the conventional RIE process.• The wet process is very useful for the ultra-thin Si-fin fabrication.

( 1 1 1 )

BOX

SOI

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

50

100

150

200

250

300

350

400

450

Effective Field [ MV/cm ]

TSi = 78 nm TSi = 98 nm TSi = 118 nm

NA = 1.6x1016

cm-3

1.1x1017

e f f

[ c m

2 / V s e c ]

0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

50

100

150

200

250

300

350

400

450

Effective Field [ MV/cm ]

TSi = 98 nm TSi = 118 nm TSi = 138 nm TSi = 86 nm

NA = 1.6x1016

cm-3

1.1x1017

8IEDM-2006

Wet etchingRIE

=1/3 =1/38.5 % up

u n i v e r s a l

e f f

u n i v e r s a l e f f

(111) (111)

hole

electronelectron

Comparison between the effective mobilities in the

FinFETs fabricated by the wet and RIE processes

• Experimental eff ’s show good agreement with

the universal curves for (111) bulk MOSFETs.

• 8.5 % improvement in eff is obtained.

Damage-free and smooth

Si-fin channel surface.

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9IEDM-2006

Outline





• Conclusion

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10IEDM-2006

Conformal TiN deposition by pressure optimized PVD

120 nm

55 nm

fin-mask

TiN

TiN

TiNVoids

P = 0.5 Pa P = 1 Pa

TiN

TiN

Uniform

• Conformal TiN deposition on the upright sidewalls of the Si-finis realized by the pressure optimized PVD.

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-1.5 -1 -0.5 0 0.5 1 1.5

10-12

10-11

10-1010

-9

10-8

10-7

10-610

-5

10-4

10-3

Gate Voltage, V g [ V ]

D r a i n C u r r e n t , I d [

A

]

-1.5 -1 -0.5 0 0.5 1 1.5

10-12

10-11

10-1010

-9

10-8

10-7

10-6

10-5

10-4

10-3

Gate Voltage, V g [ V ]

D r a i n

C u r r e n t , I d [ A

]

11IEDM-2006

S =

6 5

m V / d

e c

S = 6 4

m V / d e c

Weff =7.5 m

NMOSPMOS

|Vd | = 1 V

0.05 V

• Almost symmetrical Vth’s (normally off) are obtained thanksto the midgap work function of the sputtered TiN (4.82 eV).

n+ poly-Si gate TiN-gate

Symmetric Vth Asymmetric Vth

Id-Vg for nondoped Si-fin channel FinFETs

NMOSPMOS

|Vd | = 1 V

0.05 V

Weff =17 m

S =

7 8

m V / d

e c

S = 6

3 m

V / d e c

Lg = 21 mWeff =7.5 mLg = 21 m

Weff =17 m

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• TiN gate FinFET CMOS inverter is fabricated with 2-fin NMOS and 5-fin PMOS.

• Wn = 304 nm for NMOS, Wp = 1030 nm for PMOS, and Wp / Wn = 3.4.

PMOS

NMOS

VDD

VSS

VIN

5-fins, Hfin = 103 nm

2-fins, Hfin = 76 nm

VOUTLg = 1 m

G

5 m

12IEDM-2006

Fabricated TiN gate FinFET CMOS inverter

VDD

VIN

VSS

VOUT

PMOS

NMOS

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0 0.5 1 1.50

0.5

1

1.5

Vin

[ V ]

V o u t

[ V ]

V DD = 0.5 to 1.5 Vstep = 0.1 V

0 0.5 1 1.5 20

0.5

1

VDD [ V ]

V T H G [

V

]

CMOS inverter characteristics

13IEDM-2006

VDD

VSS

VoutVin

• Excellent transfer characteristics are obtained thanks to the well-symmetrical Vth’s

of the NMOS and PMOS. The logic gate threshold voltage (VTHG) closes to VDD/2.

Lg

= 1 m

2 DD

THG

V V

VDD = 1.5 V

0.5 V

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14IEDM-2006

Outline





• Conclusion

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-1.5 -1 -0.5 0 0.5 1 1.510-13

10-12

10-1110

-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Vg [ V ]

I d [ A

]

Metal-1 Metal-2NMOS PMOS

Dual metal-gate

Vth control for high-performance and low-power CMOS

Vth controllable asymmetric

gate oxide thickness 4T-FinFET

G1 G2

tox1 < tox2

Id

Vg1

Vg2

Vth = 0.5 VVth = -0.5 V

NMOSPMOS

TiN-gate CMOS

• The high Vth’s of the TiN-gate

FinFETs are not suitable for

high-performance CMOS.

2-finHfin = 76 nm

5-finHfin = 103 nm Lg = 1 m

15This work

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(110)SOI

SiO2 tox2 resist

Si-fin

tox1 tox2

G a t e - 2 r e g i o n

G

a t e - 1 r e g i o n

S i O 2

E B

- r e s i s t m a s k

G a t e - 2 r e g i o n

G

a t e - 1 r e g i o n

Source

Drain

Source

Drain

BOX

16IEDM-2006

• Perfect alignment between gate-1 and gate-2 regions can be confirmed.

• Two-step oxidation produces asymmetric gate oxide thicknesses.

Asymmetric gate oxide thickness 4T-FinFET fabrication

tox2tox1 <

(a) (b) (c)

Gate-1region Gate-2region

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17IEDM-2006

(d) (e) (f) (g)

TiN

EB-resist top SiO2 RIE

TiN

fin

fin

EB-resist top SiO2Separated

G1 G2

BOX

Resist etch-back process to separate

connected TiN-gate on the top of Si-fin

• The resist thickness on top of the Si-fin is much thinner than

that on the sidewall area of the Si-fin.

• This process is very useful for fabricating 3T/4T co-integration

on the same wafer.

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TiN

tox2 = 3.4 nmtox1 = 1.7 nmGate-1 Gate-2

tox1

< tox2

80 nm

TSi = 11 nm

Asymmetric tox 4T-FinFET

tox1 tox2

TSi

Hfin = 192 nm

Hfin/TSi = 18

18IEDM-2006

TiN

tox2tox1

TSi = 12 nm

Symmetric tox 4T-FinFET

Gate-1 Gate-2

tox1 = tox2 =1.7 nm

60 nm

STEM images of the fabricated

independent double-gate 4T-FinFETs

• TiN gates are completely separated at the top of Si-fin.

• Asymmetric gate oxide thicknesses (tox1 < tox2) are clearly confirmed.

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IEDM-2006

-1.2 -0.8 -0.4 0 0.4 0.8 1.2-0.5

0

0.5

1

1.5

0

100

200

= 0.68 (tox2 =1.7 nm) = 0.57 (tox2 = 3.4 nm) = 0.32 (tox2 = 7.0 nm)

Vg2 [ V ]

V t h

[ V

]

S - s l o p e [ m V / d e c ]

2g

th

V

V

20

Summary of the S-slope and Vth controllability

Siox

ox

g

th

T t t

V V

2

1

2 33

)1(60 S

• S-slope degradation in 4T-FinFET at high Vg2 region iseffectively suppressed by introducing asymmetric tox.

2

1

2 3

3

ox

Siox

g

th

t

T t

V

V

(Ch-2 depletion)

(Ch-2 inversion)

Ch-2Ch-1

Ch-2 depletion Inversion

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21IEDM-2006

Outline




• Fin-height controlled FinFET CMOS

• Conclusion

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23IEDM-2006

Fabrication process flow

70 nmTiN

BOX

(110) SOI

SiO2-mask

LOCOS

Fin-mask

Step

Si-fins

Gate SiO2

TiN

(a)

(b)

(c)

(d)

• Different Si-fin heights on the same wafer are confirmed.

20 nm

400 nm

Lower-fin Higher-fin

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-1.5 -1 -0.5 0 0.5 1 1.50

5

10

Vd [ V ]

I d

[ A

]

IEDM-2006

Hn = 98 nm

24

Current matching by tuning NMOS fin-height

• Current matching for FinFET CMOS is realized by controlling Hn to Hp/2.

PMOS

NMOS

Hp = 103 nm

Hn

Lg = 1 m

5 m

Hp= 103 nm

76 nm

57 nm

PMOS

NMOS

A

A’

PMOS

BOX

NMOSHn

changed

A-A’ cross-section

|Vg| = 1 V

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25IEDM-2006

Conclusion

• The advanced TiN metal gate FinFET CMOS fabrication

processes including the precise and uniform Si-fin formation,

TiN-gate, fin-height control and asymmetric gate oxide

thickness 4T-FinFET have successfully been developed.

• Using the newly developed technologies, the TiN metal gate

FinFET CMOS inverter with an excellent transfer performance,

and the flexible Vth-controllable asymmetric gate oxide

thickness 4T-FinFETs with a greatly improved S-slope, and

the fin-height controlled FinFET CMOS with a good current

matching have been demonstrated.

• The developed technologies are attractive to materialize the

high-performance and power-managed FinFET CMOS circuits.

061213iedm_liu.pdf

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