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A Transformerless Grid Connected Photovoltaic

Inverter with Switched Capacitors

Yunjie Gu, Wuhua Li, Bo Yang, Jiande Wu, Yan Deng, Xiangning He

College of Electrical Engineering, Zhejiang University

Hangzhou, 310027, P.R. ChinaEmail: HUwoohualee@zju.edu.cn U

AbstractIn the transformerless photovoltaic (PV) system, thecommon mode ground leakage current may appear due to the

galvanic connection between the PV array and the ground,

which causes the safety issues and reduces the efficiency. To

solve this problem, a novel inverter topology with switched

capacitors is proposed in this paper. By connecting one pole of

the PV cell directly to the neutral line of the grid, the common

mode current is eliminated. Meanwhile, the switched capacitor

technology is applied to increase the DC voltage utilization rate.

Furthermore, a modified unipolar sinusoidal pulse width

modulation (SPWM) strategy is proposed to reduce thepulsating current caused by the charging and discharging

operations of the switched capacitors. Also, several optimization

principles are put forward to further reduce the pulsating

current to improve the efficiency and reliability. Finally, the

proposed topology and modulation strategy are verified with

simulation and a 250W experimental prototype.

I. INTRODUCTIONIssues such as reliability, high efficiency, small size and

weight, and low price are of great importance to theconversion stage of PV power generation systems [1].Removing the isolation transformer in the PV system can be

an effective way to reach this goal [2]. But if the transformeris omitted, a galvanic connection between the grid and the PVcell exists, thus the common mode ground leakage currentmay appear through the stray capacitance between the PV celland the ground, which causes the safety issues and reducesthe efficiency [3].

The common mode current can be avoided by usingbipolar SPWM in the conventional full bridge inverter. Butthe switching losses and the volume of the output filter arerelatively large compared with the unipolar SPWM method.The neutral point clamped (NPC) half bridge inverter can alsobe employed to eliminate the common mode current [4].However, a much higher DC input voltage is required, which

limits the MPPT range of the PV arrays.

In this paper, a novel tranformerless inverter topologywith the switched capacitors is proposed, which eliminatesthe common mode current by connecting one pole of the PVcell directly to the neutral line of the grid. Meanwhile, theswitched capacitor technology is applied to increase the DCvoltage utilization rate, so that the proposed topology requiresthe same DC input voltage as the full bridge inverter.Furthermore, a modified unipolar SPWM strategy is proposed

to guarantee that the switched capacitors are charged everyswitching cycle in order to reduce the pulsating current,therefore improving the efficiency and reliability.

This paper also quantitatively analyzes the maximumcurrent stress on the power devices caused by the charging ofswitched capacitors, and gives a design guideline to select thecapacitances to optimize performance. Finally, the proposedtopology and modulation strategy are verified with simulation

and a 250W experimental prototype.

II. PROPOSED TOPOLOGY AND MODULATION STRATEGYThe proposed topology is shown in Fig 1. The negative

pole of the PV array is directly connected to the neutral line

of grid, so the voltage across the parasitic capacitor CPVandthe ground impedance ZGis constantly zero and the commonmode current can be eliminated perfectly. C1 is the inputcapacitor and C2is used to generate the minus voltage via theswitched capacitors method to increase the DC voltageutilization rate.Lis the output filtering inductor.

The modified unipolar SPWM strategy of this topology isdisplayed in Fig 2. During the positive half cycle, S1and S3are turned on and S2is turned off, while S4and S5commutateat high frequency complementally. The capacitors C1and C2are in parallel. The circuit rotates between state (a) and state(b), as shown in Fig 3.

During the negative half cycle, S5 is turned on and S4 is

turned off. S1 and S3 commutate at high frequencysynchronously and S2 commutates in complement to them.The circuit rotates between state (b) and state (c). At state (b),

This work is sponsored by the National Nature Science Foundation of China(50907058) and the Power Electronics S&E Development Program of Delta

Environmental & Education Foundation (DREM2009001).

978-1-4244-8085-2/11/$26.00 2011 IEEE 1940

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C2is charged by C1and the DC source. If the capacitances ofC1 and C2 are large enough, the time constant of the RCcircuit formed by C1, C2and the equivalent resistances in thecharging loop is much larger than the switching period, so thevoltage across C1and C2will change linearly, as shown in Fig4, and the charging current can be seen as constant within oneswitching cycle. At state (c), S1and S3are turned off while S2is turned on, and the minus voltage is generated by C2,

therefore increasing the DC voltage utilization rate of theinverter. During this state, C1 is charged by the DC inputcurrent, and C2is discharged by the grid current. The voltageacross them either increases or decreases linearly.

Fig 1.Proposed topology.

Fig 2.Unipolar SPWM for proposed topology.

The main characteristic of the proposed topology is thatpulsating current with much larger values than the output

current may appear on S1 and S3 during the negative halfcycle because of the charging of C2at state (b). This pulsatingcurrent increases the conduction and switching losses.Moreover, the increased current stress may cause reliabilityproblems for the power semiconductor devices due to theirsensitivity to the over current. Therefore, proper methodsshould be taken to make sure that the current pulse is as smallas possible. The modified unipolar SPWM strategy above

will guarantee that C2 is charged every switching cycle, sothat the current stress is limited.

The proper design of the circuits parameters, such as thevalues of C1and C2and the maximum duty cycle, can furtherreduce the pulsating current. This is described in detail below.

state (a)

state (b)

state (c)

Fig 3.Circuits operation states.

vC1

vC2

c b c c c c cb b b b

Fig 4.Capacitor voltage during the negative half cycle.

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III. PULSATING CURRENT ANALYSIS AND OPTIMIZATIONDuring the positive half cycle, the proposed topology

works just like the full bridge inverter under the unipolarSPWM. During the negative half cycle, the charging of theswitched capacitors leads to the pulsating current on thepower devices at state (b), resulting in differentcharacteristics from the full bridge. Reducing the maximumcurrent stress on the power switches iSmax is critical in

improving the reliability and efficiency. For this reason, iSmaxthrough S1and S3during the negative half grid cycle shouldbe analyzed in detail.

Supposing that the time constant of the RC circuit formedby the loop of C1 charging C2 is much larger than theswitching period, the voltage and current though C1 and C2can be assumed to be constant in a single switching state.With the small ripple approximation method, the currentstress on S1during state (b) can be derived as following

2 11

1 2 1 2

1SS bus grid T

C Cdi I i

d C C d C C

(1)

where d is the duty cycle and is defined as

2Time when S is on

Switch periodd ; igrid is the output current and its

reference direction is shown in Fig 1;Sgrid T

i is the small

ripple approximation of igrid, and TS is the switching period;Ibusis the average value of the DC input current from the PVarray.

Neglecting the phase shift caused by the output inductor,

Sgrid Ti and d can be written as synchronous sinusoidal

functions

sin( )Sgrid T grid

i I t

sin( )md D t

where Igrid is the amplitude of output current and Dm is themaximum duty cycle.

Apparently, the maximum value of iS1 comes when

sin( ) 1t , and can be simplified as below

11

1 2

1( 1)

2

mS max grid

m

D Ci I

D C C

(2)

Similarly, it can be deduced that

13

1 2

1( 1)

2

mS max grid grid

m

D Ci I I

D C C

(3)

From (2) and (3), it can be seen that iS1max and iS3max areaffected by three parameters, namelyIgrid,Dmand C1/(C1+C2).Based on the results above, proper optimization method canbe taken to reduce iSmax.

Igrid is determined by the output power and cannot bealternated. Dm=Vgrid /Vbus, so a higher Vbus is preferred toreduce iSmax. C1/(C1+C2) can be set by the designer. On onehand, C1/(C1+C2) should be as small as possible to reduce

iSmax. On the other hand, C1 should not be too small, or elsethe time constant of the RC circuit formed at state (b) by C1,C2 and equivalent resistances of S1 and S3 will be smallerthan TS, so that the small ripple assumption no longer holdstrue. When C1is very small, voltage across it will be chargedto be very high during state (c), and drops suddenly when S1and S3 turn on, resulting in high pulsating current on thedevices. This situation should be avoided.

As a trade off, principles below can be used in optimizingthe capacitances

1

1 2

1 21 3 2 1

1 2

0.5

( )S D C C S

C

C C

C CR R R R T

C C

(4)

whereRC1andRC2are the equivalent serial resistances (ESR)of C1and C2, whileRS1andRD3is the conduction resistancesof S1and anti paralleled diode of S3.

IV. SIMULATION AND EXPERIMENTAL VERIFICATIONThe proposed strategy is verified with the Saber

simulation. The switching frequency is 20 kHz, the ESRs ofC1and C2and the conduction resistances of all power devicesare set as 0.05. The forward voltage of all power devicesare 0.7V. The DC input voltage is 400V, the root meansquare (RMS) value of the grid voltage is 220V, and theoutput power is 250W.

The simulated waveforms of the output current and thecurrent stress on S3under different values of C1/(C1+C2) aregiven in Fig 5. It can be seen that iS3 is smaller whenC1/(C1+C2)=0.33. This result verifies the optimizationprinciples proposed in (4).

igrid0.5A/div

iS3

2A/div

10ms/div

(a) C1/(C1+C2) =0.33 (C1 = 470F, C2 = 940F)

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10ms/div

igrid0.5A/div

iS3

2A/div

(b) C1/(C1+C2) =0.67 (C1 = 940F, C2 = 470F)

Fig 5.Simulated waveforms of output current and current stress on S3

with different ratio of C1/(C1+C2).

Also, a 250W experimental prototype is built to furtherverify the functionality of the proposed circuit. In theprototype, the LCL output filter is used to decrease the outputcurrent ripples. The detailed parameters and components usedare as following:

Input Voltage (Vbus): 400VGrid Voltage (Vgrid): 220V(RMS)Output Power (Pout): 250WGrid Frequency (fgrid): 50HzSwitch Frequency (fs): 20kHzParasitic Capacitance (CPV): 75nFPower Switches (S1~S5): IKP15N60TLCL Filter Parameters: 15mH, 0.34F, 1mHSwitched Capacitors: C1=470F, C2=940F

The experimental waveform of the inverts output currentinto the grid is displayed in Fig 6. The total harmonicdistortion (THD) is 2.97%, and the power factor is 0.999. Themeasured output power is 246.3W.

The current and voltage stress on S3 is shown in Fig 7.The spiky current during turning off is caused by the reverserecovery of the anti paralleled diode of S3.

The effects of different circuit parameters on themaximum current stress on the power devices aredemonstrated in Fig 8. The current stress on S3 underdifferent ratio of C1/(C1+C2) is compared in Fig 8(a) and (b).In (a), C1/(C1+C2)=0.33, while in (b), C1/(C1+C2)=0.67. Allother parameters are the same, including the output powerand the input voltage. The result shows that the current stressis smaller when C1/(C1+C2)=0.33, verifying the theoreticalanalysis above. The current stress on S3 under differentvalues of Vbus is compared in Fig 8 (a) and (c). In (a),

Vbus=400V and the output power is 250W, while in (c)Vbus=380V and the output power is only 235W. It can be seenthat the current stress shown in (c) is larger although theoutput power is smaller. This demonstrates the sensitivity ofiSmaxto Vbus/Vgrid.

vgrid100V/div

igrid1A/div

10ms/div

Fig 6.Experimental waveforms of igridand vgrid.

vS3

200V/div

iS3

1A/div

50 /divs

Fig 7.Current and voltage stress on S3.

iS3

2A/div

4ms/div

(a) C1/(C1+C2)=0.33 (C1 = 470F, C2 = 940F), Vbus= 400V

iS3

2A/div

4ms/div

(b) C1/(C1+C2) =0.67 (C1 = 940F, C2 = 470F), Vbus= 400V

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iS3

2A/div

4ms/div

(c) C1/(C1+C2) =0.33 (C1 = 470F, C2 = 940F), Vbus= 380V

Fig 8.Current stress on S3under different conditions.

V. CONCLUSIONSA novel transformerless inverter topology with the

switched capacitors is proposed for the grid connected PVpower generation system. Only five power switches arerequired in the proposed PV inverter topology. The common

mode current is eliminated perfectly. The DC input voltagerequired is the same as the full bridge inverter.

A modified unipolar SPWM strategy is proposed for thetopology, enabling it to output three voltage levels. It is alsoguaranteed that C2 is charged every switching cycle underthis SPWM strategy, so that the current pulse on the powerdevices caused by the switched capacitors is reduced.Furthermore, based on the quantitative analysis of thedevices current stress, the principles for optimizing thecapacitances of the switched capacitors C1and C2are given.The simulation and experimental results are provided toverify the theoretical analysis.

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