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Handbook of RF and Microwave Power Amplifiers

Whether youareanRF transistordesigner,anamplifier designer,orasystemdesigner,

this isyour one-stopguidetoRF andmicrowavetransistor power amplifiers. A teamofexpertauthorsbringsyouup-to-speedonevery topic, including:

devices(Si LDMOSandVDMOS, GaAs FETs, GaN HEMTs); circuitandamplifier design(discrete, hybrid andmonolithic); CAD; thermal design; reliability; systemapplications/requirementsforRF andmicrowavetransistoramplifiers; amplifiermeasurements.

Covering state-of-the-art developments, and emphasizing practical communicationsapplications, this isyour completeprofessional referenceonthesubject.

John Walkeris currently European Sales Manager at Integra Technologies, Inc. Hereceived his Ph.D. from the University of Leeds in 1976 and has since held variousindustry positions, including MicrowaveHybrids Manager at Thorn-EMI ElectronicsandRF DivisionManager atSemelab. Heis theEditorandCoauthorof thebooksHighPower GaAs FET Amplifiersand Classic Works in RF Engineering. Heis aFellow oftheIEE.

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TheCambridgeRF andMicrowaveEngineeringSeries

SeriesEditor

SteveC. Cripps, DistinguishedResearchProfessor, Cardiff University

Peter Aaen, JaimePlaandJohnWood, Modeling and Characterization of RF andMicrowave Power FETs

DominiqueSchreurs, MairtnODroma, AnthonyA. Goacher, andMichael Gadringer,RF Ampli fier Behavioral Model ing

FanYangandYahyaRahmat-Samii, Electromagnetic Band Gap Structures in AntennaEngineering

EnricoRubiola, Phase Noise and Frequency Stabil i ty i n Oscil lators

Earl McCune, Practical Di gital Wir eless SignalsStepanLucyszyn. Advanced RF MEMSPatrickRoblin, Nonl inear FR Circuits and the Large-Signal Network AnalyzerMatthiasRudolph, ChristianFager, andDavidE. Root, Nonlinear Transistor Model

Parameter Extraction Techniques

Forthcoming

SorinVoinigescu,High-Frequency Integrated CircuitsDavidE. Root, JasonHorn, andJanVerspecht, X-ParametersRichardCarter, Theory and Design of Microwave Tubes

Anh-VuH. Pham, MorganJ. Chen, andKuniaAihara, LCP for M icrowave Packagesand Modules

NunoBorgesCarvalhoandDominiqueScheurs,Microwave and WirelessMeasurement Techniques

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Handbook of RF and Microwave

Power Amplifiers

Edited by

J OHN WA L K E R

Integra Technologies, Inc.

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CAMBRIDGE UNIVERSITY PRESS

Cambridge, NewYork,Melbourne, Madrid,CapeTown,Singapore, SaoPaulo,Delhi, Tokyo, MexicoCity

CambridgeUniversityPressTheEdinburghBuilding, CambridgeCB28RU,UK

PublishedintheUnitedStatesof AmericabyCambridgeUniversityPress, NewYork

www.cambridge.orgInformationonthis title:www.cambridge.org/9780521760102

C CambridgeUniversityPress2012

Thispublicationis incopyright. Subject tostatutoryexceptionandtotheprovisionsof relevantcollectivelicensingagreements,noreproductionof anypartmay takeplacewithoutthewritten

permissionof CambridgeUniversityPress.

Firstpublished2012

Printedin theUnitedKingdomattheUniversityPress, Cambridge

A catalog record for this publi cation is avail able from the Bri tish Library

ISBN 978-0-521-76010-2Hardback

Thetechnical descriptionsandproceduresinthisbook havebeendevelopedwiththegreatestof care; however, theyareprovidedasis, withoutwarrantyof anykind. The

author andpublisher of thebookmakenowarranties, expressedor implied, that theequations,programs,andproceduresinthis book arefreeof error, orareconsistentwithanyparticularstandardof merchantability, orwill meetyourrequirementsforanyparticularapplication.Theyshouldnotberelieduponfor solvingaproblemwhoseincorrectsolutioncould result in injurytoapersonorlossof property.

CambridgeUniversityPresshasnoresponsibilityfor thepersistenceoraccuracyof URLsfor external orthird-partyinternetwebsitesreferredtointhispublication,anddoesnotguaranteethatanycontentonsuchwebsitesis,orwill remain,accurateorappropriate.

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Contents

List of contributors pagexivPreface xv

1 Silicon LDMOS and VDMOS transistors: physics, design, and technology 1Wayne Burger and Christopher P. Dragon

1.1 Technology overview 11.1.1 Introduction/history 1

1.2 LDMOS andVDMOS construction 21.2.1 LDMOS 21.2.2 VDMOS 8

1.3 Devicephysics 10

1.3.1 Current transport 101.3.2 Behavior of parasiticelements/models 121.3.3 BVDSS, RDSon, HCI boundaries 171.3.4 Snapback/ruggedness 221.3.5 Operatingvoltageconsiderations 26

1.4 Design/layout 271.4.1 Top-downfinger layout 271.4.2 Bondpadmanifolds 291.4.3 Metal design electromigration 301.4.4 Thermal 32

1.4.5 Operatingvoltageconsiderations 341.4.6 Frequency considerations: gatelength, gatewidth, resistors 361.4.7 HVICs 37References 39

2 GaAs FETs physics, design, and models 42Rob Davis

2.1 Introduction 422.1.1 Propertiesof GaAsandrelatedcompounds 43

2.1.2 TheSchottky barrier gateandtheMESFET 452.1.3 ThePf2 limit 452.1.4 Typesof GaAsFET 46

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vi Contents

2.2 Power devicephysics 512.2.1 ThedeviceIVcharacteristicandloadline 512.2.2 Thedynamic IVcharacteristic 53

2.2.3 Theconsequencesof trappingeffects 542.2.4 Devicebreakdown 572.2.5 Breakdownmechanismsandoptimisation 582.2.6 CommentsonGaAsFET breakdownratings 592.2.7 TheFET equivalentcircuit 602.2.8 Devicegain and figures of merit 61

2.3 Devicedesign 632.3.1 Power devicedesign 632.3.2 FET channel andrecess design 63

2.3.3 Power cell design 672.3.4 Power cell combination 712.3.5 Thermal design 72

2.4 Devicefabrication 742.4.1 Overview 742.4.2 Key processsteps 752.4.3 Low-costGaAsdevice fabrication 812.4.4 Packaging 81

2.5 Models 842.5.1 Devicemodels 84

2.5.2 Small-signal models 842.5.3 Largesignal models 852.5.4 Load-pull 89

2.6 Concludingremarks 90References 91

3 Wide band gap transistors SiC and GaN physics, design

and models 103Robert J. Trew

3.1 Introduction 1033.2 Background 105

3.2.1 SiC transistors 1063.2.2 AlGaN/GaN transistors 108

3.3 Material parameters 1113.4 Transistor amplifier operatingprinciples 1153.5 DevicedesignandRF performance 118

3.5.1 4H-SiC MESFET amplifier 1203.5.2 AlGaN/GaN HFET amplifier 123

3.6 TransistorDC andlarge-signal RF models 1253.6.1 Equivalentcircuittransistor models 1253.6.2 Physics-basedlarge-signal transistor models 128

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Contents vii

3.7 Large-signal effects 1303.7.1 Spacechargelimitedcurrent transport 1303.7.2 Nonlinear sourceanddrainresistance 133

3.7.3 Gateleakage 1443.7.4 Reliabilityandtime-dependentperformancedegradation 146

3.8 Summary 152References 153

4 Amplifier classes, AS 159Steve C. Cripps

4.1 Introduction 1594.2 Activedevicemodels 161

4.3 ClassA 1624.4 ClassAB andClassB 1644.5 ClassC 1714.6 ClassF 1734.7 ClassJ 1764.8 Invertedmodes, invertedClassF 1794.9 ClassE 1814.10 ClassS 1834.11 Multimodes 184

4.12 Conclusions 186References 186

5 Computer-aided design of power amplifiers 188Stephen Maas

5.1 Introduction 1885.2 Methodsof analysis 188

5.2.1 Linear analysis 1885.2.2 Harmonic-balanceanalysis 193

5.2.3 Time-domainanalysis 2025.2.4 Applicationsof analytical methods 2055.3 Passivecircuitstructuresandsimulationaccuracy 205

5.3.1 Scattering parameter models 2065.3.2 Closed-formmodels 2085.3.3 ModelsfromEM simulation 2105.3.4 Databasemodels 2125.3.5 Parasiticextraction 212

5.4 Solid-statedevicemodels 2135.4.1 Power devicemodels 213

5.4.2 Modelingcell interconnections inlargedevices 2135.4.3 Thermal effects indevicemodels 214

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viii Contents

5.5 Special aspectsof power-amplifier modeling 2165.5.1 Lossincircuit metalizations 2175.5.2 Lossincircuitcomponents 219

5.5.3 Bondwires 2195.6 Practical aspectsof nonlinear circuitsimulation 221

5.6.1 Convergencedifficulties 2215.6.2 SPICE modelsinharmonic-balanceanalysis 2265.6.3 Problemsizeminimizationandsolutionoptimization 2265.6.4 Numerical considerations 2275.6.5 Designflow 228References 230

6 Practical HF/VHF/UHF RF power amplifier realization 232Daniel P. Myer

6.1 Introduction 2326.2 RF power amplifier markets 2326.3 Therealizationprocess 233

6.3.1 RFPA qualitativespecificationdelineation 2346.3.2 RFPA specifications, generic listandquantificationguidelines 2366.3.3 Specification/hardwarerealization 241

6.4 RFPA systemlevel designoverview 242

6.4.1 RF power amplifier moduledesignoverview 2436.4.2 RF power transistor deviceselectionprocessguidelines 2466.4.3 RF power transistor bias/thermal trackingnetworks 2496.4.4 RF input/outputcoupling/decouplingnetworks 2506.4.5 Power transistor impedancematching 2506.4.6 Feedback networks 2516.4.7 Thermal management 251

6.5 Hypothetical amplifierdesignexample 2526.5.1 Hypothetical applicationexampleoverview 2526.5.2 Amplifier qualitativespecificationdelineation 252

6.5.3 Amplifier specificationquantification 2536.5.4 Amplifier hardwaredesign/realization 2546.6.5 RF transistor selection 2556.5.6 Gatebias/temperaturetracking/compensationnetwork 2576.5.7 Input/outputRF/DC coupling/decouplingnetworks 2596.5.8 Input/output impedancematchingnetworks 2596.5.9 Feedback network 2676.5.10 Testsetupconfiguration/analysis 2686.5.11 Physical RFPA moduleconstruction 271

6.5.12 RFPA moduletest results 2736.5.13 Beyondthetestdata 281References 283

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Contents ix

7 Microwave hybrid amplifier realization 284Dominic FitzPatrick

7.1 Introduction 2847.2 Printedcircuitboards 2857.3 Housing 293

7.3.1 Materials 2947.3.2 Sealingandhermeticity 2947.3.3 Construction 2997.3.4 Thermal issuesandheatsinking 3057.3.5 RF connections 311

7.4 Components 3157.4.1 Passive lumped components 315

7.4.2 Passive distributedcomponents 3237.4.3 Transistors 331

7.5 Amplifier design 3337.5.1 Topologies 3337.5.2 Matchingandstability 3367.5.3 Internally matcheddeviceamplifiers 3437.5.4 Combining 3447.5.5 Modulesize/systemintegration 344

7.6 Biasingandcontrol 345

7.6.1 Control andinterfacing 3527.7 Tuningtechniques 353References 355

8 Monolithic power amplifiers 357Inder J. Bahl

8.1 Overview of MMIC power amplifiers 3578.1.1 Brief history of MMICpower amplifiers 3578.1.2 Advantagesof monolithicpower amplifiers 358

8.2 Monolithic IC technology 3598.2.1 MMIC fabrication 3608.2.2 MMIC substrates 3618.2.3 MMIC activedevices 3618.2.4 MMIC matchingelements 362

8.3 MMIC designmethodology 3708.3.1 CAD tools 3708.3.2 Designprocedure 3718.3.3 EM simulators 372

8.4 MMIC PA summary andexamples 372

8.4.1 Narrowbandpower amplifier 3748.4.2 Broadbandpower amplifiers 3768.4.3 Ultrabroadbandpoweramplifiers 3778.4.4 High-power amplifiers 381

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x Contents

8.4.5 Millimeter-wave2.4W PA 3868.4.6 Wireless3W power amplifier 3868.4.7 High-voltagemonolithic PAs 387

8.5 Packagingof MMIC PAs 3898.5.1 Ceramicpackages 3908.5.2 Plasticpackages 3948.5.3 Packageassembly 396

8.6 MMIC poweramplifiercharacterization 401References 406

9 RF power amplifier thermal design 411Mali Mahalingam

9.1 Whythermal designdeservescareful attention? 4119.2 RFPA thermal design basics 413

9.2.1 RFPA thermal designinatypical portableproduct 4139.2.2 RFPA thermal designinatypical radiobasestation 4169.2.3 Basicheattransferprocessesandtheir roleinanRFPA thermal

performance 4199.3 Thermo-physical propertiesof materialsinanRFPA 4239.4 Tools tocharacterizeandpredictthethermal performanceof RFPAs 4279.5 RFPA thermal designandmanagement advanced 432

9.6 RFPA thermal design trendsandprognostication 440References 442

10 Reliability 446Bill Roesch

10.1 Introduction 44610.2 Vocabularyanddefinitions(units, goals, andstrategy) 447

10.2.1 Reliability goals 44810.2.2 Semiconductor reliability strategy 448

10.3 Failurecriteria 44910.4 Failuremodes 45010.5 Failuremechanisms 451

10.5.1 Metalization 45110.5.2 Dielectric 45310.5.3 Bulk substratematerial 45410.5.4 SchottkygateFET failurecauses 454

10.6 Failuredistributions 45510.7 Accelerationfactors 458

10.7.1 Thermal acceleration 458

10.7.2 Currentacceleration 46210.7.3 Voltageacceleration factors 46510.7.4 RF biasacceleration 472

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Contents xi

10.8 Reliabilitypredictions(MTBF, MTTF, FITs, etc.) 47310.9 Wear-outversusdefects(accelerationversusreal life) 475

10.9.1 Thermal excursionexampleno. 1. Interconnectvias 475

10.9.2 Thermal excursionexampleno. 2. Copper bump 47810.9.3 DefectamplificationandKfactors 48210.9.4 Environmental example humidity activation

energy 48810.10 Processeffectsandinfluence 49210.11 Designfor reliability 49510.12 Historical trendsandtechnologycomparisons 50110.13 Summary 502

References 505

11 Power amplifier applications 508Mustafa Akkul and Wolfgang Bosch

11.1 Introduction 50811.2 Systemdesignparameter tradeoffs 509

11.2.1 Outputpowerefficiency tradeoff 50911.2.2 Linearity, modulationscheme, andcrest factor 512

11.3 Systemlevel linearizationtechniques 51411.3.1 Introductionto linearizationtechniques 514

11.3.2 Digital basebandpredistortion 51411.3.3 Memoryeffect compensation 51711.3.4 Impactonpower efficiency 517

11.4 Wirelesscommunicationpower amplifiers 51911.4.1 Mobileradiocommunicationtoday 51911.4.2 Systemlevel andpower amplifier requirements 52211.4.3 Poweramplifierdesignoutline 52311.4.4 Dohertyamplifier for efficientbasestations 527

11.5 Militarypower amplifiers 53011.5.1 Radar Tx/Rx modules 530

11.5.2 EW applications 53411.5.3 Anti-IED applications 538

11.6 In-phasepowercombiningtechniques 53811.6.1 Wilkinson power combiners 53811.6.2 Gysel combiner 542

11.7 Quadrature-phasepower combining balancedamplifiers 54411.7.1 Branch-linequadraturehybrid[19] 54711.7.2 Langecoupler 549

11.8 Anti-phasepower combining pushpull amplifiers 552

11.8.1 Coupledcoil transformers 55311.8.2 Transmissionlinetransformers 55411.8.3 RF/microwavepushpull amplifier 557

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xii Contents

11.9 Doherty combining 55911.10 Conclusions 567

References 568

12 Amplifier measurements 570Michael G. Hiebel

12.1 Introduction 57012.2 Power measurements 570

12.2.1 Typical powersensorprinciples 57012.2.2 Typical sourcesof measurementuncertainties 57412.2.3 High-power RF measurementsanddirectional power 57612.2.4 Power measurementsusingaspectrumanalyzer 579

12.3 S-parameter measurements 58012.3.1 TheconceptofS-parameters 58012.3.2 Scalar network analyzersandtheir limitations 58212.3.3 Vector network analyzers 58612.3.4 Introductiontosystemerror correction 58812.3.5 Calibrationwithdifferentconnector types 58912.3.6 CalibrationwithPCBs, testfixtures, andwafer probers 59312.3.7 Calibrationconsiderationfor high-power setups 59612.3.8 Residual errorsandmeasurementuncertainties 598

12.4 Further linear measurements 59912.4.1 Amplifier gaindefinitions 59912.4.2 Efficiency factor 60212.4.3 Linear distortion, phaseandgroupdelay measurement 60312.4.4 Linearstabilityconsiderations 60512.4.5 Mixed-modeS-parameters 608

12.5 Nonlinear measurements 61112.5.1 Inter modulationdistortion(IMD) andharmonic

distortion(HMD) 61112.5.2 Compressionpoint 615

12.5.3 Large-signal networkanalysis 61612.5.4 Load- andsource-pull measurements 61912.5.5 Hot S-parameters 622

12.6 Modulatedmeasurements 62312.6.1 Crest factor andCCDF 62412.6.2 Adjacentchannel power ratio(ACPR) 62512.6.3 Noisepower ratio(NPR) 63012.6.4 Errorvectormagnitude(EVM) andconstellation

diagram 630

12.6.5 AM/AM andAM/PM measurements 63212.6.6 Memoryeffects 632

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Contents xiii

12.6.7 Pulsedmeasurements 63312.6.8 Biterror ratio(BER)andsymbol error ratio(SER) 635

12.7 Noisemeasurements 636

12.7.1 Amplifier noisefactor andnoisefigure 63712.7.2 Noisefiguremeasurement 63712.7.3 Noiseparameters 640

12.8 Conclusions 641References 642

About the authors 644Index 651

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Contributors

Mustafa Akkul

ASELSAN A.S.

Inder Bahl

CobhamSensorSystems

Wolfgang Bosch

Graz Universityof Technology

Wayne Burger

FreescaleSemiconductor

Steve Cripps

Cardiff University

Rob Davis

RFMD

Chris Dragon


Dominic FitzPatrick

PoweRFul Microwave

Michael Hiebel

Rohde& SchwarzGmbH & Co. KG.

Stephen Maas

AWR, Inc.

Mali Mahalingam


Daniel P. Myer

CommunicationPower Corporation(CPC)

Bill Roesch

TriQuintSemiconductor

R.J. Trew

NorthCarolinaStateUniversity

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Preface

In 1989, I was responsible for organizing a workshop at the European MicrowaveConferenceonHigh-PowerSolidStateAmplifiers.Thisworkshopprovedpopularandso

ArtechHouseaskedmetopersuadethespeakerstoturntheirmaterial intoaformsuitablefor publication, the result was the book entitled High-Power GaAs FET Amplifiersof which I was editor and acoauthor. That book is of coursenot just out of print butalso largely out of date. This book adopts the same philosophy as the previous onewithchaptersondevicetechnology, amplifier design, CAD, thermal design, reliability,measurements,andapplications butwithacompletely differentsetofauthorsandwithevery chapter completely re-writtentobringthecontentuptodate.

Thepolitical, economic and technical landscapehas changed almost beyond recog-nitionin theintervening two decades. In the1980s most RF andmicrowaveengineerswereworkinginmilitaryelectronics,defensespendingwaslargely responsibleforall the

technical advances, andtherewerenomobilephones! Comparethat with thesituationnow wherethereareprobably just as many RF and microwaveengineers working oncommercial applicationsas there are in military electronics, commercial applicationsoftendrivetechnical advances, andmost householdswill havenot just onebut severalmobilephones and it is themobile phoneindustry that has largely been responsiblefor this shift toward commercial applications. However, there is one consequence ofthis sea-changein the industrial andtechnical environmentwhichhas had aprofoundknock-on effect when it comes to writing a book such as this. Now the commercialpressuresof shortestpossibletimetomarketandminimumcost,etc. aresointensethat

anyprospectiveauthor workinginthisfieldhastobepreparedtocommitendlesshoursof theirownrather thantheiremployerstimetothetask. I wanttopubliclyacknowledgemy deep debt of gratitudetoall theauthors in this book for makingthat commitmentandhencemakingthisbookpossible.

JohnWalker

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TheHandbook isacomprehensivereferenceforRF andmicrowavepoweramplifiers.It includesboththeoryandpracticeaswell asavariety of differentapplications. OftenoverlookedsupportingtopicssuchasCAD,thermal design, andreliabilityaretreatedin

depth. John Walker has put together an outstanding teamof authors, eachof whomiswell qualified to address his topic. Finally, I liketheway it is organized with separatechapters for three types of RF-power transistors (silicon, GaAs, and GaN/SiC) andseparatechaptersforamplifiersofdifferentfrequencytypes(HF/VHF/UHF,microwave,andIC).

FritzRaab,GreenMountainRadioResearchCompany

Johnhassuccessfullybroughttogether, inonebook, thecurrentknowledgefromworldexperts actively involved with the characterisation and modellingof devices together

with thosedeveloping and designing RF and microwavepower amplifiers. Thetimelypublicationof thisbookwill serveasauseful referencesourceforengineersworkinginboththecommercial andmilitary marketsectors.

SteveNightingale, CobhamTechnical Services

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1 Silicon LDMOS and VDMOS

transistorsPhysics, design, and technology

Wayne Burger and Chris DragonFreescale Semiconductor

1.1 Technology overview

1.1.1 Introduction/history

Power amplifiersareat thecoreof nearly all high-power (i.e., >5W) RF applications.The application space includes cellular phone basestation transceiver systems, pulsedradar, ISM (industrial, scientific, medical), avionics, digital television broadcast, etc.This diverse and evolving RF power amplifier landscape dictates the strategy for thedesign, fabrication, andoptimizationof multiplegenerationsof RF power devices. TheRF powertransistormustsatisfy abroadandoftenconflictingsetof applicationrequire-ments, includingbutnotlimitedtopower, linearity, efficiency, gain, reliability, thermal

management, bandwidth, ruggedness, digital predistortion (DPD) linearizability, andcost effectiveness. The amplifier architecture has also evolved to adapt to the ever-changingsystemrequirements,most recently withthewidespreadadoptionof Dohertyamplifierstoboostback-off efficiency inlinear applications.Thesearchitectural evolu-tions createopportunities for further refinements in theRF power transistor toextractpeak performancefromthearchitecture.

The various major market segments of the RF power market tend to embrace adominantdevicetechnology thatmeetsabroadrangeof theserequirementsuntil anewtechnologyemergestoofferamorecompellingsolution.Throughthelate1970s,siliconbipolartransistorswerethepreferredRF power devicetechnology[12]. Therelativelylow frequencies and amplifier requirements of the era were compatible with siliconbipolar transistor technology, which was capable of providing a robust, cost-effectivesolution.Thebipolartransistorshadadequategainandefficiency,couldbereadilyscaledto achievethedesired power levels, and offered linearity that was consistent with themodest requirements of that era. On the other hand, power gain was relatively poor,packages with isolated flanges were expensive, thermal runaway due to thenegativetemperaturecoefficienthadtobecarefullymanaged(usuallyattheexpenseof degradedperformancebecauseof theneedtoincorporateballast resistors), andtheevolvingandincreasinglymorestringentlinearityandefficiencyrequirementswerebecomingdifficult

todesignintothetransistors.The limitations of the silicon bipolar transistor eventually created an opening for

a new generation of transistor technology that offered superior performance without

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2 Silicon LDMOS and VDMOS transistors

these limitations. The early 1980s witnessed the emergenceof double diffused MOS(DMOS) transistors that were superior to silicon bipolar transistors for many high-power RF amplifier applications[34]. A rangeof factorscontributedtothis improved

performance, starting with the improved frequency response inherent to a majoritycarrierdevicecomparedtotheminoritycarriertransportinthebipolartransistor.Second,theDMOS transistor structurelends itself tohigh breakdownvoltagedesigns withoutseriouslycompromisingfrequencyperformance,openingupthepossibilityof increasingthepowersupply voltage, loweringthepowersupply cost,andsimplifyingthedesignofeverhigherpowerdevices.AnotherkeyadvantageisthatMOSFETsarenotsusceptibletothermal runaway, duetothepositivecoefficientof thermal resistance[5]. TheabilitytodesignDMOStransistorswithhighlinearefficiencyhasalsoemergedasakeyfactorin their widespreaddeployment.Thesetopicswill beexplored ingreater detail later in

this chapter.DMOS transistor structureand fabrication technology diverged into two main sub-groups depending onthedirectionof current flow, lateral DMOS and vertical DMOStransistors(LDMOSandVDMOS,respectively) [611].Eachof thesevariantshastheirstrengthsandweaknesses,andeachhaslargelysucceededinfindingappropriatemarketsegmentswithinwhichtoflourish.Thedopingprofileinthechannel regionofbothtran-sistorsisformedthroughtheoverlapof lateral diffusionprofiles,butLDMOSmaintainsthedrainregionandcurrentflow laterally near thesurfacewhereitcanbeeasily modi-fiedandoptimized,makingitmoreattractivewherelinearefficiencyandhigh-frequencyoperationareimportant.VDMOS, ontheother hand, canachieveexcellentpower den-

sity (i.e., extremely low RDSon/area) sincethelargedraindrift regionneededtosustainhighbreakdownvoltagesextendsverticallybelowthesurface.Thissamestructuretendsto limit thescaling of the gate structure, detracting from the high-frequency perfor-mance. This makes it the logical choicefor applications that requirevery high-powerdensityatrelatively lowfrequencies. Comparisonsbetweenthesetwotechnologieswillbeexploredthroughoutthischapter.

1.2 LDMOS and VDMOS construction

1.2.1 LDMOS

Figure1.1showsapictureof apackagedhigh-power LDMOS transistor, aview of theinternal construction, andahigher magnificationimageof theLDMOS die. Figure1.2showsacross-sectionofastandardLDMOSdie.LDMOSdiearen-channelenhancementmodeMOSFETs. TheLDMOS transistor hasa long, lightly-doped n-typedrift region(hereafterreferredtoasthen-driftregion)betweenthedraincontactandthegate/channelof thedevice. TheLDMOStransistorhasthen-driftregionorientedlaterally referencedto the silicon surface, the origin of the L in LDMOS. The drain supply voltage to

firstorderdeterminesthelengthanddopinglevel inthen-drift region. LDMOSdevicesoptimizedforhandsetsmayhaveann-drift lengthof lessthan0.5m,whileanLDMOSdevicedesignedtooperateat50V inanindustrial applicationmayrequireadriftregion

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1.2 LDMOS and VDMOS construction 3

(a)

Figure 1.1a2.1GHz,170W LDMOS single-endedpart inanair cavitypackage.

(b)

500mil

Array ofbonding-wires

Gate lead

Flange

MOS capacitors

Transistors

Ceramicsubstrate

Embeddedcapacitor

Drain lead

Figure 1.1b

High-power LDMOS devicewithlidremovedillustratingtheLDMOS buildingblocks,MOSCAPs,andextensivewirebondarraysintheinputandoutputmatchingnetworks.

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(c)

Gate Lead

Drain Lead

ESD Protection

Figure 1.1cTypical layoutof a50W LDMOS buildingblockdesignedfor2GHz operation.

Gate

gate oxide

oxide

metal strap

Drain

n+drainn-drift regionn+source

p-type epitaxy

p+substrate

Source

Channel

PHV region

p+sinker

Figure 1.2LDMOS cross-sectionillustratingkey features, includingtopsidegateanddrainconnectionsandabacksidesource.

56mlong.Thevastmajorityof cellular infrastructurebasestationsaredesignedwithasupplyvoltageof2832V.Whenthetransistor isturnedon,thedriftregionsimplyactsasavoltagevariableresistorandcreatesavoltagedropsuchthatthepotential inthedrainregionbelow thegateis significantly lessthantheappliedDC bias inorder topreservethe integrity of the gateoxide and ensure that HCI (hot carrier injection) is limited.MostLDMOSdesignsalsoleverageatechniquetermedRESURF REducedSURfaceFields[12],whichreliesuponarapidtwo-dimensional expansioninthedepletionregionwidthwithincreasingdrainbiasthatkeepsthepeakelectric fieldbelowthecritical field

for impactionization, withoutcompromisingthelow drainbias RDSonof thetransistor;this techniqueenables very high breakdownvoltages whilemaintaining the low RDSonnecessary toachievehigh-power density. Unless stated otherwise, references topower

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p-type

substrate

n+source

n+drain

gate

VD = 0 V

5 V

10 V

20 V

50 V

n-region

Figure 1.3DepletionregionboundariesforVDS voltagesof 0, 5, 10, 20, and50V inanLDMOSdevice.

densityrefertoW/mmgateperiphery;withthisdefinition,high-powerdensitycorrelateswithimprovedperformancefor mostfiguresof merit. Thenatureof thereactivecircuitelementsinanRF transistorenablesthepeakdrainvoltagetoreachapproximately twicethedrain supply voltage Vddduring class AB operation, and even higher during othermodes of operation[13]. The ability to withstand these peak voltages explains whydatasheetsfor transistorsdesignedfor32V ClassAB operationtypically specify 65V

minimumfordrain-to-sourcebreakdownvoltage, BVDSS.Thelightly doped n-drift regionin theLDMOS device, alongwiththelightly doped

p-epi region,aredesignedtodepleteasthedrainvoltageincreases, inalignmentwiththeRESURF principle.Theepi depth/dopingaswell asthen-driftsdepth/doping/extensionmustbeoptimizedsuchthat thepeak electric fieldacrossthisdepletionregiondoesnotexceedcritical avalanchebreakdownlevelsduringtheapplicationsRF voltageswings.Figure 1.3illustrates through simulation how the depletion region edge progressesthroughthen-drift regionas thedrain biasvoltageis increased from1V to 65V, withthegatebiasedatatypical voltageforClassAB operation.Sincethisregionisthelargest

parasitic resistancewithin the transistor, it also determines the saturation current andhencepower density. Keeping this resistanceas low as possiblewhilemaintaining anappropriatebreakdownvoltageandHCI reliabilityisacritical partof thedesigntradeoffmadeintheLDMOS transistordesignprocess. Proprietary techniquesareemployedtoincreasethepowerdensitywithoutcompromisingBVDSSorHCI.Thesethreeparameters(BVDSS, HCI, RDSon) definetheboundary within which thetransistordrain structureisoptimized. The lightly doped p-type epitaxial layer is also important to achieve lowdrain to sourcecapacitance,Cds, which is important to achievegood high-frequencyperformance.

Thegateof theLDMOStransistor ismostcommonlycomposedof astackof polysil-

icon and asilicide(e.g., WSi, CoSi) [1415]. While aDC current will not flow in thegateof aMOSFET, displacementcurrent fromtheAC waveformwill flow throughthegatecapacitance, resultingin an undesirablevoltagedrop across thewidth of thegate

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n+drainn+source

ndrift

region1E16

1E17

1E18

1E19

1E20

1E15

p-type lateral

channel diffusion

NetDopantConc(cm3)

Figure 1.4Lateral dopingprofilealongthesurfaceof anLDMOSdevice.

finger. Thesilicidelowersthegateresistancebyatleastanorderof magnitudeover thatof highly dopedpolysilicon. Inthecaseof WSi thiscanrangefrom10/sqtolessthan

1 /sq, depending on thickness. If the gateresistance is too high, the power gain ofthedevicewill suffer. Thegatelengthandgateoxidethicknessarekey indeterminingthefrequencyresponseof thetransistor (i.e., ft, theunitycurrent gainfrequencyof thetransistor). Thinnergateoxidesandshortergatelengthsresult inahigher ft. Inaddition,athinnergateoxideresultsinahigherdevicetransconductance(gm), butnotnecessarilyhigher RF power gain. This is because the thinner gateoxidealso increases the inputcapacitanceof thedevicewhichcan lower gain. This isanother examplewheredesigntradeoffsmustbeconsidered.

Theasymmetrical p-channel regionof thedeviceisoneof thedistinguishingfeatures

that differentiates theDMOS transistor fromthestandardMOSFET. For theLDMOStransistor, this region is created by usingthegateto self-alignamoderatedosep-typeimplant(referredtoasthePHV implant) tothesourceedgeof thegateof thetransistor.A subsequentfurnaceanneal isusedtolaterally diffuse(theD inDMOS) thisimplantinto the channel. Thesource-sidestructure is completed by the self-aligned implantand subsequent diffusionof theheavily doped n-typesource/drain implant. Figure1.4presentsthesimulatedprofile fromthesourcetothedraincontactalongthesurfaceofthetransistor,illustratingthefourdistinctregionsof thedevice(n+source,PHV, n-drift,andn+drain).TheresultisaMOSFET withanonuniformchannel dopingprofile,withthe source side moreheavily doped than the drain side. One advantage of this is that

thedopant gradientgenerates itsownelectric fieldwhichprovidesasmall boost totheoverall currenttransportofthedevice[16].Moreimportantly,thisdesignallowsthelargesupply voltagesdescribedearlier tobeappliedwithoutsufferingpunch-through. Asthe

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drainvoltageis increased, thedepletionregionwill spreadaway fromthenpjunctionformedbytheintersectionof then-driftandPHV/p-epi regions. If thatdepletionregionweretoreachthesourcesideof thedevice, then+sourcetoPHV junctionbarrierwouldbelowered resulting inadramatic increasein thesupply of electrons injected intothechannel andswept tothedrainterminal by theappliedelectric field.Thisphenomenonis referred to aspunch-through, andresults in alossof control of thedrain current bythegatevoltage.Sincethedepletionregionwidthisinversely proportional tothedopingdensity, thegrowthof thedepletionregionintothePHV slowsconsiderably asitmovestowards themoreheavily doped sourcesideof thechannel in an LDMOS device(seeFigure1.3). This preservesthehigh-voltagecapabilityof thetransistor.

Thesourceof thetransistor isuniqueinanRFLDMOSdevicebecauseitgetsshortedto the body of the transistor. Thebody cannot bebiased separately from the source.

This is done so that theback of thewafer can be used as the grounded source in theapplication.Makingelectrical groundconnectiontothebackofthedieobviatestheneedforsourcewirestobepresenttomakeatop-sideconnection. By eliminatingthetopsidesourcebond wires, a large amount of sourceinductance is eliminated, increasing thegainof thetransistor. To makethisbacksidesourcepossible, then+sourceis shortedtoaheavilydopedp-typeregioncalledthep+ sinker bymetal 1(typically analuminumalloy). This metal is not contacted by a bond wire for biasing and simply acts as ameans to short the pnjunction between the two regions. The p+ sinker is implantedveryearly in theprocessandis thermally diffuseduntil it meetsthep+ substratedopingwhich is gradually diffusing upwardduringthis thermal cycle. Thep-epi must notbe

entirely consumedby thesubstrateup-diffusionbecauseof thebreakdownvoltageandcapacitanceconstraints described earlier. A balancebetween keeping a low-resistancepaththroughthep+ sinker into thep+ substrateandretainingamplelightly dopedp-epifor breakdownand low Cdsmust bestruck. Thewafer is then thinned throughaback-grindprocess(tothicknessesinthe26milsrange) andback-metal isdepositedonthewaferbacksidesothatagood, low-resistancecontactcanbemadebetweenthedieandpackage.

There are two components of the device design that are located above the siliconsurface: the field plateand the drain metallization. The field plateprovides an extra

degreeof freedomwithinthen-driftoptimizationtradeoff describedearlier. By placinga grounded conductor (i.e., the field plate) close to the surfaceof the n-drift region,the field plate can perturb the depletion region and electric fields such that a higherdoping and/or shorter extension can beused for the n-drift region for agiven amountof breakdown voltage and HCI. In other words, the parasitic drain resistance of thedevice can be lowered, the RF power density of the device can be increased, andthe HCI levels in the device can be reduced if the field plate is designed correctly.Figure 1.5 is a simulation of the subsurface electric field for a device both with andwithout a grounded field plate, fromwhich the peak electric field can be seen to bedramatically reducedfor thedevicewithafield plate. Inaddition, sincethis field plate

isgrounded, itcanactasashieldbetweenthedrainmetalsandthegateof thetransistor,reducing thefeedback capacitance Cgd. The drain metallization must be designed tomeet the applications electromigration requirements. RF power devices are typically

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n+source channel

and ndrift

with shield

4.0e+05

2.0e+05

0.0e+00

without shield

LateralE-FieldMagnitude(V/cm)

Figure 1.5Comparisonof thelateral electric fieldmagnitudewithandwithoutafieldplateshield.

designed to operateat a junction temperatureup to 200 C at relatively high currentdensities. A typical device design target mightbea100-year electromigration mediantimetofailure(MTTF) atratedpowerand200C. Thisrequiresaveryrobustmetalliza-

tion, andis typically satisfiedwithathick aluminumorgold topmetal withdimensions(thicknessandlinewidth) thatareappropriatetokeepthecurrentdensitylowenoughtomeettheMTTF goals.

1.2.2 VDMOS

TheVDMOStransistor (Figure1.6) sharesmany of thedevicedesignandoperationalconsiderations described for theLDMOS transistor. Themost significant differenceisthat the body/substrateof the VDMOS transistor is n-type rather than p-type, and it

serves as thedrain of theVDMOS transistor whereas thebody/substrateis thesourcefor theLDMOS device. The n-drift region is a lightly doped n-typeepitaxial layer ontopof aheavily doped n-typesubstrate; theVDMOS epi thickness is theequivalent ofthe n-drift extension in the LDMOS device. This region is also the primary sourceof parasitic resistanceintheVDMOS devicebut it extendsdowntowards thebacksideof thedierather than remaining at thesurface. Thisdesign allowstheepi thickness tobeadjustedtoachievethetargetbreakdownvoltage. Forvery highbreakdownvoltagesinthe200+ V regime, thisvertical designismoreappropriatethanthelateral designoftheLDMOStransistor.VDMOStransistorssuitableforRF operationatdrainbiaslevelsin excess of 100 V arenow on themarket [1718], whereas 50 V is thehighest drain

voltageoperational ratingonanLDMOS transistor availabletoday [1921]. Increasingthedrainvoltageis thelogical pathway todevelophigh-power partswithuser-friendlyimpedancelevels. Thishas led toadivergencein themarket wherethesetechnologies

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n-type epitaxy

Channel

Source metal

overlay

Gate

Source

oxide

Gate

n+ substrate

p+ diffusion

n+ source n+ source

Drain

Figure 1.6VDMOScross-section illustratingkey features. UnliketheLDMOSstructure, thegateandsourceareonthetopsidewhilethedrain is onthebacksideof thestructure. Adaptedfromreference[25].

competeagainst eachother, with LDMOS tending tohavethehighest values of gain,efficiency, andoperatingfrequency, whiletheVDMOS canachievehigher power levelsathigher drainbiasvalues, butat lower frequencies.

Whilethevertical drift regiondesignenableshigher drainvoltageratingsandpowercapability, which are significant advantages for certain applications, this drift regiondesign is not amenable to the incorporation of field plates; the performance gainsachievedbyLDMOSfor thepasthalf dozenyearswereenabledbytheincorporationoffield plates to allow for aggressivereductions in RDSonandincreases in power densitywithoutcompromisingreliabilityorbreakdownvoltage.Thevertical drift regiondesignalsoleadstothebacksideof thedevicebeingthedrainratherthansource/groundterminal(theLDMOS transistor brings thesource to thedevicebackside). Since the transistormountingflangeis mechanically and electrically connected tothePA heat sink and toground, this introduces complexity into the packaging environment for the VDMOS

devicecompared totheLDMOS transistor. Finally, thetransitionof current flow fromlateral tovertical inducescurrentcrowdingthattendstolimitperformancecomparedtotheLDMOS purely lateral transport[22].

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0.45

0.40

0.35

0.30

0.25

IDS(A)

0.20

0.15

0.10

0.05

0.00

0 10 20 30 40

7.0 V

6.0 V

5.4 V

5.0 V

4.4 V

4.0 V

3.4 V

3.0 V

VGS = 2.0 V 0 V

VDS (V)

50 60 70 80

Figure 1.7 IDS-VDS family of curvesforvariousVGSvalues.

1.3 Device physics

1.3.1 Current transport

DMOS devices behave largely the same as standard three-terminal n-channel MOSdevices with regard to transistor operation. Thecurrent-voltageresponsecan bechar-acterizedashavingcutoff, linear, andsaturation regimesof operation (seeFigure1.7).Currentequationsforthelinearandsaturationregionsofoperationcanbeapproximatedby equations (1.1) and (1.2), respectively [23], where IDis thedrain current, Sis theelectronsurfacemobility, Coxis thegateoxidecapacitanceper unit area, Wis thetotal

gatewidth,Lis theeffective gatelength, and VG,VT, and VDare thegate, threshold,anddrainvoltage, respectively. Duetothegradeddopingprofile within thechannel ofthedevice, thereis an additional electric-field induced drift current component whichis not present in standard MOSFETs, providing an additional boost to the apparentmobilityand gm. Notethat for small drain voltages, theVD2 termcan bedropped fromequation(1.1),whichthenreducestothefamiliar linear relationshipbetween IDandVD.

ID= sCoxWL

(VG VT)VD1

2V2D

(1.1)

ID= sCoxW2L (VG VT)2 (1.2)

It isworthnotingthatDMOSdevicesascommonly designedforRF operationcannotbeused as four terminal devices (i.e., gate, drain, source, and body). In both LDMOS

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1.3 Device physics 11

Gate Drain

Source

Figure 1.8Illustrationof thecurrentflowin theLDMOS structure. Thecurrentflow is lateralacrossthedrain andchannel, andisthenshuntedtothesourceconnectionatthebacksideof thewafer.

andVDMOSdevices, thebodyof thedeviceisusedasthesourceordrain, respectively.In both cases this eliminates the need for a top-side contact for all three terminalsof the device (i.e., gate, source, drain). In the case of LDMOS, only the gate anddrain havetop-sidecontacts allowing for the sourceto remain a low-resistance, low-inductanceconnection(i.e.,wirebondsarereplacedbydiffusionsthatelectricallyconnectthe source to the backside of the wafer, which is then connected to systemground see Figure 1.2) which is important for RF applications. VDMOS has only gate andsourcetop-sidecontacts,whichhaslayoutdensificationadvantages,especially for very

highvoltageoperation, aswill bediscussedinalater section. Thedrain of theVDMOStransistorisinternallyshortedtothesubstratewhich,aspreviouslydescribed,requiresanaccommodationduringpackagingsincethewafer backsidecannotbemounteddirectlytothepackageflangeandheatsink.

The current paths for the LDMOS and VDMOS transistors are illustrated inFigures 1.8and1.9,respectively, but remember that current flow is the opposite ofelectronflow.TheLDMOSdeviceshowscurrentbeginningatthedrainwhereapositivevoltage has been applied and flowing through the lightly doped n-drift region beforecrossing the channel. The current then passes through then+ source into the metalwhichshortsthen+ sourcetothep+ sinker,andthenintothep+ sinker. Thecurrentthen

moves vertically through the silicon and out the backside of the substrateto ground.TheVDMOS devicehas acurrent path which begins at theback of wafer and movesvertically tothesurface, transitioningthroughthelightly dopeddrift regionformedbytheepitaxial layer.Itthencrossesthechannel andexitsoutof thesourcecontactterminal.

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Gate

Gate

Drain

Source

p+diffusion

Source metal

overlay

oxide

Figure 1.9Illustrationof thecurrentflow in theVDMOS structure. Thecurrentflow isverticalthroughthedrainregion, turninglateral acrossthechannel andintothesource.

1.3.2 Behavior of parasitic elements/models

In RF power applications, theoperational effectiveness(e.g., gain, power density, effi-ciency,etc.)ofatransistorismostly limitedbyitsparasitic elements. It is inminimizingtheseelementsthatthetruechallengeof devicedesignbecomesapparent. Capacitancesandresistancesposethebiggestproblems. Resistancesareaproblembecausethey notonly dissipateenergy but also limit thepeak current and hencepeak power capability,andcontributetoanincreaseinthekneevoltageandhencedegradethepeakefficiencyofthetransistor. Parasitic resistances, althoughanecessary by-productof certain regionsof the device (i.e., the n-drift region) to meet breakdown voltage and HCI reliabilitygoals, tend to degrade the overall performance of the transistor. Many variations ofthe basic DMOS structure havebeen reported in an attempt to reduce RDSonwithoutcompromising BVDSS. Capacitances poseseveral problems. Themost classical impactissimply todegradethefrequencyresponseof thetransistor. Equations(1.3) and(1.4)aresimplifiedequationsfor fT(unitycurrentgainfrequency)andfmax (unitypowergain

frequency), respectively [24], whereCgsistheinputcapacitance, Routis thereal partoftheoutputresistance, andRinisthereal partof theinput resistance.

fT= gm2Cgs

(1.3)

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CDS/mm(F/mm)

VDS (V)0 10 20 30

1.20E-12

1.00E-12

8.00E-13

6.00E-13

4.00E-13

2.00E-13

0.00E+00

(a)

Figure 1.10aTypical drain-sourcecapacitance(CDS) versusvoltagecurveforanLDMOS device.

(b)

6543210

CGS/mm(F/mm)

VGS (V)

1.05E-12

1.10E-12

1.15E-12

1.20E-12

1.25E-12

1.30E-12

1.35E-12

Figure 1.10bTypical drain-sourcecapacitance(CGS) versusvoltagecurveforanLDMOS device.

fmax = fT2

Rout

Rin(1.4)

The other impact is that many transistor capacitances are nonlinear functions of thejunction voltage and therefore can result in a distortion of the signal being passedthroughthePA. Figure1.10presentsinputcapacitanceCgs, outputcapacitanceCds, andfeedback capacitanceCgdversus voltagecurves that arerepresentativeof an LDMOS

transistor, illustratingthesensitivity of thecapacitances to terminal voltage. Thevari-ation of these capacitances degrades the efficiency of the input and output matchingnetworks since the fixed value passives in these networks must bedesigned to oper-ateinanenvironment wherethecapacitancesbeingmatcheddependonvoltage. What

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(c)

CDG/mm(F/mm)

VDG (V)0

5.00E-14

4.00E-14

3.00E-14

2.00E-14

1.00E-14

0.00E+00

5 10 15 20 25 30 35

Figure 1.10cTypical drain-sourcecapacitance(CGD) versusvoltagecurveforanLDMOS device.

p+substrate

RS

CGS

RG

CGD RD CDS

p-epi

Gate Drain

Source

p+

n+ n+n

p

Figure 1.11Key parasiticcapacitancesandresistancessuperimposedontheLDMOS structure.ThegateresistanceRGis actuallyperpendicular totheplaneof thedrawnstructure(i.e., intothepage).

follows is amoredetaileddiscussion on eachof thekey parasitic elementsof DMOS

transistors.Figure1.11 showsthevarious parasitic resistances and capacitances in an LDMOS

transistor. Thedrainresistance(Rd) is largely dominatedby then-drift regionandmustbedesignedtosustainappropriatelevelsof breakdownvoltagewhileminimizingHCI.

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good sinker linkage

poor sinker linkage

1E16

1E17

1E18

1E19

DopantConc(cm3)

1E20

Figure 1.12Comparisonof thevertical dopingprofilesthroughthesinker regionof anLDMOSdevicewithandwithoutgoodlinkagetothesubstrate.

This isdiscussedinmoredetail inthenextsection. Thegateresistance(Rg) iskept lowthrough theuseof asilicidewhichsitsatopthepolysilicongate. Thesilicideprovides

at least anorder of magnitudereductioningateresistanceover just polysilicon. Giventhe high-power capability of thesedevices, total gatewidths tend to be measured inmillimeters rather than microns. How this is achieved from a layout perspective isshown in a later section. The important aspect to consider is that the RF signal istravelingdownlongstretchesof gateandthereforeitmustalso beconsideredtoactasatransmission line. IfRggets toohigh, avoltagedropoccursalongthegatewidthandthegainof thedevicebecomespoor. Finally, Rsisdrivenprimarilybythesinker region,thelink to thep+ substrate, thep+ substrateresistance, andvarious smaller resistancesassociated with thedieattachand metal packageflange. If onewereto takeavertical

look at thedopantprofileseenthroughthesinker to thesubstrateit would look likethesolid linein Figure1.12. A failureto formalow-resistancelink between thep+ sinkerandthesubstrateis illustratedby thedashedlineinFigure1.12, whichwill degradetheRF performanceof thetransistor.

The capacitances in the LDMOS device typically have both fixed and nonlinearcomponents. Beginning with the drain-to-source capacitance Cds, a typical CdsCVcurveisplottedinFigure1.10a.Thenonlinearnatureof thecurveisduetothenonlinearspreadingofthedepletionregionintoboththebodyandn-driftregionasthedrainvoltageis increased(seeFigure1.3). It is affectedby thedopant levels in thedeviceaswell astheshielddesignswhichcanperturbthen-driftdepletionsif placedclosetothesurface.

Inaddition,therearefixed,voltage-invariantintermetal fringingcapacitanceswithinthedevicethatshift theentireCVcurveup. Thenonlinear natureofCdscanbeaproblemsincevoltageswingswill createarangeof capacitances for eachRF cycle. This leadstodistortionand can also becomeproblematic for specific types of PA design suchas

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envelopetrackingthatvary thedrainvoltagedynamically toadjustoutputpower levels.Another challengefromnonlinear capacitances is theimpactof thenonlinearity onthematchingnetworkdesign;sincethematchingnetworkcomponentsarevoltageinvariant

(inductorsandMOS capacitors, typically), theinstantaneousimpedancetransformationwill vary across the RF cycle as the device intrinsic capacitance varies, resulting incompromised performanceover most of theRF cycle. And finally,Cdsdetermines, tofirst order, the intrinsic output impedance of the transistor; for silicon transistors inparticular, thisjunctioncapacitancecanleadtovery lowimpedancesthataredifficult todesignbroadbandmatchingnetworks for.

Thegate-to-sourcecapacitanceCgsinthedeviceishighlydominatedbythegateoxideof thetransistor. Duetothenatureof all MOSFETstheCgsCVishighly nonlinearandshowninFigure1.10(b).Priortothedevicereachingthresholdthereisnoinversionlayer

tospanthechannel directly below theoxide. Thereforeadepletionregioniscreatedtouncoverchargetobalancetheappliedgatevoltage.Oncethedevicegoesintoinversion,thereisanamplesupply ofelectronsdirectlybeneaththeoxidesurfaceonwhichE-fieldlinescanterminate. Thecapacitancebecomesmuchlarger sinceitnowconsistsof onlythegateoxiderather thanthegateoxideinserieswithadepletioncapacitance; theon-stateCgsforanLDMOSdeviceistypically twotofourtimeslarger thanCdsmeasuredat28V whereasforaVDMOS devicetheratio is closer tounity. Thisnonlinear behaviorof theinputcapacitancewithvoltagealsocreatesproblemswithlinearity intheformofphasedelaysfromtheinputtotheoutputof thedevice.

Thegate-to-drain feedback capacitance(Cgd) hasthesameCVshapeasCdsbutthe

magnitude in a typical LDMOS device is much lower Cdgat 28 V is typically lessthan5%ofCdsat28V. Thenonlinear contributionstemssolely fromwherethen-driftregionisoverlappedby thegateandis thereforemanipulatedby then-driftdoping, theextentof thelateral diffusionofthePHV inthechannel, thegateoxide,andthevariationin depletion region locations withbias. Therearealso significant contributions to Cdgfromintermetal fringing.Variousshielddesignshavebeenusedtoconceal thegatefromthedrainmetal andhencereducethefeedbackcapacitance. Theshield isgroundedandtherefore terminates E-field lines originating with the drain. Excessive Cgdcan lowerpower gaininthedeviceandincreasetheinstability.

ThedescriptionsappliedtotheparasiticresistancesandcapacitancesforLDMOSalsoapply totheVDMOSstructure. Inexchangefor then-drift regionbecomingvertical andtherebyincreasingtheflexibilitytodesignforbreakdownvoltagesof100V orhigher,theparasitic capacitancesof theVDMOSstructuretendtobehigher thanfor theequivalentpower RF-LDMOS device. In addition, compared to LDMOS the VDMOS structurelendsitself towardsloweroperational frequencies(i.e., lowergainatagivenfrequency).The lack of agrounded shield structure in theVDMOS device (seeFigure1.6)tendstoincreaseCgd, inadditiontonotprovidingtheadditional devicedesignflexibilitythata grounded shield layer provides (i.e., the grounded shield has enabled highern-driftdopingconcentrationstoincreasepower densitywithoutsacrificingHCI performance).

Therearefew benignparasitic elementswhenconsideringtheperformanceof high-power RF transistors. A robust design process based upon models that include theseparasitic elementsis critical toenableoptimizationof thedesign across abroad range

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of performancemetrics. An excellent reference for thecharacterization andmodelingof RF power devicesis [25].

1.3.3 BVDSS, RDSon, HCI boundaries

Breakdown voltage (BVDSS), linear regime on-resistance (RDSon), and HCI are threecritical parameters that are traded off against one another in thepursuit of higher RFperformance. Manyaspectsof thetransistordesignareconstrainedbytheseparametersandfor themostpartarecontrolledby thedrain regionof thedevice. Manipulatingthedrainof thedeviceinvariousways(i.e., n-driftdoping, n-drift length, shieldplacement,and design) is collectively referred to as drain engineering. This section is devoted tothistopic.

Breakdownvoltagebetweenthedrainandsourceof aMOSFET whilethetransistorchannel isOFF (i.e.,gatevoltageiszeroforstandardLDMOSandVDMOSdevices) isreferredtoasBVDSS.Foratypical wirelessbasestationapplicationwiththePA operatingin Class AB bias, the drain DC supply voltage will bein the 2632V range, but thepeak RF voltage which occurs on top of the DC bias will essentially be double thisvalue.Thiswouldimply aminimumBVDSSrequirementof 64V.Forthisreasonthedatasheetstypically specify 65 V minimumBVDSSfor cellular infrastructureapplications.This isachievedwith thelightly doped n-drift regionthat is designed to operatein theRESURF regime. Discussion of the breakdown mechanismis required to understandhowthisworks.

The drain-source breakdown in an LDMOS or VDMOS device occurs when theelectric field across the n-drain/p-source junction (the junction which is vulnerable inthese devices is actually between the drain and the body of the MOSFET, but recallthat thesourceandbody areshorted so thedrain-sourcevernacular remainsaccurate)exceeds the critical level required for a phenomenon known as avalanchebreakdownto initiate. With any p/njunction that is reversebiased (as is thecasewhen apositivevoltageis appliedto then-typedrain whilethep-typesourceisgrounded), adepletionregion extends into each side of the junction creating a balanceof charge. Thereareno free-flowingelectrons in then-typedepletion regionor free-flowingholes in thep-

typedepletionregion, hencetheyaredepletedof mobilecarriers. Withoutthesemobilecarriers, thedopantatomswithinthesiliconlatticepresentafixedcharge(i.e., positivechargein then-typedepletionregionand negativechargein thep-typeregion). Thesefixed charges set upanelectric field across thedepletionregions. Theintegratedfixedchargeinthedepletionregionsoneithersideof thejunctionisalwaysequal. If thedrain-source voltage is increased, the depletion regions grow uncovering additional fixedchargewhich in-turnresults inalarger electric field. How largethedepletionregion isdependsonthelevel ofdopantinthatregion. If theregionishighly doped, thedepletionregionisquitesmall sinceavery small depletedareauncoversalargeamount of fixedcharge(recall thatthefixedchargecomesfromthedopantinthelattice). If theregionis

lightly doped theoppositeis true: thedepletionregionmust extendalargedistancetoexposethenecessary fixedcharge. Thisconcept is important inthat for agivenappliedvoltage, thepeak value of theelectric field that extends over a long distanceis lower

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thanonewhichoccursoveraverynarrowregion. It is thepeakvalueof theelectricfieldwhichincitesavalanche[26].

Within the depletion region electron-hole pairs areconstantly being generated that

areswept fromthedepletionregionsbytheelectricfieldcreatedby theappliedvoltage,resultingintheleakagecurrentinthedevice.Asthevoltageacrossthejunctionincreases,thepeak electric fieldwill eventually reachavaluewherethespontaneously generatedelectron-holepairsgainsufficient energy fromthefield tobreak electronbondsduringcollisions with the latticeatoms, leading to thegenerationof new electron-holepairs.Thisnewlyformedelectronholepairrepeatsthepattern; itiseasytoseehowtheprocesscan lead to an exponential increase in current for a sufficiently large applied voltage.Thisprocess istermedavalanchebreakdown. Theresultantelectrical curveisshowninFigure1.7. Inthis example it is clear thatanexponential growthincurrent is occurring

at72V.Designing for high BVDSSis most easily achieved by using a light dopant level onboth sides of the drainsource (body) junction. In both LDMOS and VDMOS cases,thebody isalready lightly doped. Thedrainhowever hasmany designelementswhichcanbeadjustedtoachievethedesiredbreakdownvoltage. Themost obviousgiventhediscussionthusfaristosimplyusealightlydopeddrain.However,if then-drainregionisshortandshallow, thenthedepletionregionwill veryquicklyconsumetheentiren-areaand hit the n+drain contact area, pinning the lateral growth of the depletion region.This means that length and depth of the n-drift region become additional parameterswhich must be carefully designed. The result is a two-dimensional depletion region

spread(RESURF) that doesnotoccur insimpleone-dimensional junctiontheory[12].Referring toFigure 1.3,the progression of depletion laterally from the channel andvertically fromthebodycausesareductioninfieldstrengthastheoverall electricfieldisnowsplitintovectorswhichareorthogonal tooneanother.A full discussionofRESURFisbeyondthescopeof thischapter but thetypical pattern in lateral electric fieldacrossthen-drift regionisseeninFigure1.6withtwoelectricfieldpeaks:onenear thechanneland onenear then+ drain contactarea. To maximizeBVDSSthen-drift doping, depth,andlengtharedesignedsothat thesepeaksarenearly equal.

Another element of drain engineering design is the use of shields or field plates

abovethen-drift region (seeFigure1.2). Theconcept behindfield plates is to providean additional degree of freedom to modify the field distributions within this criticalregion of the device. If a grounded conductive layer is placed close enough to thesurfaceof thedeviceit creates asurfacefor electric field lines to terminateupon; thisstructureiscommonly referredtoasafieldplate.Thefieldplateservesseveral purposes.Oneis toreducecapacitivecouplingbetween thedrainandgatewhichimproveshigh-frequency performance. It should benoted that early devicesplacedagroundedmetalshieldbetweenthedrainandgatetoreducecapacitance, butfarenoughfromthesiliconsurfaceto haveminimal effect on theelectric field distribution in the drain. Over thepast ten years, LDMOS device design has evolved to place the field plate closer to

the silicon surface to intentionally alter the field distribution in the drain region. Inthis regime, thecouplingbetween thedrain and thefield plateenhances theRESURFbehaviorinthedevice,allowingahigherdopantlevel tobeusedtoachieveagivenBVDSS.

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Thehigher dopant level increasesthepower density, improvingdeviceperformance. Inaddition, thedeviceengineer canplacetheshieldonly abovetheportionof then-driftregion that is needed andcanalso control how closeit is by choosingthethicknessof

thedielectric deposited below theshield, providingadditional flexibility in thedevicedesign.Itisimportanttonotethatthefieldplateintegrateseasilyintothelateral structureof theLDMOSdevice; theVDMOSstructureis inherentlyincompatiblewithfieldplatestructures.

Looking at a typical family of IDVDcurves for variousVGvalues there are twogeneral regionsof MOSFET operationasdiscussedearlier: linearandsaturation. Inthelinear regionof operation theMOSFET current versus voltage curves exhibit aslopewhose reciprocal is referred to as RDSon. Thesteeper this slope is then the larger theRF signal can swing before becoming limited by the capability of the transistor. A

lowerRDSonvaluetypically translates into higher power density andhigher efficiencyandis consideredacritical designcomponent in any LDMOS or VDMOS device. Thedesireis tokeep RDSonas lowaspossible. Thelargestcontributor toRDSonis then-driftregionwherethebreakdownvoltagediscussionaboveillustrates theneed for a lightlydoped(moreresistive)design.Thisisoneof thefundamental tradeoffs tobemadewhendesigning an RF PA transistor, and it is of little surprisethat the vast majority of thedevicedesignactivity isdevotedtodrainengineeringprecisely thisparticular tradeoff.This drove the need for shields/field plates in LDMOS and experimentation with avariety of dopingtechniquesinthen-drift area. Other contributorstoRDSonincludethesourceresistancecomponentsof theLDMOS andVDMOS devicesalready coveredas

well asthechannel resistancecontributionwhichisnegligibleif designedproperly.LDMOS devicesrelyonthelateral diffusionof ap-typeimplanttocreatethechannel

doping profile. This results in the preferred higher doping at the source end of thechannel and lower doping at thedrain end of thechannel (seeSection1.3). However,if thelateral diffusionis toogreatduetoeither athermal cyclewhich istooaggressiveor agatelength which is too short, thep-typedopant will reachthen-drift region andovercompensate.Thisresultsinthep-typedopantcounter-dopingthen-typedopantandthat areaof overcompensation becomes a p-type region. If there is non-type regionto link up to the drain edge of the gate (see Figure1.2) then the small p-type region

becomesalargeparasitic resistance, RDSonincreasesdramatically, andpower capabilityis lost in the device. This makes controlling gate lengthand lateral diffusion thermalcyclesacritical manufacturingconcernforLDMOS.TheVDMOStransistorhassimilarconsiderationsintermsof controllingthelateral diffusionof thePHV implant.

HCI in MOSFET transistors must be considered with respect to the impact it willhavein RF PA applications. HCI is thethird major consideration (theother two beingBVDSSandRDSon).ThereareavarietyofmetricsavailabletocharacterizeHCI, includingthreshold voltageshift, transconductancedegradation, etc. Thetwo critical parametersimpactedby HCI for RF power devicesareshiftsin RDSonandbiascurrent (commonlyreferred to as IDQ). For a thorough understanding of these effects a discussion of the

devicephysicsinvolvedisrequired.Two things must be present for HCI to occur: an electric field strong enough to

impart significantenergy tothecarriersmakingthemhot andthecarriersthemselves

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VDS = 0.1 V

VDS = 28 V

0 0.5 1 1.5 2 2.5 3

1.00E+00

1.00E-01

1.00E-02

1.00E-03

1.00E+04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

1.00E-11

IDS(A)

VGS (V)

Figure 1.13Sub-threshold IDVDcurvesforanLDMOS device(VD= 0.1V, VD= 28V).

(i.e., electrons). IntheBVDSSdiscussiontheconceptof RESURF wasusedtoillustratethattherearetwoelectricfieldpeakswithinthen-drift regionof anLDMOSdevice.Theelectricfield peak at thedrain edgeof thegateis theonewhichresultsin HCI if it getstoostrong.Under normal transistor operation,electronsareflowingacrossthechannelwiththeaidofalateral electricfield.Aswithavalanchebreakdown,thefieldcanbecomestrong enough that theelectrons areaccelerated toapointwherecollisions withotherelectron-hole pairs or thesilicon latticeoccur. While thefield is not strong enough tobegin theavalancheprocess, thecarriers travelingnear thesurfacecanget misdirected

duringacollisionandendupbeinginjectedintothegateoxide.Howdeepintotheoxidethey areinjecteddependsontheenergy of theelectronandtheavailableenergy statesin theoxide. Onceinjected this electron acts as afixed negativechargewhichinducesapositivecharge in thechannel below it. Depending on exactly wheretheelectron isinjectedtherearetwodifferentdevicedegradationmechanismswhichcanoccur.

If the electron is injected directly over the channel of the device (see Figure 1.2)the impact is on thebias current or IDQunder RF operation. Looking at subthresholdcurvesof atypical LDMOSdevice(Figure1.13) takenwithadrainvoltageof0.1V and28V thereis anobservedshift in thecurves. Thethresholdvoltage(VT) is lower when28V isappliedtothedrain. This is duetoashort-channel effectwithin thefield-effect

transistor (FET). Atthesurfaceof thechannel alargerdepletionregionextendsintothechannel whenlargerdrainvoltagesareapplied.Thisuncoversfixednegativechargeinthechannel. Whenapositivegatevoltageisapplied, it is lookingtogenerateanequivalent

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negativecharge in the channel. This leads to inversion as electrons arecreated at thechannel surface and the threshold voltage has been exceeded. If the larger depletionregionhasalready createdsomenegativechargefor thegateelectric field toterminate

upon,thenlessinversionelectronsarerequiredtocreateacompletelyturned-onchannel.The result is a lowerVT. PA applications will set theDC bias usingthe28 V (in thisexample) drain supply by increasingthegatevoltageaboveVTuntil thedesired IDQisreached. If HCI isoccurringduringnormal deviceoperation,electronsabovethechannelwill induceapositivechargeessentiallyreversingtheincreaseddepletionspreadcausedby the28 V. This increases VTandstarts to de-bias thepart (i.e., IDQdecreases). Overtimeasmoreelectronsareinjected, thedeviceslowly loses itsbiasandthepartwill nolonger operateasneeded in thePA. If theelectron is injected abovethen-drift region,theinducedpositivechargesimply increasesRDSonwhich, asstatedearlier,will result in

decreasedpowercapability. RobustnesstoHCI mustbedesignedintothetransistorandcharacterizationperformedtodefineacceptablelevels.Characterization of HCI affects is performed through stress testingat the DC bias

whichwill beapplied tothedevicein theapplication. A typical basestation PA couldrequire a drain voltage of 32V and an IDQof 4 mA/mmof total gatewidth. A drainvoltageof 32V is appliedandthenthegatevoltageis increaseduntil the4mA/mmisreached.A rapidassessmentof theHCI wouldentail applyingthesteadystateDC stresstothetransistor for 1648hoursso that anextrapolation can bemadeout to20 years;theRDSonand IDQdriftareestablishedby takingperiodicmeasurementsthroughout thestress period. Care should be taken to control the temperature of the device under

test (DUT) as well as theambient temperatureas VTis temperaturesensitiveandcanalso impact the IDQreadings. As described earlier, HCI into the gateoxideabovethechannel regionreversesthedepletionregionspreadcausedbytheDC biasdrainvoltage.Referring to our example onceagain, this means that the VTcurve at 32 V begins tomovetowardtheVT curveatadrainvoltageof 0.1V.Thisisaself-limitingphenomenonwhichmeansthattheinitial impacttoIDQisquitelargeandthenadditional injectionhaslessandlesseffectastimegoeson. HCI degradationcanbeestimatedasalogarithmicresponsebyplottingtheIDQresponseagainstthetimeof stressand(Figure1.14).Mostof thedegradationoccurs in thefirst few hoursand then levelsoff dramatically. Using

this log response, an estimation for the degradation out to 20 years can be made. Awell-designed transistor will keep the 20-year degradation in IDQbelow 10%. This isusually adequatefor ensuringthat the PA remains within performance specifications.RDSonincreasesarealsotabulatedafter thestresstestingdescribedabove.Again,the20-yearresponseshouldbebelow10%butalsoof importanceistheinitial 16hshiftwhichshouldbelowerthan5%(preferably lowerthan3%).It isimportanttonotethatHCI isafunctionof temperature, voltage, andcurrent,andthat theaboveDC testingisintendedto providea device with acceptable HCI sensitivity under most operatingconditions.The final assessment of HCI requires testing in the actual application environment toproperlyaccount for theactual stressconditions.

Many facetsof thedevicestructureimpactHCI sensitivity, including surfaceoxidequality, n-drift junctionprofiles, shield design, etc. HCI mitigationstrategies typicallywork against another deviceparameter (e.g., reduced n-drift doping to lower HCI will

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0.0024

0.00238

0.00236

0.00234

0.00232

0.0023

IDQ(A)

Time (s)

0.00228

0.00226

0.00224

0.00222

0.0022

1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07

20 years

1E+08 1E+09

Figure 1.14HCI induceddegradationof thequiescentcurrent(IDQ) inanLDMOSdevice.

degradeRdsonandpotentially impactBVDSS). Thetradeoffs betweenBVDSS, RDSon, andHCI arefundamental to thedesign of LDMOS and VDMOS transistors. Engineeringvariouswaysof improvingthesetradeoffstoallowfor improvementsinRF performancehas driven device development in this application space for more than 10 years andcontinuestoday. Extensivedevicesimulationisneededtofully understandthecomplexinteractions which areinvolved withany particular devicedesign. It is also importanttoperiodically characterizeHCI under typical applicationconditions toensurethat theDC characterizationremainsrelevant initsabilitytopredictapplicationHCI behavior.

1.3.4 Snapback/ruggedness

VariousRF applicationsrequirethat thedevicesbeabletowithstanddifferent levelsofRF stress theyneedtobeconsideredruggedenoughfortheapplication.Usuallywhatdrivestheruggednessrequiredisthelevel of RF voltage/currentexcursionsexpectedtobeexperiencedby thetransistor. Theseexcursionsarefrequently created by mismatchconditions that occur at theoutput of thedevice. Radar applications, for instance, usepulsed signals whichmay incur transientswhich stress thedevice, while applicationssuch as a CO2laser routinely havethe PA operating into what is essentially an open

circuit. Usually various voltage standing waveratios (VSWRs) areused to stress thedevicestodeterminethelevel of ruggedness.Devicesaretestedat5:1or10:1(orhigher)VSWRsatdifferent levelsof inputoverdrivetoassessrobustness. It isalsocommonto

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ptype epitaxy

p+sinker

PHV region

n+source ndrift region

gate oxide

Drain

oxide

metal strap

Gate

n+drain

p+substrate

Source

Figure 1.15LDMOS cross-sectionillustratingtheparasitic npnbipolar formedbetweenthedrain,channel, andsourceregions.

characterizeruggednessatelevateddrainvoltageswherethedeviceismoresensitivetoruggednessfailures.

Therearetwodevicerelateddesignconcernswhichmustbeconsideredwhenensuringadequatetransistorruggedness:breakdownvoltageandsnapbackcurrent.Theavalanchebreakdownconcept has already been discussed indetail in theprevious section. If RFvoltageswingsareallowedtoexceedthebreakdownvoltagethenthecurrentwithinthedevicerisesrapidly andthereisariskof acatastrophic thermal failureof thetransistor.This means that the first measure of defense against ruggedness failures is designingthepart such that thevoltageswings spend very little time exceeding breakdown. Of

courseonecould design thepart withanextremely largeBVDSSto ensureahigh levelof ruggedness but as is made clear in the previous section this would result in a lossinRF performance. Ideally, thetransistor shouldhavethelowest level ofBVDSSneededto provide adequate ruggedness for the application. This means that at the extremestheBVDSSwill beexceeded, thereforethesecondaspectof ruggednessdesign involvesincreasingthecurrent level which can bewithstoodwhile in breakdown. This is mostdirectly linkedtoaphenomenonknownassnapback.

Referring toFigure 1.15, there is a parasitic bipolar device within the LDMOSstructure(asimilarparasiticbipolardeviceexistswithintheVDMOSstructure indeed,it isabyproductof typical MOSFET structures).Theemitter isthen+ source, thebaseis

thebodyof thedeviceandthecollectoris thedrain.Whenimpactionizationis initiatedandavalanchebreakdownoccurs, there is asudden anddramatic increase in the levelof electronsandholes in thedrainregionof thedevice. Thebuilt-in electric fieldspull

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0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

0 10 20 30 40

VGS = 2.0 V 0 V

3.0 V

3.4 V

on-state

breakdown

off-state

breakdown

4.0 V

4.4 V

5.0 V

5.4 V

6.0 V

7.0 V

50 60 70 80

VDS (V)

IDS(A)

Figure 1.16On-stateversusoff-statebreakdowncurves.

the electrons out of the drain of the transistor, while the holes are injected into thebaseregionof thebipolar transistor. Theholecurrentcanforwardbiastheemitterbasejunction, and so moreelectrons are injected across thechannel and into thehigh fielddrain regionwhichcreatesmoreholesandelectronsduetoavalanchingandcreatingafeedback loop that can result in extremely large, localized current flowsthat result incatastrophicthermal failureof thetransistor. Thisisreferredtoassnapback,andcanbecharacterizedbybothasnapbackvoltageandcurrent.

The goal of enhancing ruggedness is to prevent snapback from occurring by both

delaying the onset of impact ionization, and to design the transistor to minimize theinjectionof holes into thebaseof theparasitic bipolar onceimpactionizationhasbeeninitiated. Increasing thesnapback voltagetypically entails increasing BVDSS. However,BVDSSis the off-statebreakdown voltage; it is equally important to increase the on-state breakdown (seeFigure 1.16). The drain region design (doping levels, shields,etc.) dictates theonandoffstatebreakdown behavior; design for ruggednessbecomesanother of the tradeoffs of the drain engineering process. Strategies to increase thesnapback current entail both moving the location of impact ionization away fromthebaseof theparasitic bipolartransistor,anddesigningthedevicetoshunttheholecurrentto ground, bypassing injection into thebaseof thebipolar.Figure1.17 is an example

illustratingtheeffectonholecurrentbymodifyingthedrainof thedevicetoaccomplishbothgoals(movingtheimpactionizationawayfromthebaseof thebipolar,andshuntingtheholecurrent toground).

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Baseline Optimized

Hole current shunted

to substrate

Hole current

injected into base

Gate Drain Gate Drain

Figure 1.17TCAD simulationof holecurrentdensity for twostructurestakenintoavalanchebreakdown. Theoneof theleftdepictsabaselinedevicewiththemajorityof theholecurrent

beinginjectedinto thebaseof theparasitic npn, whiletheoptimizedstructureontherightshuntstheholecurrenttothegroundedsubstrate, preventinglatch-up.

TLP Voltage

100 20 30 40 50

snapback

0

0.2

0.4

0.6

0.8

1

1.2

1.4

TLPCurrent(A

)

Figure 1.18Typical snapbackcurveduetoturn-onof theparasitic bipolar transistor in anLDMOSdevice.

Characterization of snapback voltage and current is typically carried out using atransmission line pulse generator (TLPG) system, in a similar manner to how ESDsensitivity is characterized. The system works by charging up a transmission line to

successively higher voltages and then throwing a switch allowing the stored energyon the transmission line to enter the transistor. At eachpulse the voltage and currentarerecorded allowinga plottingof thesnapback curve(see Figure1.18). Simple DC

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measurementswill endindestructiononcethesnapbackvoltageisexceeded.TheTLPGsystemallowsvariousdesignparameterstobeinvestigated for their efficacy inaddingruggednesstothedevice.Finally,thefullydesignedpartistestedasdescribedearlierwith

variouslevelsofVSWRsandoverdrives.Thisisalsoatesttodestructionwherethefinallevel ofsurvivabilityisrecorded.Itisimportanttonotethatruggednessperformanceisafunctionnotsimplyof thedevicebutthecompleteoperatingenvironment(surroundingcircuit,inputwaveforms,operatingtemperature,etc.); thefinal assessmentof ruggednessperformancemustbeconducted in thefinal applicationunder realistic operational andstressconditions.

1.3.5 Operating voltage considerations

Althoughconsiderabletimehasbeenspentinthissectiondiscussingwaysof designingthe breakdown voltage for a given device, the focus has largely been on base stationtypedesignswhereavoltagesupply of 2632V isused.LDMOSandVDMOSdevices,however, can be easily adapted to the voltage supply requirements of a wide rangeof applications. The optimumvoltage level tends to be proportional to the RF powerrequirementsof theapplication.

In general, changing the n-drift region length (laterally by layout for LDMOS andvertically by epi thickness for VDMOS) and doping level is the easiest way to tailorthebreakdownvoltagetoagivensupply voltagerequirement. For lower voltageappli-cations such as handset PAs, the voltage can drop as low as 3 V, while for broadcast

applications50V isquickly becomingcommonplace. Other applications in theindus-trial/scientific/medical (ISM)spaceareamenabletoevenhigheroperatingvoltages,withVDMOSdevicesonthemarketdesignedfor100V orhigheroperation(i.e., BVDSSover200V).Typical n-driftregionlengthsrangefrom3mforcellularinfrastructures2832V requirementsdowntotherangeof0.5mforthelowvoltage, low-powerapplications,butcanbeashighas69mfor the50V applicationsandveryhighRF powers. Eachendof thisrangehasitsownsetof designconcernstoconsider.

At thelow-voltageendof thespectrum, suchashortn-drift regionmakes itdifficulttomakethepartresistanttosnapback.Justbythenatureof suchasmall driftregion, the

avalancheprocessisgoingtooccur incloseproximitytothebaseof theparasiticbipolartransistor.Thismakestheuseof ap+ regionaroundthen+ sourcetolowerthegainof thebipolar transistor thatmuchmoreimportantinthesedesigns. For50V LDMOSdesignsthereisthechallengeof achievingbreakdownsinexcessof 100V. Longn-drift regionscoupledwithintelligentshielddesignsareneededtooptimizetheusual setof tradeoffs(RDSon, HCI,ruggedness,andBVDSS).Butatsomepoint,thevertical breakdownbeginstobethelimitingfactorasopposedtothelateral breakdown.Tocircumventthislimitation,a thicker epitaxial layer must be used to extend the amount that the depletion regioncanextendvertically beforehittingthehighly doped p+ substrate. Thelink-upbetweenthep+ sinker andthesubstratemustberedesignedsincethereisnowathicker epi layer

throughwhichalow-resistancepathmust becreated. TheVDMOS devicestructureismoreamenabletoincreasingtheoperatingvoltage. InVDMOS theepi layer thicknessand doping level determinethebreakdowncharacteristics. TheLDMOS structurehas

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1.4 Design/layout 27

Figure 1.19LDMOS discretetransistor layout for an50W devicewith500munit gatewidth(UGW).

moreflexibilitytobedesignedforveryhigh-powerdensity(W/mmgateperiphery)withlowparasiticcapacitanceduetothelateral structureandaccesstoshieldlayers, butthisflexibility tendstobelimitedtobreakdownvoltages in the100130V range. VDMOS

devices,ontheotherhand,canbedesignedwithbreakdownvoltagesinexcessof 200V,butwithrelatively higher parasitic capacitancelevelsthat tendtolimitthefrequencyofoperation.

1.4 Design/layout

1.4.1 Top-down finger layout

LDMOS and VDMOS devices for RF PAs deliver very large amounts of power. It is

notuncommonforasingletransistordietodeliver 50W, andoftentwotofour of theseblocksarearrangedinparallel withinapackagetocreateasingledevicewhichdeliversinexcessof 200W. Generatingthisamount of power requiresavery largegatewidth.Single transistorgatewidthsareroutinely over 50mmandhavebeenknowntorun toover 1 m. This is an extremely largeamount of gateperiphery whichmust begiven alayoutdesignwhichisefficientandoptimizedforRF operation.Thissectionwill discussthevariouscritical designconcernsregardingtop-downlayoutofLDMOSandVDMOSdevices.

The layout of power transistors with very large gate periphery is designed to sat-

isfy anumber of considerations, includingthermal, aspectratio for stressandpackagecompatibility, andfrequencyof operation. Thesolutiontothischallengeistoarrangealargenumber of shorter gates in parallel suchthat they operatein unisonas onetran-sistor. This parallel arrangement is referred toas an array of gatefingers. All of thesefingerssitwithinonelargeactiveareasurroundedbysometypeof fieldoxideisolation.Figure1.19 showsa top-downview of a typical LDMOS layout designed for 50 WRF power at2GHz. Eachgatefinger is 500mwideandis referredtoastheunit gatewidth (UGW) of thetransistor. Two fingers in parallel yields1 mmof gateperiphery.Thefingersarearrayedsuchthat thereissymmetryaroundthecenter of eachdrainandeachsource. This leads totwiceasmany gatefingersas therearedrainfingersaseach

drain(andsource) feedstwogates.TheRF signal andbiases aregoing to beapplied to thebondpadsat theendof the

fingers.Thismeansthateachfingerwill actasatransmissionlineasthesignal progresses

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Figure 1.20Layoutshowinggatebusesfeedinggatetapsspacedat100mintervalsalongthefingersinanLDMOS device.

down its length. To minimizethe transmission line losses or phase delays which canresult, theconcept of gatetaps is introduced. Notice in Figure1.20 that thereisagatecontactevery 100mattachedtoametal lineconnectedtothegatebondpad. Thisgatemetal line or gatebus is used to carry the input signal down the length of the fingerwith minimal transmission line effects due to the high conductivity of the aluminumalloy. This bus is then electrically connected to thegateitself suchthat each500 mgate is actually five100mgates in parallel. Recall that thegate itself also typicallyhasasilicideatopthepolysilicontokeeptheintrinsicgateresistancelow. This silicide

resistance, however, is two to three orders of magnitudehigher in resistance than themetal gatebus, illustratingthenecessityof thegatebus. Otherunitgatewidthsandgatetapspacingsareemployed, typically dictatedby thepower level andfrequency. Largerandlarger UGWs eventually generatetransmissionlinelossesevenwithin thegatebuswhile very small UGWs makefor very poor aspect ratio devices. Higher frequencieswill causetransmissionlinelossestoappear sooner duetotheshorter wavelengthsandit isthereforemorecommontoseelargeUGW devicesoperatinginthe900MHz spaceandbelow inthecellular infrastructurearena.

Finally thedevicepitchmust beconsidered. Thedrain-to-sourcepitchfor LDMOSorsourceto gatepitchfor VDMOS of agiven layout is thedistancebetweeneachaxis

of symmetry within asingle finger (i.e., fromthecenter of thesourcetothecenter ofthedrain for LDMOS,or center of gatetocenter of sourcefor VDMOS). TheLDMOSdrain region is typically kept to a minimumbecause the n+ implant regionneeded to

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1.4 Design/layout 29

makea gooddrain contact is a large contributor to the output capacitancewithin thedevice. Therefore, theminimumn+ drain isdeterminedby theminimumdraincontactdimension plus enclosure rules for the n+ implant. The rest of the drain contributionto pitch is set by the n-drift region requirements of the transistor. The sourceside ofthedeviceallowsfor moreflexibility and can usually beexpanded or contracted to fitagivenpackagespaceormeet athermal requirement. Whenshrinking thesourceareaforLDMOS caremustbetakenthat thep+ sinker implantdoesnot get tooclosetothechannel of thedevice. Recall that thep+ sinker undergoes an aggressivethermal drivetodiffusethedopantdownthroughtheepi tomeetthep+ substrate. Lateral diffusionofthedopant isoccurringat thesametimeandtypically reachesseveral microns. Devicepitch, unit gatewidth, and gatetap spacingareall flexible design parameters that areadjustedbasedontheperformancerequirementsof thepart.

1.4.2 Bond pad manifolds

ToprovideanRF signal tothetransistor, wiresmuchbeconnectedfromtheleadsof thepackageto thesilicon die. In thecaseof LDMOS thereareonly gateand drain wiressince the source is connected through the package flange to ground. This seeminglysimple electrical connection turns out to be quite complex in the field of RF devicedesign, since these elements are not merely electrical conductors but instead theseconductiveelementshavecapacitance, inductance, andtransmissionlinebehaviorsthat

arefundamental totheRF performance.Despitethedesignconsiderationsmentionedintheprevioussection, thetransistordiestill hasalargeaspectratio.Itisnotuncommontohavediewhichare13cmwidewithanarrayoffingersspanningmostof thelength(seeFigure1.1). Placingonegatewirein thecenter of this array will causeatransmissionlineaffecttobepresentfromthecenterfingerstotheoutsidefingers.Eachfingerwill notreceivethesameRF stimulusandthiscanintroducenonuniformitiesindeviceoperationduetophasedifferencesbetweentheindividual fingers.Toremedythissituation,alargenumber of wires in parallel are bonded fromthe package lead to a bond pad whichspanstheentirewidthof thedevice. Thebondpads incur parasitic capacitancebut this

is minimizedby placingthemontopof thefield oxide. Thegoal is to feedthearray offingers as uniformly as possible to maximizeperformance. This parallel arrangementof wires introduces inductanceat the input and output of thedeviceand this must beincorporated intoany matching intendedfor thetransistor. Moreover, thiswirearray istypically utilizedandoptimizedby designers topresentadesirablelevel of impedanceatthepackageleadtoeasethecustomersuseof thepart.

At afiner level of detail, there is design of themetal whichconnects thebond padto the finger itself. Theprimary consideration in this region of the device is resistivelossesduetolargeamountsofRF currentbeingfunneledoutofeachfingerintothelargeexpanseof bondpadmetal. However, designingtomeetelectromigration requirements

typically minimizes this resistive loss (seeSection 1.4.3), so this is not typically aproblem. Nevertheless,flaressuchasshowninFigure1.21canbeusedtominimizetheimpact.

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Figure 1.21Drainmetal flaredesignsfor transitioningfromdrain bustodrainbondpad.

1.4.3 Metal design electromigration

Electromigration is a phenomenon which occurs in metal lines when the DC currentdensitywithin thelinesbecomesexcessiveinconjunctionwithelevatedtemperaturesconditionsthatareeasilymetinRF powerdevices.Momentumtransferduetocollisionsbetween electronsandthemetal conductor atoms can displacethemetal atoms whichleadstoresistanceincreaseandeventually anopencircuitundersevereconditions. Thisis a wearout mechanismwhich occurs over the lifetime of the part and, as such, is areliability consideration. Electromigration is discussed further in Chapter 10,but thissectiondiscusseshow todesignadevice properly such that adequateelectromigrationlifetimesareachieved.

To begin designing for electromigration robustness, the metal being used must becharacterized with various current and temperaturestress tests. Different metal alloysandmetal typesvary widely intheir electromigrationresponses.Gold, for instance, hasmuch higher electromigration resistance than aluminum. Aluminumalloys, typicallyformed by the addition of a small percentage of copper [27] have been developedand are in widespread use in the semiconductor indu

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