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Modeling Nanoscale MOSFETs By a Neural Network

Approach

Min Fang, Jin He, Jian Zhang, Lining Zhang, Mansun Chan, and Chenyue Ma

Abstract - This paper presents modeling nanometer

MOSFETs by a neural network approach. The

principle of this approach is firstly introduced and its

application in modeling DC and conductance

characteristics of nano-MOSFET is demonstrated in

details. It is shown that this approach does not need

parameter extraction routine while its prediction of

the transistor performance has a small relative error

within 1% compared with measure data, thus its

result is as accurate as that BSIM model.

.

I. INTRODUCTIONFollowing the ITRS prediction, the CMOS integrated

circuit will soon approach 32nm technology generation

in two or three years, and the compact model for suchnanoscale MOSFETs is highly required for the deviceoptimization and circuit analysis. The traditional devicemodels such as BSIM and PICM models use thethreshold voltage method to construct the compactmodel framework. Such a model approach, however, is

generally believed to be outdated due to the regionalcharacteristics, too many fitting parameter which lead to

complex parameter extraction routine, thus requires a

paradigm shift in the core model structure. In such abackground, the advanced MOSFET model approachessuch as surface potential based and charge-based become

popular in compact modeling community in recentseveral years. These new developments will replaced the

threshold voltage based model for us to be sued in thenanoscale MOSFET circuit simulation and analysis.

In this paper, we forsake the traditional method anddevelop a neural network approach to modelingnanoscale MOSFET transistor. When comparing with themeasured data, the accuracy of this appraoch is

satisfactory for the compact modeling application because the relative error is within 1%. The paper is

divided into four sections, the section one is a simpleintroduction, and in section two we give a description ofthe neural network principle and its algorithm-back propagation algorithm. In section three, we design a

neural network to model the DC and conductance performance of different size MOSFET device. Insection four we show the neural network method resultcompared with the measurement data and BSIM model.The final is the conclusion and acknowledgement.

Min Fang Jin He and Mansun Chan are with the Key

Laboratory of Integrated Microsystems, Peking UniversityShenzhen Graduate School, Shenzhen, China;

Jin He, Jian Zhang, Lining Zhang, and Chenyue Ma are withTSRC, Key Laboratory of Microelectronic Devices andCircuits, Ministry of Education, EECS, Peking University,

Beijing, China, E-mail:jinhe@ime.pku.edu.cn

II. NEURAL NETWORK PRINCIPLE AND BACK

PROPAGATION ALGORITHM

We first describe the neural network structure to better

understand what neural network is and why it has theability to model nanoscale MOS transistor performance.We start the neural network from the externalinput-output-point-of-view, and also from the internalneuron information processing point-of-view. The most popularly used neural network structure is themultiplayer perception (MLP) as shown in Fig.1. A

typical neural network structure has two types of basiccomponents, namely, the processing elements andinterconnections between them. The processing elementsare called neuron and the connections between theneurons are known as links or synapses. Every link has acorresponding weight parameter associated wit it. Each

neuron receives stimulus from other neurons connectedto it, processes the information, and produced an output. Neurons that receive stimuli from outside network arecalled input neurons, while neurons whose outputs areused externally are called output neurons. Neurons thatreceive stimuli from other neurons and whose outputsare stimuli for other neurons in the network are known as

hidden neurons. Different neural network framework can be constructed by using different type and amount ofneurons and by connecting them differently. The typeand amount determine the network scale and theconnecting algorithm determines network efficiency andaccuracy. In this paper, we used a so-called back propagation algorithm, which may be suitable for the

nanoscale device modeling [1].P.J.Werbos first depicted the back-propagation

algorithm in his Ph.D thesis [2]. It became widely usedafter it was rediscovered by Rumehlhart, Hinton,Williams [3], David Parker and Yann Le Cun [4]. Someresearch results proven that MLP feed forward networks

with arbitrary squashing functions can be approximatedas a bore integrable function from one finite dimensionalspace to another finite dimensional space. Fig.1 is athree-layer forward neural network, there are R neuroninputs, S

1, S2, and S3 neurons in the first, second and

third layer, respectively. The output of one layer becomes the input to the following layer, the equation

that describe this operation is as follows:3 3 3 2 2 1 1 1 2 3( ( ( ) ) )a f w f w f w p b b b (1)

wi, bi denote the weight and bias matrix of the ith layer.The work principle of the neural network shown in

Fig.1 includes two different stages: training and working.

In the former stage, data is sent into the input layer of thenetwork and transmitted to the output layer. The training process needs to be repeated until the error reaching adefined value. The parameters are updated by using the

978-1-4244-2540-2/08/$25.00 2008 IEEE

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steepest descent back programming algorithm [1], butsome disadvantages limits its action in practice.

As an improved, the Levenberg-Marquardt algorithmis a variation of Newtons method that was designed forminimizing functions that are sums of squares of othernonlinear function, this algorithm is well suited to neuralnetwork training. The Levenberg-Marquardt algorithm is

written as1

1 ( ( ) ( ) )T T

K K K K K X X J X J X I J

(2)

Where the XK is the weights or bias matrix of the Kth

epoch of network, J(XK) is the Jacobian matrix thatcontain first derivatives of the network errors with

respect to the weights and biases, V(XK) is a vector ofnetwork errors.

This algorithm has a very useful feature: As Kincreases it approaches the steepest descent algorithmwith small learning rate:

1 11 ( ) ( ) (2 ) ( )TK K K K K K K X X J X V X X X F X (3)

While as K decreases to zero the algorithm becomesGauss-Newton algorithm:

1

1 ( ( ) ( )) ( ) ( )T T

K K K K K K X X J X J X J X V X

(4)

The algorithm begins with being set to some small

value. If a step does not yield a smaller value for F(X),

then the step is repeated with multiplied by some

factor>1, eventually F(X) should descent; otherwiseKis divided by for the next step, so that the algorithmwill approach Gauss-Newton which should providefaster convergence. The algorithm provides a goodcompromise between the speed of Newtons method andthe guaranteed convergence of steepest descent [1].

III. NEURAL NETWORK APPROACHTO

MODELING NANOSCALE TRANSISTOR

Here, we select a three-layer forward network, thenetwork has 6 inputs parameters: drain-source voltage(Vds), gate-source voltage (Vgs), bulk-source voltage(Vbs ), length (L), width (W), and temperature (T). The

network has 16,8,1 neurons in the first, second and thirdlayer and the corresponding transfer function f1, f2, and f3

is hyperbolic tangent sigmoid, log-sigmoid and linearfunction, the output is the drain-source current.

TABLE

Ids-Vds TRAINING DATA

measure Parameters range

Vds (V) 0.05:0.05:1.3

Vbs(V) -0.75, -0.5, 0

Vgs (V) 0.2:0.2:1.2

W/L(m) 0.1/0.08,0.24/0.08,0.5/0.08,1/0.08,

0.12/0.09,0.12/0.1, 0.12/0.12,2/0.24

T( ) -55,25,125

TABLE

Ids-Vgs TRAINING DATA

measure Parameters range

Vds (V) 0.05:0.05:1.2

Vbs (V) -1, -0.5,0,0.25

Vgs (V) 0.0:0.05:1.35

W/L (m) 0.1/0.08, 0.24/0.08, 0.5/0.08,0.12/0.09, 0.12/0.1,0.12/0.12,2/0.24

T() -55,25,125

This network can model the transistor DC and ACcharacterization of nanoscale MOSFETs. We firstly trainthe network with the measure data coming from 90nm

CMOS production process. The training data is show in

TABLE ) and TABLE ), the training algorithm is

the Levenberg-Marquardt algorithm, after epochs to 300,the output of the network compared with the measuredata, has only the relative error within 1%, thecorresponding result is show in Fig.2-3 and Fig.4-5.

Fig. 1. Three layer forward network diagram.

0.0 0.4 0.8 1.20.0

3.0x10-4

6.0x10-4

9.0x10-4

Ids

(A)

Vds(V)

me asure ne ura l

vgs=0.2

vgs=0.4

vgs=0.6

vgs=0.8

vgs=1.0

vgs=1.2

Trained W/L/T=2.0/0.24/125 Vbs=-0.5V

Fig. 2. Comparison of the trained MOSFET output performance with the measured data for the transistor

with W/L/T=2/0.24/125 and Vbs=-0.5V. The dot is themeasure data and the line is the neural network output.

0.0 0.4 0.8 1.2

10-6

10-5

10-4

10-3

log

gds

(A/V)

Vds

(V)

measu neur

Vgs=0.2

Vgs=0.4

Vgs=0.6

Vgs=0.8

Vgs=1.0

Vgs=1.2

Trained W/L/T=2.0/0.24/125 Vbs=-0.5V

Fig. 3. Trans-conductance (gm) comparison obtainedfrom above Fig.2.

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0.0 0.4 0.8 1.20.0

5.0x10-5

1.0x10-4

1.5x10-4

Ids

(A)

Vgs

(V)

measu neur

Vbs=-1.0Vbs=-0.5Vbs=-0.0Vbs=0.25

Trained W/L/T=0.12/0.12/-55 Vds=1.2V

0.0 0.4 0.8 1.20.0

5.0x10-5

1.0x10-4

1.5x10-4

gm

(A/V)

Vgs(V)

measu neur

Vbs=-1.0

Vbs=-0.5

Vbs=-0.0

Vbs=0.25

Trained W/L/T=0.12/0.12/-55 Vds

=1.2V

Fig. 4 Fig. 5

Fig. 4. Comparison of the trained MOSFET transfer performance with the measured data for the transistorwith W/L/T=0.12/0.12/-55 and Vds=1.2V.Fig. 5.Comparison ofgm obtained from Fig. 4.

0.0 0.4 0.8 1.20.0

2.0x10-4

4.0x10-4

Ids

(A)

Vds

(V)

meas neur

vgs=0.2

vgs=0.4

vgs=0.6

vgs=0.8

vgs=1.0

vgs=1.2

Working for W/L/T=0.5/0.08/25 Vbs=-0.75V

Fig. 6. The comparison of the neural network predicted

output performance with the measured data for thetransistor with W/L/T=0.5/0.08/25 and Vbs=-0.75V.

0.0 0.4 0.8 1.2

10-6

10-5

10-4

10-3

log(g

ds

)(A/V)

Vds

(V)

measu neur

Vgs=0.2

Vgs=0.4

Vgs=0.6

Vgs=0.8

Vgs=1.0

Vgs=1.2

working for W/L/T=0.5/0.08/25 Vbs=-0.75V

Fig. 7. The output-conductance comparison from Fig. 6.

0.0 0.4 0.8 1.20.0

1.0x10-4

2.0x10-4

3.0x10-4

Ids

(A)

Vgs(V)

me as u n eur Vbs=-1.0

Vbs=-0.5

Vbs=-0.0Vbs=0.25

Working for W/L/T=0.24/0.08/-55 Vds=1.0V

0.0 0.4 0.8 1.20.0

1.0x10-4

2.0x10-4

3.0x10-4

4.0x10-4

gm

(A/V)

Vgs

(V)

measu ne ur

Vbs=-1.0

Vbs=-0.5

Vbs=-0.0Vbs=0.25

Working for W/L/T=0.24/0.08/-55 Vds=1.0V

Fig. 8 Fig. 9

Fig. 8. Comparison of the neural network predictedtransfer performance of the MOSFET withW/L/T=0.24/0.08/-55V and Vds=1.0V.

Fig. 9. Comparison ofgm from Fig.8.

Based on the training results, the trained network canwork now. Measured data with W/L/T=0.5/0.08/25compared with the neural network worked results, as

shown in Fig.6-7 and Fig.8-9. It is found from thesefigures that the relative error between the neural networkprediction and measured data is about 1%.

IV. RESULT CMPARISON BETWEENTHENEURAL

NETWORKMETHODAND BSIM MODEL

In order to validate the neural network method, we usethe neural network method and BSIM model to fit thesame measured data of the same nanosale transistor. Theresults and the relative errors are shown in from Fig.10to Fig.17. It is found that the relative error between theneural network method and the measured date is about

1% while the relative error between the BSIM model andthe measured data is larger than 1% in most cases. Sowe can conclude that the neural network method is atleast as accurate as BSIM model, and can be used tomodel nanoscale MOSFET transistor.

0.0

1.0x10-4

2.0x10-4

3.0x10-4

4.0x10-4

5.0x10-4

0.0 0.4 0.8 1.2

Ids

(A)

Vds(V)

measure neural bsim

vgs=0.2

vgs=0.4vgs=0.6

W/L/T=0.5/0.08/25 Vbs=-0.75V

vgs=0.8

vgs=1.0vgs=1.2

Fig. 10. Comparison of output characteristics fromneural network method, BSIM model, and measureddata.

0.0 0.4 0.8 1.2

1

2

3

4

5

Relativeerror

Vds(V)

neural bsim

vgs=0.2

vgs=0.4

vgs=0.6

vgs=0.8

vgs=1.0

vgs=1.2

W/L/T=0.5/0.08/25 Vbs=-0.75V

Fig. 11. The relative error comparison of the output

characteristics from the neural network method andBSIM model compared with measured data.

0.0 0.4 0.8 1.2

10-7

10-6

10-5

10-4

10-3

Vgs=0.8

Vgs=1.0

Vgs=1.2

loggds

(A/V)

Vds(V)

measure neural bsim

Vgs=0.2

Vgs=0.4

Vgs=0.6

W/L/T=O.5/0.08/25 Vbs=-0.75V

Fig. 12. Comparison ofoutput-conductance from neuralnetwork method, BSIM model, and measured data.

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0.0 0.4 0.8 1.2

1

2

3

4

5

Relativeerror

Vds(V)

neural bsim

vgs=0.2

vgs=0.4

vgs=0.6

vgs=0.8

vgs=1.0

vgs=1.2

W/L/T=0.5/0.08/25 Vbs=-0.75V

Fig. 13. The relative error comparison of output-

conductance from neural network method and BSIMmodel compared with measured data.

0.0 0.4 0.8 1.20.0

1.0x10-4

2.0x10

-4

3.0x10-4

ids(A

)

Vgs(V)

measure neural bsim

Vbs=-1.0

Vbs=-0.5

Vbs=-0.0

Vbs=0.25

W/L/T=0.24/0.08/-55 Vds=1.0V

Fig. 14. The comparison of Ids-Vgs from the neuralnetwork method, BSIM model, and measured data.

0.4 0.8 1.20.00

0.03

0.06

0.09

0.12

0.15

relativeerror

Vgs(V)

neural bsim

Vbs=-1.0

Vbs=-0.5

Vbs=-0.0

Vbs=0.25

W/L/T=0.24/0.08/-55 Vds=1.0V

Fig. 15. The relative error comparison of Ids-Vgs fromthe neural network method and BSIM model comparedwith measured data.

0.0 0.4 0.8 1.20.0

1.0x10-4

2.0x10-4

3.0x10-4

gm

(A/V)

Vgs (V)

measure neural bsim

Vbs=-1.0

Vbs=-0.5

Vbs=-0.0

Vbs=0.25

W/L/T=0.24/0.08/-55 Vds=1.0V

Fig. 16. Comparison ofgm from neural network method,BSIM model, and measured data.

0.4 0.8 1.20.0

0.1

0.2

0.3

relativeerror

Vgs(V)

neural bsim

Vbs=-1.0

Vbs=-0.5

Vbs=-0.0

Vbs=0.25

W/L/T=0.24/0.08/-55 Vds=1.0V

Fig. 17. The relative error comparison ofgm from theNeural network method and BSIM model compared with

the Measure data.

V. CONCLUSIONS

In this paper we present a neural network approach to

modeling nanoscale MOSFET transistor performance.The MLP neural network application in modelingnanoscale MOSFETs is demonstrated in details via thetraining and working processing. It is shown that theneural network approach does not need extraction

parameters while also having some other advantages: thecharacteristic curve can be differentiable from first order

to infinite order in all transistor operation regions.Moreover, The used neural network methods accuracy istested and is further validated by compared with BSIMmodel.

ACKNOWLEDGMENT

This work is subsidized by the National naturalScience Funds of China (90607017). This work is alsopartially supported by a NEDO grant from Japan.

REFERENCES

[1] Martin.Hagan, Howard B.Demuth, Mark H.Beale,Neural network design, PWS, 1996.

[2] P.J.Werbos, beyond regression: new tools for prediction and analysis in the behavioral sciences,Ph.D.Thesis, tionHarvard University, Cambridge,MA, 1974.

[3] D.E.Rumelhart, G.E.Hinton and R.J.Williams,

learning representations by back propagatingerrors, Nature, vol.323, pp.533- 536, 1986.

[4] D.B.Parker, learning-logic: casting the cortex of thehuman brain in silicon, Technique Report TR-47,Center for computational research in economics andmanagement science, MIT, Cambridge, MA, 1985.