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508 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007
Optimal Modulation of Flying Capacitor and StackedMulticell Converters Using a State Machine Decoder
Brendan Peter McGrath, Member, IEEE, Thierry Meynard, Member, IEEE, Guillaume Gateau, andDonald Grahame Holmes, Senior Member, IEEE
AbstractModulation of flying capacitor and stacked multicellconverters is complicated by the fact that these converters haveredundant states that achieve the same phase leg voltage output.Hence, a modulator must use some secondary criteria such as cellvoltage balancing to fully define the converter switched state. Al-ternatively, the modulator can be adapted to directly specify thecell states, such as has been proposed for the harmonically optimalphase disposition (PD) strategy. However the techniques reportedto date can lead to uneven distribution of switching transitions be-tween cells, and the synthesis of narrow switched phase leg pulses.
This paper presents an improved strategy that decouples thetasks of voltage level selection and switching event distribution.Conventional PD and centered space vector pulsewidth modula-tion (CSVPWM) strategies are used to define the target voltagelevel for the converter, and a finite state machine is then used todistribute the transitions to the converter cells in a cyclical fashion.Experimental results for a four-level flying capacitor inverter arepresented, verifying that the natural balancing properties of thisconverter has been preserved, the cell switching utilization is equaland the expected harmonic gains of PD and CSVPWM comparedto phase shifted carrier PWM have been achieved.
Index TermsFlying capacitor, multicell, multilevel spacevector modulation (SVM), natural balance, phase disposition(PD), stacked multicell (SMC).
I. INTRODUCTION
THE flying capacitor converter [1], and its derivative, the
stacked multicell converter (SMC) [2], have many attrac-
tive properties for medium voltage applications, including in
particular the advantage of transformerless operation, and the
ability to naturally maintain the cell capacitor voltages at their
target operating levels [1]. This property is called natural bal-
ancing, and allows in principle the construction of such con-
verters with a large number of voltage levels. The flying capac-
itor (or multicell) converter, shown in Fig. 1(a), uses a seriesconnection of cells comprising a flying capacitor and its as-
sociated complimentary switch pair, and produces a switched
Manuscript received June 24, 2005; revised May 16, 2006. This paper waspresented at the IEEE Power Electronics Specialists Conference (PESC),Recife, Brazil, June 2005. Recommended for publication by Associate EditorR. Zhang.
B. P. McGrath was with the School of Electrical Engineering and ComputerScience, The University of Newcastle, Callaghan, NSW 2308, Australiaand is now with Monash University, Clayton 3800, Australia (e-mail:[email protected]; [email protected]).
T. Meynard is with the Groupe Convertisseurs Statiques, Laboratoire dElec-trotechnique et dElectronique Industrielle (LEEI), Toulouse 31071, France.
D. G. Holmes is with the Department of Electrical and Computer SystemsEngineering, Monash University, Clayton 3800, Australia.
Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2006.889932
Fig. 1. Single-phase, five-level structures for (a) flying capacitor and(b) stacked multicell converters.
voltage that is the sum of the individual cell states. The SMC,
shown in Fig. 1(b), stacks two flying capacitor converters to-
gether, with the upper stack switching only when a positive
output is required, and the lower stack switching only when a
negative output is required [2].
The modulation of these two converter structures has sim-
ilar challenges to the cascaded multilevel converter, since all
three topologies have redundant states that achieve the same
phase leg voltage output (see Table I for the converter states for
five-level flying capacitor and SMC systems). Therefore, a mod-
ulator must control each phase leg both to achieve the required
target voltage levels, and to incorporate additional criteria to
fully define the state of the phase legs at each switching in-
stant. The typical criteria are to balance the number of switching
transitions between the cells, and also to preserve the natural
balancing property of these converters. Note that these con-
straints usually require that all cells switch with approximately
the same frequency and duty cycle [1]. The conventional mod-
ulation approach for these converters is phase shifted carrier
pulsewidth modulation (PSCPWM), which automatically sat-
isfies the secondary objectives [1]. However, for three phase
0885-8993/$25.00 2007 IEEE
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MCGRATH et al.: OPTIMAL MODULATION OF FLYING CAPACITOR AND STACKED MULTICELL CONVERTERS 509
TABLE ISWITCHING STATES FOR FIVE-LEVEL FLYING
CAPACITOR AND SMC CONVERTERS
systems this strategy is now known to be spectrally suboptimal
compared to phase disposition (PD) and centered space vectorPWM (CSVPWM) [3][5].
Various strategies have been proposed to improve the har-
monic performance of converters with redundant phase leg
states by implementing PD PWM instead of PSCPWM. These
strategies adapt a conventional PD modulator to directly control
the cell states, incorporating either discontinuous reference
waveforms or reduced magnitude trapezoidal carrier waveforms
that change their mark space ratio as the reference waveforms
move between carrier disposition bands [6][8]. However, these
strategies do not evenly distribute switching transitions between
cells as the reference waveforms cross the disposition bands,
and they can also create narrow pulses that can be particularly
problematic for high power converters [9].This paper presents an improved modulation strategy for
flying capacitor and SMC systems that decouples the level
selection and cell switching event distribution processes. First,
conventional PD and CSVPWM strategies are used to define
the target voltage level for each multilevel phase leg. Then, a
state machine is used to allocate the switching events to the
converter cells in a cyclical fashion. This balances the switching
transitions between the converter cells, avoids creating narrow
switching pulses, and also preserves the natural balancing
property of these converters. Simulation and experimental
results are presented to verify the effectiveness of the strategy.
II. CARRIER PWM FOR MULTICELL CONVERTERS
The conventional carrier PWM strategy for multicell con-
verters is PSCPWM, which is illustrated for the five-level case
in Fig. 2. With PSCPWM, a sine-triangle comparison con-
trols the cell switching, with each cell having a unique carrier
waveform and a common reference waveform. For an -level
inverter, this strategy achieves its best harmonic performance
when the carrier waveforms are phase shifted with respect to
one another according to
(1)
PSCPWM is known to achieve a balanced distribution ofswitching pulses, while maintaining the natural balancing of the
Fig. 2. Phase shifted carrier PWM for a five-level converter.
Fig. 3. Five-levelPD and CSVPWM: (a) PD modulator with thecorrespondingswitched phase voltage and (b) CSVPWM Modulator.
cell capacitor voltages. However, it is spectrally sub-optimal
compared to the phase disposition (PD) and centered spacevector (CSV) PWM methods.
The PD method applied to an -level converter arranges
1 carrier waveforms of the same amplitude, frequency and
phase into contiguous bands that fully occupy the linear mod-
ulation range. The intersections of the low frequency reference
waveforms with these carrier waveforms dictate the switched
voltage level for each phase leg at any instant, as shown in
Fig. 3(a). This strategy is spectrally superior because it produces
a large carrier harmonic in the phase voltage spectrum that can-
cels in the line-to-line voltage, thereby reducing the output har-
monic distortion [3].
A PD modulator can be further refined by recognising that
the space vector states implicitly selected by the modulator arenot centered within the equivalent half-carrier interval. Previous
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510 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007
Fig. 4. Five-level trapezoidal carrier for decoded PD PWM of a cascaded orflying capacitor converter.
work has shown that vector centering can be achieved by adding
a common mode offset to the three reference waveforms of a PD
modulator [4], [5]. The common mode offset includes a third
harmonic component, given by
(2)
where ; and a modulo function component which
identifies the references responsible for the first and last
switching transitions in the interval, according to
(3)
This component enables the space vectors to be centered.
Equations (2) and (3) can then be combined to achieve the finalreference waveforms of
(4)
Fig. 3(b) shows a five-level example of a CSVPWM modu-
lator using (2)(4). CSVPWM is currently identified in the lit-
erature as the optimal harmonic approach for a carrier based
multilevel PWM modulator [4], [5].
The output of a PD or a CSVPWM modulator is a required
switched voltage level, which must then be decoded for the
multicell and SMC systems to select specific cell states. This
can be done by allocating each rising and falling switchingevent to specific cells, so that the sum of the cell outputs always
achieves the target switched voltage. Previous work [6][8]
has shown how this decoding is achieved for cascaded and
flying capacitor converters if each cells phase leg reference
is compared against a reduced magnitude trapezoidal carrier
waveform whose duty cycle varies for each disposition band, as
shown for a five-level system in Fig. 4. If 1 such carriers
are phase shifted according to (1) the resulting carrier/reference
intersections achieve PD or CSV PWM, as shown in the lower
section of Fig. 4. However, this approach does not evenly dis-
tribute the switching transitions between cells, as illustrated in
Fig. 5 for a five-level system, switching with a pulse ratio of 15.
From Fig. 5, it can be seen that cell 2 switches twice as much ascell 4, while cells 2 and 3 also sometimes double switch rapidly
Fig. 5. Flying capacitor cell pulse patterns for a five-level decoded PD modu-latorasymmetric sampling.
to produce very narrow pulses. These switching problems occur
as the reference waveforms cross the disposition bands, and
shift to a new trapezoidal carrier. Hence, decoding PD and CSV
modulation in this way for flying capacitor and SMC systems
is clearly suboptimal.
III. STATE MACHINE BASED PWM DECODER
The problems of narrow pulse widths and uneven switching
load can be solved by expanding the switching allocation
process to consider sequential switching transitions that arise
when the reference waveform crosses the boundaries betweendisposition bands. This can be done using a conventional PD
or CSV modulator to select the target switched voltage for
each phase, and then a finite state machine to distribute the
switching pulses among the cells on a cyclical basis. State
machine structures for both flying capacitor and SMC systems
will now be developed.
A. State Machine for Flying Capacitor Converters
An -level flying capacitor converter has 1 cells that
must switch at the same rate with approximately the same duty
cycle, to satisfy both the balanced switching load and natural
voltage balancing criteria. With this in mind, Fig. 6(a) showsthe target cell switching transitions for a five-level flying capac-
itor converter under PD PWM, where the phase leg reference
waveform lies totally within the uppermost disposition band,
i.e., levels 3 and 4. The cyclical allocation of transitions between
the four converter cells is clearly evident. From these patterns a
state transition diagram can be defined for the uppermost dispo-
sition band only, as shown in Fig. 6(b). The state transitions are
triggered from the modulator switching signals.
This process can be repeated for each disposition band. It
should be immediately apparent that for an -level inverter, a
complete state transition diagram will contain 1 sub-dia-
grams corresponding to each disposition band, and there will be
2 1 states per sub-diagram, corresponding to one risingand falling transition per cell. It then remains to determine the
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Fig. 6. State diagram derived from target cell transitions. (a) PD PWM targetcell switching patterns when the phase leg reference is in the upper dispositionvoltage band. (b) Corresponding state transition diagram.
transitions between each sub-diagram to create the complete
state structure. This is illustrated for the five-level case in Fig. 7,where the four rows of states represent each disposition band.
Transitions between these rows indicate the disposition band
changes, and such transitions occur following a sequence of two
rising or two falling transitions in a row (e.g., from state 1,1,1,1
in the upper row and the modulator selecting level 3 followed
immediately by level 2). The precise state to which these band
change transitions lead is determined by enforcing a cyclical al-
location of transitions to the cells. So for example, when in the
state 1,0,0,0 in the bottom row of the diagram, the last cell to
switch on was cell 1. Hence, cell 2 must make the next rising
transition. Therefore with a rising band change the next state
must be 1,1,0,0 in row 2. Applying this rule, and allowing fordouble rising or falling transitions from any state it is possible
to account for all possible disposition band changes, as shown
in Fig. 7.
Fig. 8 shows a five-level PD modulator with a pulse ratio of
15 decoded using the state machine structure shown in Fig. 7.
It is immediately clear that the state machine has allocated each
of the disposition band changes to different cells, thereby elim-
inating narrow pulse problems, and distributing the switching
transitions evenly. The efficacy of the state machine approach
has also been tested for asynchronous PWM with similar results,
including the harmonic performance. This is of course not un-
expected, since recent work has shown that integer and triplen
pulse ratios are not required for optimal harmonic performancewith PD and CSVPWM [10].
Fig. 7. Complete state machine for a five-level flying capacitor inverter.
Fig. 8. Flying capacitor cell pulse patterns for a five-level PD modulator witha state machine decoderasymmetric sampling.
Since cascaded and flying capacitor converters have exactly
the same degree of phase voltage redundancy, the state machine
structure for a flying capacitor inverter is applicable to cascaded
inverters. However it should be recognized that the output of
a flying capacitor inverter is the sum of cell states, but for a
cascaded inverter the output is the sum of H-Bridge states. Since
H-Bridges consist of a pair of two-level phase legs, one of which
adds to the H-Bridge output while the other subtracts from the
output, it is therefore necessary to invert the state machine logic
for this latter group of H-Bridge two-level phase legs. However
this is a trivial modification to the state machine structure.
B. State Machine for Stacked Multicell Converters (SMC)
SMCs are madeup oftwo flying capacitor converters stacked
together as shown in Fig. 1(b), with the upper stack creating a
positive output while the lower stack creates the negative output.
This constraint reduces the redundancy options for an SMC, sothat for an -level converter each stack has states that follow
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512 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007
Fig. 9. Complete state machine for a seven-level SMC.
the equivalent redundancy pattern of a 1 2 level flying
capacitor inverter, while the zero state is not redundant (i.e., thestate , , , 0, 0, 1, 1 in Fig. 1(b)). Hence, it is
possible to build a state machine for an SMC by stacking two
multicell converter state machines of reduced order together, as
is illustrated for the seven-level case in Fig. 9.
Once again the state machine is composed of 1 rows
representing the 1 disposition carrier bands. However
unlike the flying capacitor state machine there are now only
1 states per row which correspond the 1 2 cells
per stack, which are allowed to switch in any given disposition
band. This is, however, the only significant difference between
the state structures of the flying capacitor and SMC systems.
C. Level Transitions Greater Than 1
The state machine structures presented so far only consider
incremental level transitions, but there may be cases, such as
transient conditions, where level transitions greater than 1 may
occur. This type of event must also be included in the state ma-
chine, with the transitions ensuring that the switching events are
evenly distributed between all cells.
To illustrate this, consider the state 0,0,0,0 in the sub-set of
the five-level state machine shown in Fig. 10. Under a level tran-
sition of 1, the state machine advances to 1,0,0,0 in accordance
with the rules identified previously. However, under a level tran-
sition of 2, the target state is 1,1,0,0 whereby both cells 1 and
2 have been turned on. This state is the fourth entry in row 2 ofthe state machine, and importantly is also the target state from
Fig. 10. State machine sub-set including level transitions greater than 1.
TABLE IIFOUR-LEVEL FLYING CAPACITOR CONVERTERCIRCUIT PARAMETERS
0,0,0,0 following two subsequent incremental rising transitions.
Similar observations can be made for a level selection signal ofzero, while in state 1,0,0,1. Thus for rising or falling level transi-
tions of magnitude , the target state that must be encoded to en-
sure an equal distribution of switching events is simply the state
that would be arrived at following incremental or decremental
transitions respectively. Hence, the practical implementation of
the state machine can be realized either by coding nonsingular
transitions explicitly (as was done in this study) or by slew rate
limiting the reference waveform to one transition per half car-
rier interval (the sample period).
IV. SIMULATION AND EXPERIMENTAL RESULTS
To ensure that the use of a state machine to decode the PDand CSV modulators does achieve the target spectral perfor-
mance, and also preserves the natural balancing characteristic of
the flying capacitor and SMC systems, simulation studies using
MATLAB/SIMULINK were performed. The balancing charac-
teristic was investigated using single phase simulations with a
PD modulator for a four-level flying capacitor converter and a
seven-level SMC. Tables II and III provide the circuit parame-
ters for each converter for the simulation studies performed.
The balance booster parameters in Tables II and III refer to a
series RLC filter that is placed in parallel to the load. This filter
presents a low impedance at the cell switching frequency, and
thus improves the dynamic balancing response of the converter
[1]. For three phase structures the balance booster is configuredin a wye arrangement.
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TABLE III
SEVEN-LEVEL STACKED MULTICELL CONVERTERCIRCUIT PARAMETERS
Fig. 11. Start-up transient for the flying capacitor voltages with uncharged ini-tial conditionsfour-level flying capacitor Inverter.
Fig. 12. Start-up transient for the flying capacitor voltages with uncharged ini-
tial conditionsseven-level SMC.
Figs. 11 and 12 show the start-up transients for both con-
verters, using the state machine decoders with PD modulators
with the flying capacitors initially uncharged. Note that this is an
abnormal operating condition, since the flying capacitors would
normally be precharged to their target operating values to pre-
vent destruction of the switching devices. Thus the investiga-
tion of this type of transient response is the worst case unbal-
anced condition. Hence, it is useful, because in both figures it
is clear that the flying capacitor voltages still naturally evolve
to their target operating voltages, confirming that the state ma-
chine decoder does preserve the natural balancing property ofthese converters.
Fig. 13. Experimental switched voltages, and filtered load current. PD PWMwith state machine decoder.
Fig. 14. Experimental switched phase voltage and cell command signals. PDPWM with state machine decoder.
The PD and CSV modulators were also investigated experi-
mentally using a four-level three phase flying capacitor inverter,
with again the same circuit parameters as those presented in
Table II. The modulator functions and the state machine decoder
were programmed onto an Altera ACEX1K EP1K100QC20802
FPGA device, while the reference waveform generation,common mode offset injection and converter supervisory func-
tions were performed using a TMS320C6711DSP processor.
Fig. 13 shows the converter switched voltages and filtered
load current. The four distinct voltage levels in the phase leg
voltage confirm that the flying capacitor voltages have stabi-
lized to their nominal operating points, while the seven-level
line-to-line voltage waveform shows a trademark characteristic
of PD PWM in that the switched voltages lie within a single
voltage band at any one time. Fig. 14 shows more detail of the
switched phase voltage and associated cell command signals
through two falling disposition band transitions (evidenced by
the phase leg switched voltage progressing across four levels).
It is clear from this figure that the state machine has allocatedthe transitions evenly to each cell, avoiding narrow pulses. Note
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514 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007
Fig. 15. Simulated line to line voltage spectrum, four-level PD PWM.
Fig. 16. Experimental voltage spectrum, four-level flying capacitor in-verter. PD PWM with state machine decoder.
also that while the modulator itself may demand narrow pulse
widths, the decoder always distributes the switching events for
that pulse to different cells, as illustrated in Fig. 14. Hence,
narrow pulses will only be a potential problem at over and undermodulation limits, as is standard for any converter [10].
Fig. 15 shows the simulated line-to-line voltage spectrum
for PD PWM. Figs. 16 and 17 show experimental line-to-line
and phase leg voltage spectra for the system under PD modula-
tion. The large carrier harmonic (20% at 4.5 kHz) in the phase
voltage spectrum is clearly evident, as is the cancellation of this
component in the line-to-line voltage spectrum. Also, the match
between simulation and experimental results confirms that the
state machine implementation of the PD technique does indeed
achieve the required performance.
It should be noted that the experimental spectra in Figs. 16
and 17 do show baseband harmonics of up to approximately
0.4%, which are not predicted by theory [3]. These harmonicsare produced by second order effects such as dc bus ripple,
Fig. 17. Experimental phase voltage spectrum, four-level flying capacitor in-verter. PD PWM with state machine decoder.
Fig. 18. Simulated line to line voltage spectrum, four-level CSVPWM.
floating capacitor ripple and dead-time distortion [10], and are
present in any practical inverter.
Figs. 18 and 19 contrast the experimental and simulated
line-to-line voltage spectrum for the CSV method, and again it
is clear that the state machine implementation of the modulatormatches the theoretical result. The suppression of the first
carrier sideband group (clustered around 4.6 kHz) is evident,
when compared to Figs. 15 and 16. This illustrates the major
difference between PD and CSV PWM, in that CSVPWM
suppresses this group at the expense of the second carrier
sideband group (clustered around 9.2 kHz) which results in a
lower net weighted total harmonic distortion (WTHD). This
is further illustrated in Fig. 20, which plots the theoretical
normalized WTHD (NWTHD) for the PSC, PD, and CSV
PWM methods as well as the experimental CSV data, where
NWTHD is defined as
(5)
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MCGRATH et al.: OPTIMAL MODULATION OF FLYING CAPACITOR AND STACKED MULTICELL CONVERTERS 515
Fig. 19. Experimental line to line voltage spectrum, four-level flying capacitor
inverter. CSVPWM with state machine decoder.
Fig. 20. Theoetical PSC, PD, and CSV PWM NWTHD curves, and experi-mental CSV PWM datafour-level flying capacitor Inverter.
is the magnitude of the nth harmonic of the fundamental,
is the magnitude of the fundamental and is the modulation
depth. Again the match between theoretical and experimental
performance is excellent, and the fractional harmonic improve-
ment of CSV over PD PWM by virtue of the suppression of the
first carrier sideband group is clear. However, much more sig-
nificant are the harmonic gains achieved by both CSV and PD
PWM over PSCPWM at higher modulation indexes, as shown
in Fig. 20. The close agreement between the experimental and
theoretical NWTHD results confirms that the state machine im-
plementation preserves the harmonic characteristics of the mod-ulation strategy throughout the entire modulation range.
V. CONCLUSION
This paper explores the implementation of the harmonically
superior PD and CSV PWM techniques to flying capacitor and
SMC converters. Standard PD and CSV PWM are used to se-
lect the target switched voltage for each phase leg, but since
these converters have redundant phase leg voltage states, the
modulator output must then be decoded to select the appro-
priate cell switching state. Previous attempts to do this have
used reduced magnitude trapezoidal carrier waveforms to com-
pare against the phase leg reference waveforms, but this ap-
proach is suboptimal because it incorrectly allocates switching
events as the phase references cross disposition bands. This re-
sults in narrow pulses and uneven distribution of switching tran-
sitions between cells. In this paper, a finite state machine is used
to decode the modulator output to select cell switching transi-
tions on a cyclical fashion, and to account for every possible
switching transition over a complete fundamental cycle. The re-
sulting state machine algorithm is simpler to use than the pre-
vious approach, and is readily implemented on an FPGA device.
Simulation and experimental results are presented to confirm the
spectral performance of the PD and CSV modulators with a state
machine decoder, and verify that the natural capacitor voltage
balancing property of the flying capacitor and SMC converters
is preserved.
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Brendan Peter McGrath (M99) received the B.Sc.degree in applied mathematics and physics and theB.E. degree in electrical and computer systems en-gineering, and the Ph.D. degree in PWM theory formultilevel converters from Monash University, Vic-toria, Australia, in 1997 and 2003, respectively.
After the completion of his Ph.D. degree, he spenttwo years with Creative Power Technologies, Mel-
bourne, Australia, where he was part of a develop-ment team working on auxiliary traction convertersystems and precise utility instrumentation systems.
In 2004, he was a Post-Doctoral Researcher with the Laboratoire d Electrotech-niqueet dElectronique Industrielle (LEEI), Toulouse, France, where he workedon themodulation of multicellconverters.He has just recently joined the facultyat Monash University, Clayton, Australia, after having spent two years at theUniversity of Newcastle, New South Wales, Australia. His principle researchinterests include the modulation and control of multilevel power converters,and the application of signal processing and control theory to power conver-sion systems.
Dr. McGrath received the Douglas Lampard medal from Monash Universityfor his Ph.D. thesis, in 2004. He is a member of the IEEE Power Electronics,Industrial Electronics, and Industry Applications Societies.
Thierry Meynard (M94) received the M.S. degreefrom the Ecole Nationale Suprieure dElectrotech-nique, dElectronique, dHydraulique de Toulouse,Toulouse, France, in 1985 and the Ph.D. degree formthe Institut National Polytechnique de Toulouse,
Toulouse, France, in 1988.Next, he was an Invited Researcher at the Univer-
sit du Qubec Trois Rivires, Canada, in 1989. Hejoined the Laboratoire dElectrotechnique et dElec-tronique Industrielle (LEEI), Toulouse, as a full-timeResearcher in 1990 and was Head of the Static Con-
verterGroup, LEEI, from1994 to 2001. He is currently theDirector of Researchat the LEEI and a part-time Consultant with Cirtem, Labge, France, on a reg-ular basis. His research interests include soft-commutation, series and parallelmulticell converters for high power and high performance applications, and di-rect acac converters.
Guillaume Gateau received the M.S. degree from the Ecole NormaleSuprieure de Cachan, Paris, France, in 1992 and the Ph.D. degree from theInstitut National Polytechnique de Toulouse, Toulouse, France, in 1997.
He joined the Laboratoire dElectrotechnique et dElectronique Industrielle(LEEI), Toulouse, as an Assistant Professor in 1998. His research interests in-clude digital control of power converters, series multicell converters for highpower and high performance applications, and new topologies for high voltagesapplications.
Donald Grahame Holmes (M87SM03) re-ceived the B.S. degree and the M.S. degree inpower systems engineering from the Universityof Melbourne, Melbourne, Australia, in 1974 and1979, respectively, and the Ph.D. degree in PWM
theory for power electronic converters from MonashUniversity, Clayton, Australia, in 1998.
In 1984, he joined Monash University to workin the area of power electronics, and he now headsthe Power Electronics Research Group at this uni-versity. The present interests of this group include
fundamental modulation theory and its application to the operation of energyconversion systems, current regulators for drive systems and PWM rectifiers,active filter systems for quality of supply improvement, resonant converters,current-source inverters for drive systems, and multilevel converters. He has astrong commitment and interest in the control and operation of electrical power
converters. He co-authored a major reference textbook on PWM theory. He haspublished well over 100 papers at international conferences and in professional
journals, and regularly reviews papers for all major IEEE TRANSACTIONS in
his areas of interest.Dr. Holmes is an active member of the Industrial Power Converter and Indus-
trial Drive Committees of the Industrial Applications Society of the IEEE, is amember of the Adcom of the IEEE Power Electronics Society.