02_nios_parallelport

8/12/2019 02_Nios_Parallelport

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Lab_01

1.

Requirement:

Design the System on DEII kit (Altera company) including the following

components.

Nios II Processor

SRAM memory

JTAG BLASTER

Input Parallel Port

Output Parallel Port

Note: Not using the Avalon bus as interface for communication

2. Application:

Students use SWITCHs as the Input Parallel Port to control the LEDRs as the

Output Parallel Port. Besides, the KEY and CLK_50 are used as the reset signal

and clock signal of the system. The application program is embed in to SRAM

device by JTAG BLASTER device.



Basic Step

1/ Create the project:Creating the project named as “soc_parallel_port ” by Quatus Software.



Project Directory

Project Name



FPGA Family

FPGA seri



2/ Create the SOPC system

Students use the SOPC Builder to build the own system including Nios

CPU(integrated in FPGA-CycloneII), SRAM memory (ISSI –

IS61LV25626AL-512KB contains the application source code), JTAG

BLASTER (driver for embed the application source code – C languagefrom PC to FPGA kit-DEII kit), In/Out Parallel Ports(These parallel

ports will be connected to the SW and LEDR).



S stem Name

Choosing devices for system



Now students see 2 tabs: System Contents and System Generation . What

we will do in the System Contents tab and the component we will you

will be list in the Component L ibrary space. For now we will focus on

Processor , I nterface Protocols and University Program trees. Notice the

red squares below.

Open the Processor tree, there is only one option, double click it and it

will bring you the option for your wanted CPU. Click finish, we willconfigure the CPU option later.



In the “Custom Instruction”option, the “Floating Point

“Hardware” & “Interrupt

Vector” components are used



Open the I nter face Protocol tree, open the Serial sub tree and double

click the JTAG UART , click Next, check the first option then finish.

This UART will be the bridge for loading our C/assembler codes into the

Nios system.



The NIOS c u has ust enerated



Open the University Program tree to add the SRAM

Find and open the sub tree Memory , this contains the option for

choosing the memory type for your CPU. For the all labs we mostly

used SRAM option unless mentioned otherwise. Double click it, in

the SRAM option menu, select DE2 and uncheck checkbox then

click finish.



Open the University Program tree to add the Parallel Port

Find and open the sub tree Gener ic I O , this contains the option for

mouse, keyboard… (PS2 port) or using the switches, buttons and led

on nios boards. In lab 1 and 2, we are using Paral lel Por t . Double

click it to open the option menu.

Students have to generate two parallel ports (Port In for SW & Port

Out for LEDR). There are two options such as “Create custom

parallel port” or not to generate these ports. Hence, students should

choose this option to control the corresponding devices.



For Input Parallel Port (SW), 8bit parallel port corresponding to SW

is generated. Specially, if students want to use “Interrupt” prototype

to control the behavior of input ports, the “Edge Capture Register” ischosen. As the result, when the SW (parallel port in)is in rising edge

status, one interrupt event is issued, the interrupt function is called to

solve. This will be clarified in the application source code.

Really, the parallel ports generated automatically or in custommethod are equivalent. The bellow figure is just reference.



After generating the Input Parallel Port inserting the interrupt

function, there is conflict in interrupt priority. Then, the interrupt

priority of Output Parallel Port should be set to 1.

For the Output Parallel Port (LEDR[0-7]), it is generated same as the

Input Parallel Port. Only “Port Direction” is set “Output Only”.

Because this port is output property, this was not inserted theinterrupt function.



Modify the the CPU property

Double click the CPU you created in step 4 to configure it (which

will be called cpu_xx if you has not changed its name). For entire

lab we will using the middle CPU types, the left one is good too.Select Embedded Multiplier option in Hardware Multiply scroll

box, tick the Hardware divide checkbox. In the memory section

below, select your SRAM option, no need to change the offset

option next to it. Click next till you reach this page, double click

the I nterr upt Vector and F loating Hardware to add it into your

CPU. Remember to tick the Use fl oating point division hardware

checkbox when open the Floating Hardware option. If you forgot

it, select the fpoint unit in the next space and click the edit button

below to reconfigure.



Menu bar -> File -> Save.

In the bottom of the program click generate button and wait for

your system to be generated. After that, save the system again.



3/ Develop the top module and compile all system

After generating the SOPC system (soc_lab.v file), “soc_lab.v” file

including many verilog format files is presented as following detail

Students has to create the Verilog project file (soc_parallel_port.v) in

which the Nios system (soc_lab) is included. The name of project file

has to same as the name of project generated last step.

module soc_lab (// global signals:clk_0,reset_n,

// Parallel port out

LEDR_from_the_port_in_ld_sw,

//Parallel port inSW_to_the_port_in_sw_dt,

// SRAM interfaceSRAM_ADDR_from_the_sram_0,SRAM_CE_N_from_the_sram_0,SRAM_DQ_to_and_from_the_sram_0,SRAM_LB_N_from_the_sram_0,

SRAM_OE_N_from_the_sram_0,SRAM_UB_N_from_the_sram_0,SRAM_WE_N_from_the_sram_0

)

;

…………..



module soc_parallel_port (

CLOCK_50, //Clock deviceSW, //SW device

KEY //KEY deviceLEDR, //LEDR device//SRAM deviceSRAM_ADDR,SRAM_CE_N,

SRAM_DQ,SRAM_LB_N,

SRAM_OE_N,SRAM_UB_N,SRAM_WE_N

);input CLOCK_50;input [0:0]KEY;output [7:0]LEDR;

output [17:0] SRAM_ADDR;output SRAM_CE_N;inout [15:0]SRAM_DQ;

output SRAM_LB_N;

output SRAM_OE_N;output SRAM_UB_N;output SRAM_WE_N;

//Cakk the soc_lab instancesoc_lab soc_lab01(

.clk_0(CLOCK_50),

.reset_n(KEY[0]), //Connect the KEY0 to system reset directly

. SW_to_the_port_in_sw_dt (SW[7:0]),

. LEDR_from_the_port_in_ld_sw (LEDR[7:0]),

.SRAM_ADDR_from_the_sram_0(SRAM_ADDR),

.SRAM_CE_N_from_the_sram_0(SRAM_CE_N),

.SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ),

.SRAM_LB_N_from_the_sram_0(SRAM_LB_N),

.SRAM_OE_N_from_the_sram_0(SRAM_OE_N),

.SRAM_UB_N_from_the_sram_0(SRAM_UB_N),

.SRAM_WE_N_from_the_sram_0(SRAM_WE_N));

endmodule



In order to understand the structure, the Verilog knowledge should be

reviewed. Students can image that the structure is presented as thefollowing figure



After develop the Verilog wrap file, students should add the DEII pin list

and compile all system to finish hardware development task.



4/ Create Nios project (build the software Project)

Because the “parallel_port_nios.avi” clip is very clear, the detail of this step isnot presented.

Students only take not e that the software project should be made in the

“software” directory as the flowing figure

The application source file (port.c) is included as the following figure. Theapplication source file example is also supported to help the students understand

how to writing the correct application and how to use the interrupt function.



5/ Evaluate the system

After developing the software project and application source file, the systemshould be embedded to the DEII kit firstly. Next, the source code will be

transferred after that.

Students use the SW and check the LEDR to confirm that the SW controls the

LEDR correctly.



reset n

soc_lab

CLK_50 clk_0

sopc_vga.v

KEY

SRAM_ADDR;

SRAM_CE_N;SRAM_DQ;SRAM_LB_N;

SRAM_OE_N;SRAM_UB_N;

SRAM_WE_N;

Nios cpu

VGASRAM

SRAM_ADDR_from_the_sram_0

SRAM_CE_N_from_the_sram_0

SRAM_DQ_to_and_from_the_sram_0

SRAM_LB_N_from_the_sram_0

SRAM_OE_N_from_the_sram_0

SRAM_UB_N_from_the_sram_0

SRAM_WE_N_from_the_sram_0

VGA_CLK

VGA_HSVGA_VS,VGA_BLAN

VGA_SYNCVGA_R

VGA_GVGA_B

02_nios_parallelport

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