document02

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013 1219

Synchronous-Reference-Frame-Based Control ofSwitched Boost Inverter for Standalone DC

Nanogrid ApplicationsRavindranath Adda, Student Member, IEEE, Olive Ray, Student Member, IEEE, Santanu K. Mishra, Member, IEEE,

and Avinash Joshi

Abstract—Switched boost inverter (SBI) is a single-stage powerconverter derived from Inverse Watkins Johnson topology. Unlikethe traditional buck-type voltage source inverter (VSI), the SBIcan produce an ac output voltage that is either greater or lessthan the available dc input voltage. Also, the SBI exhibits betterelectromagnetic interference noise immunity when compared tothe VSI, which enables compact design of the power converter.Another advantage of SBI is that it can supply both dc and acloads simultaneously from a single dc input. These features makethe SBI suitable for dc nanogrid applications. In this paper, theSBI is proposed as a power electronic interface in dc nanogrid.The structure and advantages of the proposed SBI-based nanogridare discussed in detail. This paper also presents a dq synchronous-reference-frame-based controller for SBI, which regulates both dcand ac bus voltages of the nanogrid to their respective referencevalues under steady state as well as under dynamic load variationin the nanogrid. The control system of SBI has been experimentallyvalidated using a 0.5-kW laboratory prototype of the SBI supplyingboth dc and ac loads simultaneously, and the relevant experimentalresults are given in this paper. The low cross regulation and thedynamic performance of the control system have also been verifiedexperimentally for a 20% step change in either dc or ac load ofSBI. These experimental results confirm the suitability of the SBIand its closed-loop control strategy for dc nanogrid applications.

Index Terms—DC nanogrid, switched boost inverter (SBI),synchronous reference frame (SRF) control.

I. INTRODUCTION

DC NANOGRID is a low-power dc distribution system suit-able for residential power applications [1]–[3]. The aver-

age load demand in the nanogrid is generally met by the localrenewable energy sources like solar, wind, etc. An energy stor-age unit is also required in the nanogrid to ensure uninterruptiblepower supply to the critical loads and to maintain power balancein the nanogrid.

Fig. 1 shows the schematic of a dc nanogrid consisting of asolar panel as an energy source, a storage unit, and some dcand local ac loads. The solar panel is associated with a series-blocking diode DS to avoid reverse power conduction. As the

Manuscript received February 29, 2012; revised May 21, 2012; acceptedJuly 7, 2012. Date of current version October 12, 2012. Recommended for pub-lication by Associate Editor D. Perreault.

The authors are with the Department of Electrical Engineering, Indian Insti-tute of Technology Kanpur, Kanpur 208 016, India (e-mail: [email protected];[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2211039

Fig. 1. Schematic of a dc nanogrid.

dynamic behaviors of all the different units of nanogrid are notuniform, they are interfaced to a common dc bus using powerelectronic converters, as shown in Fig. 1. As per the consumerpreference, each dc load in the nanogrid also has its own powerelectronic interface [1]–[3] which is not shown in Fig. 1 forsimplicity.

In the nanogrid structure of Fig. 1, three different power con-verter stages are used to interface the renewable energy source,energy storage unit, and the local ac loads in the system to thedc bus. This paper proposes a structure of the dc nanogrid us-ing switched boost inverter (SBI) [4]–[6] as a power electronicinterface. Fig. 2 shows the structure of the proposed SBI-baseddc nanogrid, and Fig. 3 shows the circuit diagram of the SBIsupplying both dc and ac loads.

As shown in Fig. 3, the SBI has one active switch (S), twodiodes (Da , Db ), one inductor (L), and one capacitor (C) con-nected between voltage source Vg and the inverter bridge. Alow-pass LC filter is used at the output of the inverter bridge tofilter the switching frequency components in the inverter outputvoltage vAB . As shown in Fig. 3, the capacitor C (connectedbetween node VDC and ground) of SBI acts as a dc bus fordc loads while the capacitor Cf (connected between nodes AO

and BO ) of SBI acts as an ac bus for ac loads. The operatingprinciple and pulsewidth modulation (PWM) control of the SBIhave been explained in Section III of this paper.

Fig. 2 shows structure of the proposed SBI-based dc nanogridwhich has the following advantages when compared to the con-ventional structure [1]–[3]:

1) SBI is a single-stage power converter that can supply bothdc (between node VDC and ground) and ac loads (betweennodes AO and BO ) simultaneously from a single dc input.So, it can realize both the dc-to-dc converter for solar paneland the dc-to-ac converter in a single stage. This decreasessize and cost of overall system.

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1220 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Fig. 2. Structure of the proposed SBI-based dc nanogrid.

Fig. 3. Circuit diagram of SBI supplying both dc and ac loads.

2) The output ac voltage of SBI can be either higher or lowerthan the available source voltage. So, it has wide range ofobtainable output voltage for a given source voltage.

3) SBI exhibits better electromagnetic interference (EMI)noise immunity when compared to a traditional voltagesource inverter (VSI), as the shoot-through (both switchesin one leg of the inverter bridge are turned ON simulta-neously) due to EMI noise will not damage the inverterswitches [4]. This reduces extra burden on the power con-verter protection circuit and helps in realization of com-pact design of the power converter.

4) As the SBI allows shoot-through in the inverter legs, it doesnot require a dead-time circuit and hence eliminates theneed for complex dead-time compensation technologies[9], [10].

This paper presents a structure of the SBI-based dc nanogridand its advantages compared to the conventional structure shownin Fig. 1. This paper also describes the steady-state and small-signal analysis of SBI supplying both dc and ac loads along withits PWM control technique. Also, a closed-loop control strategyof SBI that regulates both the dc and ac bus voltages of SBI totheir respective reference values has been given in this paper.The closed-loop control strategy has also been experimentallyvalidated using a 0.5-kW laboratory prototype of SBI shown inFig. 3.

The organization of this paper is as follows. Section II presentsa review of the SBI and its comparison with the traditional two-stage conversion system. Section III describes the steady-stateoperation of the SBI supplying both dc and ac loads, followed

Fig. 4. (a) Schematic of IWJ topology. (b) Equivalent circuit of IWJ topologyin D·TS interval. (c) Equivalent circuit of IWJ topology in (1 – D)·TS interval.(d) CIWJ topology.

by its PWM control strategy. The small-signal analysis of SBIand design of a closed-loop control system using synchronousreference frame (SRF) approach has been given in Section IV.In Section V, the control strategy has been experimentally val-idated using a 0.5-kW laboratory prototype of SBI controlledusing TMS320F28335 DSP. Section VI presents some conclud-ing remarks of this paper.

Note that in this paper, GS , GS 1 , GS 2 , GS 3 , and GS 4 repre-sent the gate control signals of switches S, S1 , S2 , S3 , and S4 ,respectively, fed through a noninverting gate driver. Lowercaseletters are used to represent the sinusoidal signals and uppercaseletters are used to represent the dc signals. Uppercase letter witha hat (ˆ) represents peak value of a signal, while lowercase let-ter with a hat (ˆ) represents small-signal variation in the signal.Also X is the phasor representation of a sinusoidal signal x. Thesuperscript “∗” is used to represent the reference signals to thecontrol system of dc nanogrid.

II. SWITCHED BOOST INVERTER TOPOLOGY

SBI is a single-stage power converter derived from InverseWatkins Johnson (IWJ) Topology [4]. This topology exhibitsproperties similar to that of a Z-source inverter (ZSI) [7] withlower number of passive components and more active compo-nents. This section presents a review of the approach used toderive the SBI from IWJ topology. A detailed comparison ofSBI with a traditional two-stage dc-to-ac conversion system isalso given in this section.

A. Derivation of SBI From IWJ Topology

The schematic of IWJ converter [26] is shown in Fig. 4(a)and its equivalent circuits in D·TS and (1 – D)·TS intervals of aswitching cycle TS are shown in Fig. 4(b) and (c), respectively.As shown in Fig. 4(b), during D·TS interval, the two switchesof the converter are in position 1, and inductor L is connectedbetween the input and the output. Similarly, during (1 – D)·TS

interval, the switches are in position 0 and the inductor is con-nected between the output and the ground, as shown in Fig. 4(c).

ADDA et al.: SYNCHRONOUS-REFERENCE-FRAME-BASED CONTROL OF SWITCHED BOOST INVERTER 1221

Fig. 5. (a) Realization of CIWJ topology using power semiconductor devices. (b) Connection of a VSI across the dc output node VDC of CIWJ topology.(c) Connection of a VSI across the switching terminal Vi of the CIWJ topology (switch Si can be realized by using the shoot-through state of the VSI).

Interchanging the D·TS (position 1), and (1 – D)·TS (position 0)intervals of IWJ converter leads to Fig. 4(d). This configurationis named as the complementary IWJ (CIWJ) topology in [4].Note that this interchange has no impact on the states of theconverter. However, as far as implementation is concerned, thiswill imply that the controlled switch and diode of CIWJ andIWJ are interchanged.

Fig. 5(a) shows the realization of CIWJ topology using powersemiconductor devices [4], [5]. The output of this converteris a dc voltage VDC . In order to convert this dc voltage to anac voltage, one has to use a VSI. This VSI may be directlyconnected at the output node VDC of CIWJ topology [shownin Fig. 5(b)], which becomes a cascaded connection of a dc–dcconverter and a regular VSI. But this combination cannotovercome the general limitations of a traditional VSI [7], [8],viz., 1) dead-time is necessary to prevent the damage of theswitches in the event of shoot-through in inverter phase legs,2) complex dead-time compensation technologies shouldbe used to compensate the waveform distortion caused bydead-time.

Fig. 5(c) shows another possible connection of the VSI, inwhich the inverter bridge is connected across the switch nodeVi of the CIWJ topology. Note that this combination requiresonly controlled switch S apart from the inverter bridge. Theswitch Si of CIWJ topology can be realized by utilizing theshoot-through state of the inverter bridge. Also, similar to thecascaded connection shown in Fig. 5(b), this circuit can alsosupply a dc load (at the output of CIWJ) and an ac load (atthe output of the inverter bridge) simultaneously from a singledc voltage source Vg . The circuit of Fig. 5(c) is named as SBItopology in [4]. Note that it is not a direct cascade connection ofCIWJ topology and VSI, as the inverter bridge is connected ata switch node of CIWJ converter but not at its output terminal.When compared to the cascaded connection shown in Fig. 5(b),the SBI has following advantages:

1) In the event of shoot-through in any phase leg of the in-verter bridge, the diode Db is reverse-biased and capaci-tor C is disconnected from the inverter bridge. Now, thecurrent through the circuit is limited by the inductor L.So, similar to ZSI, shoot-through does not damage theswitches of the SBI also.

2) As the SBI allows shoot-through, no dead-time is neededto protect the converter. Also this circuit exhibits betterEMI noise immunity compared to a traditional VSI.

3) Since dead-time is not required, there is no need of extradead-time compensation technologies to compensate thewaveform distortion caused by dead-time.

Note that a ZSI [7] also exhibits similar advantages of SBImentioned above. But the SBI achieves these properties withlower number of passive components and more active com-ponents compared to ZSI [4]. This is because the impedancenetwork of ZSI uses two inductors, two capacitors, and a diodeapart from the inverter bridge, while the SBI requires only oneinductor, one capacitor, a controlled switch, and two diodes. Thereduction in number of passive components leads to the reducedsize of the power converter stage. Also ZSI requires passivecomponents with high consistency [7], [8] which is not the casewith SBI. Another major advantage of SBI when compared toZSI is that it can supply both dc and ac loads simultaneouslyfrom a single dc voltage source, as shown in Fig. 3. However,the limitation of SBI is that its peak inverter input voltage isonly (1 – D) times that of ZSI, where D is the shoot-throughduty ratio of the inverter bridge. A more detailed quantitativecomparison of SBI and ZSI is given in [4].

B. Comparison of SBI With a Traditional Two-Stage DC-to-ACConversion System

In the previous section, it is shown that the SBI is a single-input, two-output (one dc output and one ac output) power con-verter derived from IWJ converter and a VSI. Similar to the tra-ditional two-stage dc-to-ac conversion system shown in Fig. 6,the SBI can also generate an ac output voltage that is eithergreater or less than the input dc voltage. However, the SBI hascertain advantages and limitations when compared to the two-stage conversion system shown in Fig. 6, which are discussedbelow.

1) Dead-Time Requirement: A shoot-through event in theinverter bridge of the two-stage conversion system damages thepower converter stage, as well as the dc loads connected to thedc bus of the nanogrid. So a dead-time circuit is necessary tominimize the occurrence of shoot-through events in this system.


Fig. 6. Traditional two-stage dc-to-ac conversion system: Boost converter cascaded with a VSI.

Moreover, to compensate the waveform distortion caused bydead-time, one has to use the complex dead-time compensationtechnologies [8]–[10]. This is not the case with SBI, as it allowsshoot-through in the inverter phase legs. So the use of SBI elim-inates the need for a dead-time circuit as well as the requirementof dead-time compensation technologies.

2) Reliability and EMI Noise Immunity: Even with a dead-time circuit, the probability of a shoot-through event cannot beeliminated completely because an EMI noise can also causeshoot-through in the inverter phase legs [4], [7]. With the use ofSBI, the shoot-through event does not damage the switches ofthe power converter. So, SBI exhibits better EMI noise immu-nity and hence has better reliability compared to the two-stageconversion system.

3) Extreme Duty Cycle Operation: At the extreme duty ratiooperation (e.g., for D ≥ 0.75) of a conventional boost converter,the inductor L is charged over a longer time duration in theswitching cycle, and very small time interval is left to dischargethe inductor through the output diode Db . So this diode shouldsustain a short pulsewidth current with relatively high ampli-tude. Also, this causes severe diode reverse recovery currentand increases the EMI noise levels in the converter [11]–[14].This also imposes a limit on the switching frequency of theboost converter and thus increases the size of the passivecomponents used in the two-stage conversion system shownin Fig. 6.

In case of SBI, the maximum shoot-through duty ratio isalways limited to 0.5 for a positive dc bus voltage VDC [4].So, even when the converter operates at the point of maximumconversion ratio, the conduction time of the diodes Da , Db

of SBI is approximately equal to 50% of the switching timeperiod, which alleviates the problems due to extreme duty ratiooperation of a boost converter. So, SBI can operate at relativelyhigher switching frequencies compared to the traditional two-stage conversion system. This also decreases the size of passivecomponents used in the power converter.

4) Voltage Stress of Switching Devices: Table I comparesthe voltage stress of the semiconductor devices used in the SBIand the two-stage conversion system shown in Fig. 6. Fromthis table, it can be observed that the switch “S” has less voltage

TABLE IVOLTAGE STRESS COMPARISON OF SBI AND TWO-STAGE CONVERSION SYSTEM

stress (VDC – Vg ) in case of SBI. For all other devices, the voltagestress is same for both SBI and the two-stage conversion system.

5) Maximum Conversion Ratio: The maximum conversionratio (VDC/Vg ) of a practical boost converter cannot exceed 3.0(approximately), due to the effects of various nonidealities [26]such as DCR/ESR of the passive components, on-state voltagedrops of the semiconductor devices, etc. This value may slightlyvary depending on the actual values of nonideal elements presentin the converter. Similarly, the rms ac output voltage (vAC (rms))of a single-phase inverter using sinusoidal PWM cannot exceed1/√

2 times the dc link voltage (VDC ) [25], [27] in the linearmodulation range (0 < M < 1), for a low distortion sine waveoutput. So the maximum overall rms ac-to-dc conversion ratio oftwo-stage conversion system shown in Fig. 6 is approximately2.12. This value may still decrease if the effects of nonidealitiesin VSI are taken into consideration.

The rms ac-to-dc conversion ratio of the two-stage conversionratio may be increased slightly by using semiconductor deviceswith very low forward voltage drops and passive componentswith very low ESR/DCR. This enhances the overall cost of thepower converter stage. Another way to increase the conversionratio of the two-stage conversion system is to use high step-up dc-to-dc converters [12]–[14] or the converters with trans-former/coupled inductor [8], [26]. These converters require ad-ditional semiconductor devices and passive components whichincrease the size as well as cost of the power converter stage.

In this paper, it is shown experimentally in Section V thatthe maximum rms ac-to-dc conversion ratio of the SBI is 2,which is comparable to that of a two-stage conversion system.Also, as explained above, SBI has no diode reverse recovery


problems with extreme duty ratio operation. So this conversionratio is possible even at high switching frequency and with betterreliability and EMI noise immunity.

Note that, in this paper, the SBI has been tested with only onePWM control technique proposed in [6], where the maximumvalue of modulation index (M) is limited by the shoot-throughduty ratio (D). However, as the operation of SBI is similar to ZSI,it is possible to extend maximum boost control and maximumconstant boost control techniques of ZSI [15]–[17] to SBI. Thismay help SBI to achieve higher conversion ratios compared tothe two-stage conversion system, without increasing the numberof devices.

6) Number of Control Variables: Similar to a two-stage con-version system, the SBI also has two control variables: Shoot-through duty ratio (D) and the modulation index (M). The dc busvoltage VDC is controlled by D, while ac output voltage of theconverter is controlled by M. However, similar to ZSI [7], thevalue one of these two control variables decides the upper limitof the second control variable of SBI. The mathematical relationbetween D and M depends on the control technique used. Notethat, as mentioned above, it is possible to extend most of thePWM control techniques of ZSI [15]–[17] to control the SBIalso.

7) Number of Devices: As shown in Fig. 3, the SBI requiresfive active switches, six diodes, two inductors, and two capaci-tors for its realization. The two-stage conversion system shownin Fig. 6 uses only one diode (Da ) less compared to the SBI.However, in a dc nanogrid, the input comes from a renewable en-ergy source, e.g., solar panel or fuel cell, which should alwaysbe associated with a series diode to block the reverse powerflow [7], [18], [19]. So the diode Da of SBI can be a part ofthe renewable energy source which eliminates the need for anexternal diode. Thus, the number of devices in both convertersis same.

III. STEADY-STATE ANALYSIS AND PWM CONTROL OF SBISUPPLYING BOTH DC AND AC LOADS

A. Steady-State Analysis of SBI

The circuit diagram of SBI supplying both dc and ac loads isshown in Fig. 3. Fig. 7(a) and (b) shows the equivalent circuitsof SBI during the shoot-through interval D·TS and non-shoot-through interval (1 – D)·TS of the inverter bridge, respectively.As shown in Fig. 7(a), during D·TS interval, the inverter is inshoot-through zero state and switch S is turned ON. The diodesDa and Db are reverse biased as VDC > Vg . In this interval,capacitor C charges the inductor L through switch S and theinverter bridge. So, the inductor current equals the capacitordischarging current minus the dc load current.

During (1 – D) ·TS interval, the inverter is in non-shoot-through state and the switch S is turned OFF. The inverter bridgeis represented by a current source in this interval as shown inthe equivalent circuit of Fig. 7(b). Now, the voltage source Vg

and inductor L together supply power to the dc load, inverter,and the capacitor through diodes Da and Db . The inductorcurrent in this interval equals the capacitor charging currentadded to the inverter input current and the dc load current. Note

Fig. 7. (a) Equivalent circuit of SBI in D·TS interval. (b) Equivalent circuitof SBI in (1 – D)·TS interval. (c) Steady-state waveforms. (d) Transfer (dc–dc)characteristics of SBI.

that the inductor current is assumed to be sufficient enough forthe continuous conduction of the diodes Da , Db for the entireinterval (1 – D)·TS .

Fig. 7(c) shows the steady-state waveforms of the converteroperation for one switching cycle TS with respect to the gatecontrol signal GS of switch S. From Fig. 7(a) and (b), one has

vL (t) =∣∣∣∣vDC(t), if 0 < t < D · TS

Vg − vDC(t), if D · TS < t < TS

(1)

iC (t) =∣∣∣∣−iL (t) − iDC(t), if 0 < t < D · TS

iL (t) − iDC(t) − ii(t), if D · TS < t < TS

(2)

vi(t) =∣∣∣∣0, if 0 < t < D · TS

vDC(t), if D · TS < t < TS .(3)

Using small ripple approximation, (1)–(3) can be rewritten as

vL (t) =∣∣∣∣VDC , if 0 < t < D · TS

Vg − VDC , if D · TS < t < TS

(4)

iC (t) =∣∣∣∣−IL − IDC , if 0 < t < D · TS

IL − IDC − Ii, if D · TS < t < TS

(5)

vi(t) =∣∣∣∣0, if 0 < t < D · TS

VDC , if D · TS < t < TS .(6)

Here, VDC , IL , and IDC are dc components in vDC (t), iL (t),and iDC (t), respectively, and Ii is the current drawn by inverterbridge in (1 − D) · TS interval. Under steady state, the averagevoltage across the inductor and average current through the


capacitor in one switching cycle should be zero. Using volt-second balance, we have

VDC · D + (Vg − VDC) · (1 − D) = 0 ⇒ VDC

Vg=

1 − D

1 − 2D.

(7)Similarly, using charge-second balance, one can write

(−IL − IDC) · D + (IL − IDC − Ii) · (1 − D) = 0

⇒ IL =(

11 − 2D

)· IDC +

(1 − D

1 − 2D

)· Ii. (8)

The average dc link voltage Vi can be calculated as

Vi = 0 · D + VDC · (1 − D) = VDC · (1 − D) . (9)

The expression for conversion ratio (VDC/Vg ) is plotted inFig. 7(d). As shown in the figure, (VDC/Vg ) is unity whenD = 0 and it becomes very high as D approaches 0.5. Note that,similar to a ZSI [7], the shoot-through duty ratio (D) of the SBIalso cannot exceed 0.5 for a positive dc bus voltage, VDC .

B. PWM Control of SBI

The SBI utilizes the shoot-through interval of the H-bridgeto invoke the boost operation. So, the traditional PWM tech-niques of VSI [25], [27] have to be modified to incorporate theshoot-through state, so that they are suitable for SBI. In [6],a PWM scheme for SBI is developed based on the traditionalsine-triangle PWM with unipolar voltage switching [25], [27].This technique has been illustrated in Fig. 8 during positive andnegative half cycles of the sinusoidal modulation signal vm (t)[shown in Fig. 8(a)].

As shown in Fig. 8(b) and (d), during positive half cycleof vm (t) (vm (t) > 0), the gate control signals GS 1 and GS 2are generated by comparing the sinusoidal modulation signalsvm (t), and –vm (t) [shown in Fig. 8(a)] with a high-frequencytriangular carrier vtri(t) of amplitude Vp . The frequency fS ofthe carrier signal is chosen such that fS � fO . Therefore, vm (t)is assumed to be nearly constant in Fig. 8(d). The signals ST1and ST2 are generated by comparing vtri(t) with two constantvoltages VST and –VST , respectively. The purpose of these twosignals is to insert the required shoot-through interval D·TS inthe PWM signals of the inverter bridge. Now the gate controlsignals for switches S3 , S4 , and S can be obtained using thelogical expressions given as follows:

GS3 =GS2 +ST1; GS4 =GS1 + ST2; GS = ST1 + ST2 .(10)

Similarly, as shown in Fig. 8(c) and (e), during negative halfcycle of vm (t) (vm (t) < 0), the gate control signals GS3 andGS4 are generated by comparing the modulation signals –vm (t),and vm (t) with the triangular carrier vtri(t). The shoot-throughsignals ST1 and ST2 are generated in the same manner as inthe positive half cycle. The gate control signals for switches S1 ,S2 , and S can be obtained using the logical expressions given asfollows:

GS1 =GS4 +ST1; GS2 =GS3 + ST2; GS = ST1 + ST2 .(11)

Fig. 8. (a) Sinusoidal Modulation Signals vm (t) and –vm (t). (b) Schematicof the PWM control circuit when vm (t) > 0. (c) Schematic of the PWM controlcircuit when vm (t) < 0. (d) Generation of gate control signals for SBI whenvm (t) > 0. (e) Generation of gate control signals for SBI when vm (t) < 0.


Fig. 9. Closed-loop control architecture of the dc nanogrid.

It can be observed from Fig. 8 that, during positive half cycleof vm (t), the shoot-through signals ST1 , ST2 are logically addedto GS2 , GS1 , respectively, while in negative half cycle of vm (t),these signals are logically added to GS4 , GS3 , respectively. Thistakes care that all four switches of the inverter bridge equallyparticipate in generating the shoot-through interval.

Note that with this PWM control technique, the shoot-throughstate of the inverter bridge will have no effect on the harmonicspectrum of the inverter’s output voltage vAB , if the sum ofshoot-through duty ratio (D) and the modulation index (M) isless than or equal to unity [6], i.e.,

M + D ≤ 1. (12)

If the values of M and D are chosen according to (12), thepeak value of the ac output voltage vAC is given by [6]

VAC =(VAB

)

fundmental= M · VDC = M ·

(1 − D

1 − 2D

)· Vg .

(13)Inequality (12) limits the maximum ac-to-dc conversion ratio

of SBI that can be achieved with this PWM control technique.However, as the operation of SBI is similar to that of a ZSI,it is possible to extend maximum boost control and maximumconstant boost control techniques of ZSI [15]–[17] to SBI. Withthese techniques, the sum of M and D of SBI can be more thanunity. Thus, the SBI can achieve higher ac-to-dc conversionratios with these control techniques.

IV. CLOSED-LOOP CONTROL OF SBI

Fig. 9 shows the closed-loop control architecture of the SBIsupplying both dc and ac loads. In this scheme, the task of thecontroller is to generate gate control signals (GS , GS 1 , GS 2 ,GS 3 , and GS 4) for SBI shown in Fig. 3 such that the volt-ages at the dc bus (VDC ) and the ac bus (vAC ) are regulatedto their respective reference values V ∗

DC and v∗AC . As shown in

Fig. 9, the controller for the dc nanogrid has been implementedin digital domain using Texas Instruments TMS320F28335DSP [30], [31]. This DSP has a built-in 12-bit analog-to-digitalconverter that accepts analog feedback signals (VDC , vAC , and

Fig. 10. Equivalent circuit of SBI referred to ac side (RLf : DCR of theinductor Lf , RAC : ac load).

Fig. 11. Bode plots of (a) inner current control loop and (b) outer voltagecontrol loop.

iLf ) from SBI and converts them into digital domain. Thesefeedback signals along with the reference signals for the ac anddc bus voltages are given as inputs to the controller block. Thecontroller block has two separate control loops for controllingthe dc bus voltage VDC and ac bus voltage vAC . The ac busvoltage controller has a cascaded control structure with an in-ner current control loop and an outer voltage control loop. Notethat, as the ac bus voltage controller is designed using SRF ap-proach [20]–[22], the reference for ac bus voltage v∗

AC is directlygiven in dq domain (V ∗

d ,V ∗q , and frequency ω) in Fig. 9, in order

to reduce the extra computational burden on the DSP.The outputs of the controller block are shoot-through duty

ratio D and modulation signal (m = vm (t)) of the SBI. These are


Fig. 12. Block diagram of the ac bus voltage controller, (a) outer voltagecontroller, and (b) inner current controller.

given as inputs to the enhanced pulsewidth modulation (ePWM)modules [31] of DSP which are the key peripherals to generatethe PWM signals of SBI. Now the gate control signals (GS ,GS 1 , GS 2 , GS 3 , and GS 4) for SBI are generated by the ePWMmodules using the modified unipolar sine-triangle PWM tech-nique of SBI described in the previous section.

A. AC Bus Voltage Controller

Fig. 10 shows the equivalent circuit of SBI referred to the acside, in which the ac load is represented by an equivalent resistorRAC . From this figure, one can write

diLf

dt= −RLf

Lf· iLf +

1Lf

· (vinv − vAC) (14)

dvAC

dt=

1Cf

· iLf − vAC

RAC · Cf. (15)

Equations (14) and (15) can be written in dq domain [20]–[22]as (using the transformation matrix “T” given in (22))

d

dt

[Id

Iq

]=

⎡

⎢⎣−RLf

Lfω

−ω −RLf

Lf

⎤

⎥⎦ ·

[Id

Iq

]+

1Lf

Fig. 13. Simplified equivalent circuit of SBI referred to dc side.

Fig. 14. Bode plots of dc bus voltage control loop.

·[

Vinvd − Vd

Vinvq − Vq

](16)

d

dt

[Vd

Vq

]=

⎡

⎢⎣− 1

RAC · Cfω

−ω − 1RAC · Cf

⎤

⎥⎦ ·

[Vd

Vq

]

+1

Cf·[

Id

Iq

]. (17)

Transforming these equations into s-domain, the control tooutput transfer functions of inner current control loop and outervoltage control loop are given by

Id (s)U ′

id (s)=

Iq (s)U ′

iq (s)=

1s · Lf + RLf

(18)

Vd (s)U ′

vd (s)=

Vq (s)U ′

vq (s)=

RAC

s · RAC · Cf + 1(19)

where

U ′id =Vinvd−Vd +ω · Lf ·Iq ; U ′

iq = Vinvq − Vq − ω · Lf · Id ;

Uvd = Id + ω · Cf · Vq ; and U ′vq = Iq − ω · Cf · Vd.

Fig. 11 shows open-loop (uncompensated) and loop (compen-sated) bode plots of the inner current and outer voltage controlloops with the plant parameters given in Table II. Fig. 12(a) and(b) show the detailed block diagrams of the outer voltage con-troller and inner current controller, respectively. The complete


Fig. 15. Complete Block diagram of the DSP-based controller for the SBI supplying both dc and ac loads.

block diagram of the ac bus voltage control loop is given inFig. 15.

B. DC Bus Voltage Controller

Fig. 13 shows the simplified equivalent circuit of SBI, inwhich the dc load is represented by an equivalent resistor RDC ,and the inverter bridge is represented by parallel combination ofa switch Si and a resistor Ri [24]. Using state-space averagingapproach [26], [27], the small-signal state-space model of theSBI can be obtained as follows:

K. ˙x = A.x + B.u

y = E.x + F.u (20)

where

x =[iL vDC

]T; u =

[d vg

]T;

y = [vDC] ; and K =[

L 00 C

].

The matrices A, B, E, and F of (20) are given in AppendixA. From this state-space model, the control to output transferfunction of the dc bus voltage controller (vDC/d) can be obtainedas

vDC

d=

b1s + b0

a2s2 + a1s + a0. (21)

The coefficients ax (x = 0 to 2) and by (y = 0, 1) of (21) aregiven in Appendix A. Fig. 14 shows the open-loop (uncompen-sated) and loop (compensated) bode plots of the dc bus voltagecontrol loop with the parameters given in Table II. Note thatthe transfer function (vDC/d) of SBI is a nonminimum phasetransfer function with a real zero at s = − (b0/b1) in the righthalf of the s-plane.

C. Complete Block Diagram of the Closed-LoopControl System

Fig. 15 shows the complete block diagram of the closed-loopcontrol system of SBI for dc nanogrid applications. As shownin Fig. 15, the control system has a dc bus voltage controllerthat regulates the dc bus voltage VDC to its reference value V ∗

DC .The output of this controller is the shoot-through duty ratio Dof the SBI. The ac bus voltage controller has a cascaded controlstructure with an inner current controller block and an outervoltage controller block, as shown in Fig. 15. The detailed viewof these two controllers is given in Fig. 12. Note that, as the acbus voltage controller is implemented using SRF approach, thefeedback signals (vAC , iLf ) should also be transformed fromsingle phase (1Φ) to dq domain. This transformation involvesthe following two steps.

Step 1: 1Φ to αβ transformationThe sensed sinusoidal voltage vAC of SBI is passed

through a quadrature signal generator (QSG) that is based onsecond-order generalized integrator (SOGI) [23]. The tuning


TABLE IIPARAMETERS USED FOR EXPERIMENT

TABLE IIICOMPONENTS USED FOR EXPERIMENT

Fig. 16. Photograph of the power stage of SBI.

frequency of the SOGI is set to the input frequency ω, asshown in Fig. 15. The outputs of the SOGI-QSG are two in-quadrature sinusoidal signals vα and vβ such that Vα = VACand Vβ = (−j1).VAC . A similar technique is used to transformthe sensed sinusoidal current iLf into αβ domain, as shownin Fig. 15.

Step 2: αβ to dq transformationIn this step, the sinusoidal signals (vα , vβ ) and (iα , iβ ) are

premultiplied by the transformation matrix, T [21], as given inthe following equation:

[VdVq

]= T ·

[vα

vβ

];

[IdIq

]= T ·

[iαiβ

]

Fig. 17. Gate control signals of SBI generated by the DSP (a) during positivehalf cycle of vm (t) and (b) during negative half cycle of vm (t).

TABLE IVEXPERIMENTAL VERIFICATION OF BUCK–BOOST CAPABILITY OF THE SBI

where T =[

sin θ − cos θcos θ sin θ

]. (22)

Note that as the controller is designed for a standalone system,“θ” is generated by integration of the input frequency “ω,” asshown in Fig. 15. As a result of the transformation given in(22), these sinusoidal signals are transformed into dc signals(Vd , Vq ) and (Id , Iq ), respectively. Now the sensed feedbacksignals are in dq domain and can be given as inputs to the ac


Fig. 18. Experimental results of SBI with different values of rms ac-to-dc conversion ratios and input voltages. (a) Boost mode with Vg = 24 V. (b) Buck modewith Vg = 24 V. (c) Boost mode with Vg = 48 V. (d) Buck mode with Vg = 48 V.

bus voltage controller, as shown in Fig. 15. The outputs of theac bus voltage controller are the modulation signals of the SBIin dq domain, i.e., Md and Mq . From these two dc signals indq domain, the sinusoidal modulation signal, m (= vm (t)) ofSBI can be obtained using dq to 1Φ transformation given in thefollowing equation:

vm (t) = m = Md. sin θ + Mq. cos θ. (23)

The outputs of the controller block (D and m) are given asinputs to the ePWM modules [31] of DSP in order to generatethe gate control signals (GS , GS 1 , GS 2 , GS 3 , and GS 4) forSBI, using the PWM control technique described in the previoussection.

V. EXPERIMENTAL VERIFICATION

A 500-W laboratory prototype of the SBI supplying both dcand ac loads, shown in Fig. 3, is developed to verify the the-oretical analysis given in the paper. Tables II and III list the

parameters and components used for the experimental verifi-cation. Fig. 16 shows the photograph of power stage of theSBI prototype used for experimentation. The closed-loop con-trol strategy has been implemented using the Texas instrumentsTMS320F28335 DSP as mentioned in previous sections.

A. Gate Signals Generated by the DSP

Fig. 17 shows the gate control signals of SBI during positiveand negative half cycles of the modulation signal vm (t), gener-ated using TMS320F28335 DSP. It can be observed that thesegate signals are consistent with the PWM control signals givenin Fig. 8(d) and (e).

B. Verification of Buck–Boost Capability of SBI

One of the main advantages of SBI over the traditional VSI isthat it can generate an ac output voltage that is either higher orlower than the source voltage Vg . To verify this experimentally,


Fig. 19. Steady-state operation of SBI (a) input voltage Vg , dc load voltageVDC , ac output voltage of SBI vAC , and ac load voltage, and (b) dc load voltageVDC , switch node 1 voltage Vsn1 , input voltage of the inverter bridge Vi , andoutput voltage of H-Bridge VAB .

TABLE VCOMPARISON OF ACTUAL VOLTAGES OF THE SBI IN FIG. 19(a) WITH THEIR

REFERENCE SIGNALS (N = 5)

the SBI has been tested for different conversion ratios and inputvoltages given in Table IV, and the corresponding experimentalresults are given in Fig. 18. From these results, it is clear that

the rms ac-to-dc conversion ratio can vary between 0.5 and 2.This verifies the buck–boost capability of the SBI.

Note that, in this paper, the SBI has been tested with thePWM technique proposed in [6], where the maximum value ofmodulation index M is limited by the shoot-through duty ratioD [see inequality (12)]. However, as the operation of SBI issimilar to ZSI, it is possible to extend most of the PWM controltechniques of ZSI [15]–[17] to SBI. These techniques help tofurther improve the rms ac-to-dc conversion ratio of the SBI.

C. Operation of SBI With an Isolation Transformer

Most of the residential and commercial ac loads require either110 V or 230 V rms ac supply. In order to generate 230-VACoutput using SBI, one can either increase input voltage level to120 VDC (since the maximum practical rms ac-to-dc conversionratio of SBI is 2 with the PWM technique used in this paper) oruse a step-up transformer at the ac output of the SBI. The use oftransformer also provides galvanic isolation between the powerconverter stage and loads, which increases protection level andreliability of the system.

In the previous section (see Fig. 18 and Table IV), it is alreadyshown that both the dc and ac output voltages of SBI can beincreased by increasing the input voltage Vg . In this section, theoperation of SBI has been tested with an isolation transformerconnected between the ac output and the ac load of the converter.This section also verifies the capability of SBI to supply both dcand ac loads simultaneously.

Fig. 19(a) shows the steady-state waveforms of the SBI sup-plying a 250-W dc load and a 250-W ac load simultaneously,with an input voltage Vg = 48 V. The ac load is isolated fromthe power converter stage using a 1:5 isolation transformer. Thereference signals for the closed-loop control system of SBI areV ∗

DC = 130 V, v∗AC = 46 V (rms), V ∗

d = 65 V, V ∗q = 0 V, and

ω = 100π rad/s. Note that the reference value for vAC is chosensuch that the ac load voltage is equal to 230 V rms (=5 × 46 V).Table V compares the actual voltages at various nodes of theSBI with their respective reference values. From Fig. 19(a) andTable V, it is clear that the actual voltages are matching wellwith their respective reference signals. These results verify theoperation of SBI with an isolation transformer at the ac outputof the converter. Also these results show that the SBI can supplyboth dc and ac loads simultaneously from a single input Vg .Fig. 19(b) shows the dc bus voltage VDC , switch node voltageVsn1 , inverter input voltage Vi , and inverter output voltage VABof the SBI. It is important to note that as the VSI is connectedat the switch node Vi of the CIWJ topology, the input voltageof the inverter bridge Vi in SBI is a switching waveform thatvaries from 0 to VDC . Also, it can be observed from Fig. 19(b)that the width of the shoot-through interval (when Vsn1 = VDC ,Vi = 0) is less than the width of zero-interval (when vAB = 0)which proves that inequality (12) is satisfied.

D. Performance of the Closed-Loop Control System With a StepChange in the Load

To test the dynamic performance of the closed-loop controlsystem, a 20% step change has been applied in both ac and dc


Fig. 20. Performance of the controller with (a) 20% step-down change in ac load current, (b) 20% step-up change in ac load current, (c) 20% step-down changein dc load current, and (d) 20% step-up change in dc load current.

loads of SBI separately, and the results are presented in Fig. 20.In all these figures, the signal shown in channel 1 (orange)represents the ac or dc load current. It can be observed from thesefigures that both the dc bus and ac bus voltages are maintainedto be constant by the closed-loop controller even during a stepchange in either ac load or dc load. This confirms that the DSP-based closed-loop control system presented in this paper showsexcellent dynamic performance as well as low cross regulationof ac and dc bus voltages of SBI.

E. Performance of SBI With an RL and Rectifier Loads

Fig. 21(a) shows the experimental results of SBI supplying anRL load: (18+j14) Ω, 125 W, 0.8 pf lag. As shown in Fig. 21(a),with an input voltage Vg of 48 V, the SBI generates a dc busvoltage of 150 V and an output ac voltage vAC of 60 V rms.Channel 1 (Orange) shows the ac load current iAC of SBI. Itcan be observed from this figure that the ac load current lags

the load voltage, which is the characteristic of an RL Load. Thisverifies the performance of SBI with RL loads.

Fig. 21(b) shows the experimental results of SBI supplying asingle-phase diode bridge rectifier with RC load: 150-Ω resistorin parallel with a 470-μF capacitor. Channel 1 (Orange) showsthe current iAC drawn by the rectifier bridge from SBI, andChannel 3 (Pink) shows the output voltage of the rectifier bridgeVRect . It can be observed that the output ac voltage vAC ofSBI is distorted due to the harmonics in the current drawn byrectifier. Note that this distortion happens even with a regularVSI supplying a rectifier load [28], [29]. However, it is possibleto improve the quality of output voltage by modifying the closed-loop control technique of the inverter [28], [29].

VI. CONCLUSION

This paper presents a novel power electronic interface calledswitched boost inverter (SBI) for dc nanogrid applications. It is


Fig. 21. (a) Experimental results of SBI supplying an RL load. (b) Experi-mental results of SBI supplying a rectifier load.

shown that the SBI is a single-stage power converter that cansupply both dc and ac loads simultaneously from a single dcinput. It is also proven that the SBI can generate an ac outputvoltage that is either higher or lower than the available sourcevoltage. This paper also describes the advantages and limitationsof SBI when compared to the ZSI and the traditional two-stagedc-to-ac conversion system. The steady-state and small-signalanalysis of the SBI supplying both dc and ac loads, and a PWMcontrol technique suitable for SBI are also described in thispaper. Also, the analysis and design of a SRF-based controllerthat regulates both the dc and ac bus voltages of SBI to theirrespective reference values has been discussed in this paper.The steady state and dynamic performance as well as the lowcross regulation of the closed-loop control strategy have beenexperimentally validated using a 0.5-kW laboratory prototypeof SBI supplying both dc and ac loads. The performance of SBIhas been tested experimentally with an isolation transformer and

also with three different types of ac loads: R, RL, and nonlinearloads. It can be concluded from the experimental results thatthe control strategy of SBI shows excellent performance duringsteady state as well as during a step change in either dc or ac loadin the system. These results confirm the suitability of SBI andits closed-loop control strategy for dc nanogrid applications.

APPENDIX A

The matrices A, B, E, and F in (20) are

A =

⎡

⎣0 2D − 1

1 − 2D − D

RDC− 1 − D

Req

⎤

⎦

B =

[2 · VDC − Vg 1 − D

VDC ·(

1R e q

− 1RD C

)− 2 · IL 0

]

E = [ 0 1 ] ; F = [ 0 0 ] ; and Req =RDC · Ri

RDC + Ri.

The coefficients of (vDC/d) in (21) are given by

a0 = RDC · Req · (2D − 1)2

a1 = L · (D · Req + (1 − D) · RDC)

a2 = C · L · RDC · Req

b0 = −RDC · (2D − 1) · (2VDC − Vg ) · Req

b1 = −L · (VDC · (Req − RDC) + 2 · IL · RDC · Req) .

REFERENCES

[1] D. Boroyevich, I. Cvetkovic, D. Dong, R. Burgos, F. Wang, and F. C. Lee,“Future electronic power distribution systems—A contemplative view,”in Proc. 12th IEEE Int. Conf. Optim. Electr. Electron. Equip., May 2010,pp. 1369–1380.

[2] J. Schonberger, R. Duke, and S. D. Round, “DC-bus signalling: A dis-tributed control strategy for a hybrid renewable nanogrid,” IEEE Trans.Ind. Electron., vol. 53, no. 5, pp. 1453–1460, Oct. 2006.

[3] H. Kakigano, Y. Miura, and T. Ise, “Low-voltage bipolar-type DC micro-grid for super high quality distribution,” IEEE Trans. Power Electron.,vol. 25, no. 12, pp. 3066–3075, Dec. 2010.

[4] S. Mishra, R. Adda, and A. Joshi, “Inverse Watkins-Johnson topologybased inverter,” IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1066–1070, Mar. 2012.

[5] S. Upadhyay, S. Mishra, and A. Joshi, “A wide bandwidth electronicload,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 733–739, Feb. 2012.

[6] R. Adda, S. Mishra, and A. Joshi, “A PWM control strategy for switchedboost inverter,” in Proc. 3rd IEEE Energy Convers. Congr. Expo., Phoenix,AZ, 2011, pp. 4208–4211.

[7] F. Z. Peng, “Z-source inverter,” IEEE Trans. Ind. Appl., vol. 39, no. 2,pp. 504–510, Mar./Apr. 2003.

[8] Y. Zhou and W. Huang, “Single-stage boost inverter with coupled induc-tor,” IEEE Trans. Power Electron., vol. 27, no. 4, pp. 1066–1070, Apr.2012.

[9] L. Chen and F. Z. Peng, “Dead-time elimination for voltage source in-verters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 574–580, Mar.2008.

[10] S. H. Hwang and J. M. Kim, “Dead-time compensation method voltage-fed PWM inverter,” IEEE Trans. Energy Convers., vol. 25, no. 1, pp. 1–10,Mar. 2010.

[11] F. Gao, P. C. Loh, R. Teodorescu, and F. Blaabjerg, “Diode-assisted buck–boost voltage-source inverters,” IEEE Trans. Power Electron., vol. 24,no. 9, pp. 2057–2064, Sep. 2009.

[12] A. A. Fardoun and E. H. Ismail, “Ultra step-up DC–DC converter withreduced switch stress,” IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025–2034, Sep./Oct. 2010.


[13] E. H. Ismail, M. A. Al-Saffar, and A. J. Sabzali, “High conversion ratioDC–DC converters with reduced switch stress,” IEEE Trans. CircuitsSyst. I, Reg. Papers, vol. 55, no. 7, pp. 2139–2151, Aug. 2008.

[14] Q. Zhao and F. C. Lee, “High-efficiency, high step-up DC–DC converters,”IEEE Trans. Power Electron., vol. 18, no. 1, pp. 65–73, Jan. 2003.

[15] P. C. Loh, D. Vilathgamuva, Y. S. Lai, G. Chua, and Y. Li, “Pulse-widthmodulation of Z-source inverters,” IEEE Trans. Power Electron., vol. 20,no. 6, pp. 1346–1355, Nov. 2005.

[16] F. Z. Peng, M. Shen, and Z. Qian, “Maximum boost control of the Z-sourceinverter,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 833–838, Jul.2005.

[17] M. Shen, J. Wang, A. Joseph, F. Z. Peng, L. M. Tolbert, and D. J. Adams,“Constant boost control of the z-source inverter to minimize current rippleand voltage stress,” IEEE Trans. Ind. Appl., vol. 42, no. 3, pp. 770–778,May/Jun. 2006.

[18] Y. Huang, M. Shen, F. Z. Peng, and J. Wang, “Z-source inverter forresidential photovoltaic systems,” IEEE Trans. Power Electron., vol. 21,no. 6, pp. 1776–1782, Nov. 2006.

[19] R. J. Wai, C. Y. Lin, R. Y. Duan, and Y. R. Chang, “High-efficiency DC-DC converter with high voltage gain and reduced switch stress,” IEEETrans. Ind. Electron., vol. 54, no. 1, pp. 354–364, Feb. 2007.

[20] U. A. Miranda, M. Aredes, and L. G. B. Rolim, “A DQ synchronousreference frame current control for single-phase converters,” in Proc. 36thIEEE Power Electron. Specialists Conf. (PESC), Recife, Brazil, Jun. 2005,pp. 1377–1381.

[21] B. Crowhurst, E. F. El-Saadany, L. El Chaar, and L. A. Lamont, “Single-phase grid-tie inverter control using DQ transform for active and reactiveload power compensation,” in Proc. IEEE Int. Conf. Power Energy, KualaLumpur, Malaysia, Nov./Dec. 2010, pp. 489–494.

[22] P. Rodriguez, R. Teodorescu, I. Candela, A. Timbus, M. Liserre, andF. Blaabjerg, “New positive-sequence voltage detector for grid synchro-nization of power converters under faulty grid conditions,” in Proc. 37thIEEE Power Electron. Spec. Conf., Jeju, Korea, Jun. 2006, pp. 1–7.

[23] M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “A new single-phase PLLstructure based on second order generalized integrator,” in Proc. 37thIEEE Power Electron. Spec. Conf., Jeju, Korea, Jun. 2006, pp. 1–6.

[24] J. Liu, J. Hu, and L. Xu, “Dynamic modeling and analysis of Z sourceconverter-derivation of AC small signal model and design-oriented anal-ysis,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1786–1796, Sep.2007.

[25] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Con-verters: Principles and Practice. Piscataway, NJ: IEEE Press, 2003.

[26] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics,2nd ed. Norwell, MA: Kluwer, Jan. 2001.

[27] N. Mohan, T. Undeland, and W. Robbins, Power Electronics: Converters,Applications and Design, 2nd ed. New York: Wiley, 1995.

[28] K. Selvajyothi and P. A. Janakiraman, “Reduction of voltage harmonicsin single phase inverters using composite observers,” IEEE Trans. PowerDel., vol. 25, no. 2, pp. 1045–1057, Apr. 2010.

[29] Z. Yao and L. Xiao, “Control of single-phase grid-connected inverterswith nonlinear loads,” IEEE Trans. Ind. Electron., 2012, to be published.doi:10.1109/TIE.2011.2174535.

[30] Texas Instruments (2012, May), TMS320F28335 Digital Signal Con-troller (DSC): Data Manual [Online]. Available: http://www.ti.com/lit/ds/symlink/tms320f28335.pdf

[31] Texas Instruments (2009, Jul.), TMS320×2833x, 2823x Enhanced PulseWidth Modulator (ePWM) Module Reference Guide [Online]. Available:http://www.ti.com/lit/ug/sprug04a/sprug04a.pdf

Ravindranath Adda (S’11) received the B.E. degreefrom Andhra University, Vishakhapatnam, India, in2007, and the M.Tech. degree from the Indian Insti-tute of Technology Kanpur, Kanpur, India, in 2009,both in electrical engineering, where he is currentlyworking toward the Ph.D. degree in the Departmentof Electrical Engineering.

His research interests include power electronicsfor dc distribution systems, pulsewidth modulationcontrol techniques of inverters, and digital control inpower electronics.

Olive Ray (S’12) received the B.E.E. degree fromJadavpur University, Kolkata, India, in 2009, theM.Tech. degree from the Indian Institute of Tech-nology Kanpur, Kanpur, India, in 2011, both in elec-trical engineering, where he is currently working to-ward the Ph.D. degree in the Department of ElectricalEngineering.

His research interests include converter modelingand control, dc distribution systems, and digital con-trol in power electronics.

Santanu K. Mishra (S’00–M’04) received theB.Tech. degree in electrical engineering from the Col-lege of Engineering and Technology, Bhubaneswar,India, in 1998, the M.Tech. degree in energy systemsengineering from the Indian Institute of TechnologyChennai, Chennai, India, in 2000, and the Ph.D. de-gree from the Department of Electrical and ComputerEngineering, University of Florida, Gainesville, in2006.

He worked as a Senior and Staff Application Engi-neer with the International Rectifier Corporation from

2004 to 2008. He is currently an Associate Professor at the Indian Institute ofTechnology Kanpur, Kanpur, India. His research interests include server powersystem, low-voltage power conversion, and converter modeling and control.

Avinash Joshi received the Ph.D. degree in electricalengineering from the University of Toronto, Toronto,ON, Canada, in 1979.

He is currently a Professor of electrical engineer-ing at the Indian Institute of Technology Kanpur,Kanpur, India. From 1970 to 1973, he was with theGeneral Electric Company of India Ltd., Calcutta,India. His research interests include power electron-ics, circuits, digital electronics, and microprocessorsystems.

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