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EE201: Digital Circuits and Systems 1 Combinatorial Logic page 1 of 39 EE201: Digital Circuits and Systems Section 1 - Combinatorial Logic 1.1 Encoders: Definition An encoder produces a digital code which depends on which one of its input is activated I 0 Enc I 1 I 2 O 0 O 1 O N-1

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EE201: Digital Circuits and Systems

1 Combinatorial Logic

page 1 of 28

EE201:Digital Circuits and Systems

Section 1 - Combinatorial Logic

1.1 Encoders:

Definition

An encoder produces a digital code which depends on which one of its input is activated

Only one of M inputs is activated at a time

Encoder outputs a N-bit output code

Always: 2N ( M

Example

4-Line to Binary Encoder:

4 inputs

2 outputs

The logic diagram can be generated using formal methods:

Y = D + C

Similarly:

X = D + B

Application

Decimal to BCD Encoder:

10 inputs 4 outputs

1.2 Decoders:

Definition

An decoder activates only one of its outputs depending on the binary code provided as input

Decoder receives a N-bit input code

Only one of M outputs is activated at a time

Always: 2N ( M

Example

Binary to 4-Line Decoder:

2 inputs

4 outputs

The logic diagram can be generated using formal methods:

_ _

_

_

A = X Y,B = X Y,C = X Y,D = X Y

Implementation

Application 1

BCD to Decimal Decoder:

4 inputs 10 outputs

Implementation

Application 2

BCD to 7-segment Decoder:

Horizontal segments: a, c, f

a

=>

0, 2, 3, 5, 6, 7, 8, 9

c

=>

2, 3, 4, 5, 6, 8, 9

f

=>

0, 2, 3, 5, 6, 8, 9 Minimisation

a

AB/CD00011110

001011

010111

11XXXX

1011XX

Equation

Minimisation

c

AB/CD00011110

000011

011101

11XXXX

1011XX

Equation

Minimisation

fAB/CD00011110

001011

010101

11XXXX

1011XX

Whats missing?

Equation

Implementation (a segment)

Implementation (with NAND gates)

1.3 Multiplexers:

Definition

A multiplexer selects one of its inputs to direct to the output depending on the binary code provided at the select inputs

Multiplexer receives a M-bit selection code

Only one of N inputs is directed at the output

Always: 2M = N

Example 1

Two-channel Multiplexer

2 inputs

1 select input

1 output

The logic diagram can be generated using formal methods and minimising, it results:

_

Z = A S + B S

Implementation???Example 2

Two-channel two-bit Multiplexer

4 inputs

1 select input

2 outputs

After minimisation, results:

_

_

Z0 = A0 S + B0 S

Z1 = A1 S + B1 S

Implementation Homework: implementation using gates!Example 3

Four-channel Multiplexer

4 inputs

2 select input

1 output

We have:

_ _

_ _

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0

Implementation Homework: implementation with 2-channel MUXExample 4

Eight-channel Multiplexer

8 inputs

3 select input

1 output

We have:

_ _ _ _ _

Z = I0 S2 S1 S0 + I1 S2 S1 S0 + + I7 S2 S1 S0

Homework: implementation with 2-channel MUX Homework: implementation with logic gatesApplications

Data selection, data routing, parallel to serial conversion, waveform generation, logic function generation, etc.Application 1

Parallel to serial conversion:

4 inputs 1 output 4-bit Register 2-bit Counter 4-channel Mux 1 serial line

The Register contains parallel data 2-bit Counter generates S1 and S2 At every Clock, a different input of the 4:1 line Mux is outputted on the Serial line: X0, X1, X2, X3Application 2

Logic function generator:

E.g. 1

Original function:

Full form:

4-channel Multiplexer:

Matching data and select inputs:

Notes:

There are other ways of implementing the same function by matching different input variables on the select inputs of the MUX In general the number of select lines needed is equal to the number of input variables minus 1 (there are also exceptions: see next) Homework:

Implement F in another way using 4-channel MUX

Implement F using 2-channel MUX

Implement F using logic gates

Implement F using NAND logic gates

E. g. 2

Original function:

Partial form:

4-channel Multiplexer:

Matching data and select inputs: Note: normal implementation would have required a 16-channel MUX

E. g. 3

Original function:

Implement F using 16-channel MUX Factorised function:

Implement F using 4-channel MUX Can you reduce it further if you had 2-ch MUX?

1.4 Demultiplexers:

Definition

A demultiplexer transfers its input to one of the outputs depending on the binary code provided at the select inputs

Demultiplexer receives a M-bit selection code

The input is directed to one of the N outputs

Always: 2M = N

Example 1

Two-channel Demultiplexer

1 input

1 select input 2 outputs implementation using logic gates

Example 2

Eight-channel Demultiplexer

1 input

3 select inputs 8 outputApplication

4-bit/4-word Serial Data Transmission System: The circuit serially transmits four 4-bit words stored in registers A, B, C and D to registers W, X, Y and Z

Initially all Counters are RESET to 0

16 clock pulses are applied on the Clock line

First clock determines such a select input combination at MUX that the first bit from register A is outputted to the serial line

The same clock determines such a select input combination at DMUX that the incoming bit on the serial line will be directed and stored in register W Next clock triggers the transmission of bit 2 from register A and its storage in bit 2 of register W, etc.

Each clock determines a SHIFT of bits in the registers

Therefore clock five determines the transmission of bit two from register B and its storage into bit two of register X, etc.

ON-1

I2

I1

I0

Enc

InputsOutputsABCDYX100000010001001010000111

O1

O0

Y

AB/CD0001111000X1X1010XXX11XXXX100XXX

X

Y

D

C

B

Enc

A

S0S1S2S3S4S5S6S7S8S9B0B1B2B310000000000000010000000000010010000000001000010000000011000010000001000000010000010100000010000110000000010001110000000010100000000000011001

B0

S1

S9

O0

B3

Enc

S0

Dec

O1

O2

OM-1

I0

I1

IN-1

A

Dec

B

C

X

Y

D

InputsOutputsXYABCD001000010100100010110001

A

X/Y01010100

B3

S9

B2

Dec

S0

B0B1/B2 B30001111000100001000011XXXX1000XX

ABCDNo.Segments00000a, b, d, e, f, g00011b, g00102a, b, c, e, f00113a, b, c, f, g01004b, c, d, g01015a, c, d, f, g01106a, c, d, e, f, g01117a, b, g10008a, b, c, d, e, f, g10019a, b, c, d, f, g1010X-1011X-1100X-1101X-1110X-1111X-

InputsOutputsB0B1B2B3S0S1S2S3S4S5S6S7S8S900001000000000000101000000000010001000000000110001000000010000001000000101000001000001100000001000011100000001001000000000001010010000000001

B1

S0

B0

Z

a

b

c

d

e

f

g

Mux

I1

Dec

A

B

C

D

I0

S0 S1 SM

Z

S

Mux

InputsSelectOutputABSZ00000010010001111001101011011111

IN-1

EMBED Visio.Drawing.11

EMBED Visio.Drawing.11

S

A

B

SelectOutputSZ1Z00A1A01B1B0

Mux

Z0

A1

B0

EMBED Visio.Drawing.11

A0

B1

Z1

Z

Mux

I1

I2

I0

I3

S0

S1

S1S0Z100I001I110I211I3

EMBED Visio.Drawing.11

S2S1S0Z1000I0001I1010I2011I3100I4101I5110I6111I7

Z

Mux

I1

I6

I0

I7

S0

S2

S1

SO0O10I010I

EMBED Visio.Drawing.11

EMBED Visio.Drawing.11

Is Mod-8 Counter correct?

IM

_1157713431.unknown

_1157968394.unknown

_1296026056.unknown

_1326705848.unknown

_1326705991.unknown

_1326705779.unknown

_1157968955.vsd1

B0

B1

B2

B3

So

S1

S2

S3

S4

S5

S6

S7

S8

S9

_1157714232.unknown

_1157733805.unknown

_1157745995.vsd1

I

S0

S1

S2

O0

O1

O2

O3

O4

O5

O6

O7

_1157968257.unknown

_1157745663.vsd1

O0

I

O1

S

_1157732529.unknown

_1157713439.unknown

_1157576222.vsd1

X

Y

A

B

C

D

_1157588145.vsdA

B

C

D

a

_1157612502.vsdI0____S1____S0

I1____S1

S0

I2

S1____S0

I3

S1

S0

Z0

_1157708687.unknown

_1157610675.vsdtext

2-channelMUX

2-channelMUX

A0

A1

B0

B1

Z0

Z1

S

_1157587526.vsd1

A

B

C

D

a

_1129133191.unknown

_1157570473.vsdB

A

C

D

X

Y

_1129244705.unknown

_1129133019.unknown


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