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CMO S CIRCUIT DESIGN OF THRESHOLD GATES WITH HYSTERESISGerald E. Sobelman, Karl Fant

Theseus Logic, Inc.1080 Montreal Ave., Suite 20 0St. Paul, MN 55116, USAsobelman@theseus.com, ant@theseus.com

ABSTRACTM-of-N threshold gates with h ysteresis form a class ofcircuit elements that have important application inNULL Convention Logic ", a novel asynchronous logicdesign methodology. General design guidelines for theseM-of-N gates are presented using C MOS technology.Three types o f circuit implementations are discussed:static, semi-static and dynamic. In addition,initialization technique s are presented for use inestablishing a known initial state.

1. INTRODUCTIONThe clocked synchronous paradigm is currently thedominant design methodology for digital systems.While this approach has enjoyed great success over manydecades, limitations and drawbacks of the methodologyexist. For example, the need for precise distribution ofhigh-speed clocks over a large chip area is complex andthe clock tree itself dissip ates a significant fraction of thetotal power consumption. Also, the need to m eet criticalpath constraints requires a complex timing analysisbased on w orst-case design w here the performance islimited by the edges of the sp ecified process, temperatureand voltage ranges. These problems become more severeas device sizes continue to shrink and as clockfrequencies continue to rise.Asynchronous design techniques have been proposed asan alternative to the clocked system methodology, andthe subject has a long history [11. These appro aches seekto overcome the above limitations by dispensing withthe clock and using self-timed signaling to control thesequencing of computations in the system. W hile muchresearch has been devoted to this area, no asynchronousapproach has yet managed to gain a strong foothold inthe design commu nity. Most of these approaches arethemselves highly complex and difficult to d esign. Also,their claimed advan tages have, for the most part, notbeen sufficiently compelling for designers to consid eradopting a major change in their existing methodology.NU LL Convention Logic'" (NCL '") is a new clock-free,delay-insensitive logic design methodology [2 ,3] fordigital systems. Unlike previous asynchronous designapproach es, NCL circu its are very easy to design andanalyze. In NCL, a circuit consists of an interconnectionof primitive modules known as M-of-N threshold gateswith hysteresis. All functional blocks, including both

combinational logic and storage elements, areconstructed out of these same primitives. The designersimply specifies an interconnectio n of library modules inorder to obtain a desired computational functionality.The circuit operates at the m aximum speed of theunderlying semiconductor device technology.In this paper, we will describe the transistor-level desig ncriteria for CMO S im plementations of the M-of-N gates.In section 2, the d esired threshold and hysteresisbehavior are explained. Then, in sections 3 - 5, varioustypes of CMO S circuit implementations are presented.Initialization technique s are discussed in section 6.Finally, the results are summarized in section 7.2. BEHAVIOR OF THRESHOLD GATES WITHHYSTERESIS

The primitive element that we consider is an M-of-Nthreshold gate with hysteresis, which w e refer to assimply an M-of-N gate. The abstract symbol for an M-of-N gate is shown in Figure 1. The cases of interest arethose where M sN. An M-of-N gate is a generalizationof both a Muller C-element [4] and a Boolean OR gate.Specifically, for N > 1, an N-of-N gate corresponds to anN-input Muller C-elemen t. On the other hand, a 1-of-Ngate corresponds to an N-input Boolean OR gate. Thecases where both M > 1 and M

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have been established . In the case of a transition toDATA , the output remains at NULL until at least M ofthe N inputs become DATA. In the case of a transitionto NULL, the output remains at DATA until all N of theinputs become NUL L.In the following sections, we will dem onstrate how thisdesired abstract behavior is implemented using static,semi-static and dynam ic CM OS circuits. The propertiesof each implem entation are pointed out.

3. STATIC IMPLEMENTATIONThe general structure of a static M-of-N threshold gatewith hysteresis is shown in Figure 2.

l;$-&bZ

DATADATA

Figure 2. General structure of a static CMO S M-of-N gate.For any M-of-N gate, the Go to NULL and Hold DATAblocks are complementary to each other and have theuniversal forms shown in Figure 3.

A1 A2 A3 ANb d b

Figure 3. Universal blocks within the staticCM OS M-of-N gate.From these topologies, it is clear that the Go to NULLblock is only ON when all N inputs are 0. Also, theHold DATA block is ON if one or more of the inputs are1. Because of the series chain in the G o to NULL block,speed considerations will limit these structures to amaximum number of inputs, typically N 5 6 . Thresholdgates with higher values o f N can be synthesized using amulti-level tree of small-N gates.Similarly, the G o to DATA and Hold NULL arecomp lementary to each other, but their precise structuresdepend on the particular values ofM and N. It issimplest to begin with the special case where M = N.The general structure of a static N-of-N gate is shown inFigure 4.As no ted earlier, this structure has been knownin the literature as an imp lementation of Muller C -elements [4].

A2+

: I 4 A 2 4 * * ' A N AAN-+; '9Figure 4. General structure of a static CMO S N-of-N gate.For analy sis of its operation, begin with the situationwhere all N inpu ts are 0. In this case, the G o to NULLand Hold NULL blocks are ON and Z goes low, so thatall of the PMOS transistors in the pull-up network (notcounting the inv erter) are ON . At the same time, the Goto DATA and Hold DATA blocks are OFF, and all ofthe NMOS transistors in the pull-down network (notcounting the inverter) are OFF. If one of the inputs goesto 1, the Go to NULL block tums OFF and the HoldDATA block tums ON. How ever, the Z output does notchange because the Hold NULL block, which remainsON, maintains a connection between the intermediatenode and VDD. It is only when all N of the inputs go to1 that the output can change. At that point, the HoldNULL block tums OFF and the Go to DATA blocktums ON , forcing the Z output to DATA. We then reacha situation when all of the PM OS transistors in the pull-up network (not counting the inverter) are OFF and all ofthe NMOS transistors in the pull-down network (notcounting the inverter) are ON. Because o f the symm etryof the circuit, a similar set of actions will occur for thetransition of the output back to NU LL.In the cases where M < N, the topologies of the Go toDATA and Hold NULL blocks must be determined foreach case. As an exam ple, a 2-of-3 gate having inputs A,B and C is shown in Figure 5.-

6Figure 5. Static 2-of-3 gate.

Note first that the G o to NULL and Hold DATA blocksassum e their standard forms. The forms for the other twoblocks may be obtained by the following analyticalprocedure. First, begin with the Go to DATA block.This should turn ON when any 2 of the 3 inputs gohigh. The switching expression for this condition is asfollows:

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f = AB + BC + C A = A B + C(A + B)The structure of the Go to DATA block is obtaineddirectly from this expression using the normal rules forconstructing NMO S sw itching networks. Since the HoldNUL L block is complementary to this, its structure maybe obtained by complementing the above expression andthen simplifjling using D eMorgans laws as follows:f = [AB + C(A + B)] = (A + B)(C + AB) = AC+ AB + BC = AB + C(A + B)The final form for f eads directly to the topology of theHold NULL block show n in Figure 5using the normalrules for constructing PMO S switching networks. Notethat the equation for f mplies that the Hold NULLblock will be ON if two or more of the inputs are 0,which agrees with the desired behavior for this gate. Thisis seen to be true because, if two or more of the inputsare 0, then the three input values would necessarily bebelow the threshold value for this particular gate.Note also that in this example, the topologies of the Goto DATA and Hold NU LL blocks are identical. We referto this as the self-dual properq. This is a specialattribute that is present in only a su bset of all possibleM-of-N gates.As a second and more complicated example, consider thedesign of a 3 -o f4 gate having inputs A, B, C and D.The switching expression for the G o to DATA block isimmediately obtained from the desired behavior of thisgate:

f = AB C + ABD + AC D + BC DThis can be factored into a more compact form asfollows:

f = AB(C + D) + CD(A + B)The Hold NULL block is computed as follows:

f = (A + B + C)(A + B + D)(A + C + D)(B + C + D)After expanding and simplifying terms, we obtain:f = ,473 + AC + AD + BC + BD + CDA factored representation is as follows:

f = ( A + B)(C + D ) + AB + CDNote that this result co rresponds to the fact that the HoldNULL block will be ON provided that at least two of thefour inputs are low. This agrees with the desiredbehavio r for this particular gate.The factored equations for f and f ead directly to thecircuit shown in Figure 6.Note that the 3-of-4 gate doesnot have the s elf-dual property.

Figure 6. Static 3-of-4 gate.4. SEMI-STATIC IMPLEMENTATIONS

The general structure of a semi-static M-of-N thresho ldgate with hysteresis is shown in Figure 7.Go to NULLwzo to DATA

Figure 7.General structure of a semi-staticthreshold gate with hysteresis.As a specific example, the design of a semi-static 2-of-3threshold gate with hysteresis is shown in Figure 8.Note the structure of the NMOS transistors in the pull-down network is derived from the unfactoredform of theswitchin g expression given earlier. This form is used inorder to obtain maximum robustness against chargesharing effects. This robustness is due to seve ral factors.First, note that the precise order o f the A, B and Cinputs have been permuted so that only one intermediatenode capacitance in the pull-down n etwork willcontribute to charge sharing when any on e of the threeinputs is high. Also, in an actual physical layout, each ofthe three intermediate nodes in the pull-dow n networkwould consist of a single shared diffision region, whichwould have a very sm all capacitance. Note th at thepresence of the weak feedback inverter also provides som eprotection. Since the NMOS and PMO S transistors inthis inverter are weak, they may not be able to source orsink current fast enough to com pletely counteract theeffects of charge sharing. How ever, the current from theweak devices as well as the extra capacitance at theintemal node both act to limit the extent of charg esharing. Moreover, the weak inverter will eventuallyrestore a partially degraded voltage level at the intemalnode to the rail value, which provides additional noiseimmunity.

$ weak)T-

Figure 8. Semi-static 2-of-3 ga te.11-63

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5. DYNAMIC IMPLEMENTATIONSIn many real-time com puting applications, such as thoseinvolving signal processing, the input data stream iscontinuous at a specified minimum rate. In thesesituations, there is no need to maintain state informationwith a feedback mechanism. Rather, the presence orabsence of charge at an isolated node can be m aintainedon the order of a few milliseconds without any loss ofinformation. Thus, for these kinds of applications, wecan eliminate the weak feedback inverter of the semi-static configuration. The resulting circuits are calleddynamic M -of-N gates, and the general block diagram forsuch a gate is shown in Figure 9.The form of the Go toNUL L and Go to DA TA blocks are the same as thoseused in the semi-static configuration, including theappropriate o ptimizations for m inimizing charge sharingeffects.

T1Go to DATA54Figure 9. General structure of a dynamicthreshold gate with hysteresis.

For example, a dynamic 2-of-3 gate would have the sameform as the circuit of Figure 8except that the weakfeedback inverter would be removed.6. INITIALIZATION TECHNIQUE

In many applications, it is necessary to be able toindependently reset a given M-of-N gate to a knowninitial state. A general mechanism for accomplishing thisinitialization is shown in Figure 10for the case wherethe output Z can be initialized to 0. (An analogousstructure can be constructed for initializing Z to 1.) In thecircuit, the signal -RST is an active-low reset signal.When -RST = 0, the output Z is forced to 0 regardless ofthe states of the pull-up and pull-down networks. W hen -RS T = 1, the M -of-N gate operates normally. Thisgeneral structure applies to any of the three circuitimplementation styles discussed above.T T

Network PR l-- RS TNode 1

Pull-Down

Figure 10.General structure o f a threshold gatewith hysteresis and reset to 0.As a specific exam ple of this technique, a static 2-of-2gate with the reset-to-0 capability is shown in Figure 11.

Node 1 1-b- 2A 4

0Figure 11. Static 2-of-2 gate with reset to 0.

7. CONCLUSIONSThe gen eral class of M-of-N threshold gates w ithhysteresis has been introdu ced and several types ofCMO S circuit implementations have been proposed. Thegeneral design proced ures for static, semi-static anddynam ic configurations have been described , and severalspecific M-of-N gate d esign examples have been given.These gates are the primitive building blocks of NULLConvention Logic.These circuit techniques can be used to cons truct anASIC ce ll library of M-of-N gates for a range of values ofM and N. Standard automated place and route tools canbe com bined with schematic capture or synthesis tools toproduce a complete CAD environment for logical andphysical design of systems within this framework.Several prototype chips, including one-dimensional andtwo-dimensional discrete cosine transform processorshave been desig ned and fabricated using thismethodology.

8. ACKNOWLEDGMENTSWe thank Ryan Jorgenson, David Lamb, Dave Parker, RossSmith, Rick Stephani, Ching-Yi Wang and Ken Wagner ofTheseus Logic, Inc. for their help in developing thistechnology and for their comments on this paper. Researchsupported by Ballistic Missiles Defensehnovative Scienceand Technology and managed by the Office of NavalResearch.G. . Sobelman is also with the University of Minnesota,Minneapolis, MN .

9. REFERENCES[ l ] J. A . Brzozowski and C.-J. H. Seger, AsynchronousCircuits, Springer-Verlag, 1995.[2] Karl M. Fant and Scott A. Brandt, NULL ConventionLogic SystemTM,U. S. patent #5,305,463, April 19, 1994.[3] Karl M. Fant and Scott A. Brandt, NULL ConventionLogic? A Complete and Consistent Logic forAsynchronous Digital Circuit Synthesis, Proceedings,International Conference on Application-Specific Systems,Architectures and Processors, pp. 261-273, 1996.[ 41 T.-Y. Wuu and S. B. K. Vrudhula, A Design o f a Fastand Area Efficient Multi-Input Muller C-element, IEEETransactions on Very Large Scale Integration (VLSI)Systems, Vol. 1, No. 2, p. 215-219, 1993.

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