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Reference 2800.1010.1011 FW Version 2.0.x

Revision A Date 24/10/2016

of 75 Copyright © 2015 Eiger Design GmbH

1 Technical Details

J-Testr CAN, ARINC429* and RS2422/485 (CARS) Peripheral

2 Features

Dual CAN Controllers Standard, Extended and Remote frames supported. Supports ARINC825 and CANaerospace Standards 8 maskable identifier filters. 8-message Transmit and Receive FIFOs. Re-transmission disable capability. Monitor (Listen only) Mode Selectable termination (On/Off)

Dual RS422 or RS485 channels Selectable between RS422 or RS485 Selectable Slew rate (115kbps, 500kbps, and 10Mbps*) Selectable termination (On/Off) 5 to 9 Data Bits Parity Odd/Even/Mark/Space/Off Stop Lengths of 1, 1.5 and 2 2K RX and TX Buffers.

2 ARINC RX Channels* 2 ARINC TX Channels* Programmable label recognition for 256 labels* 32 x 32 Receive FIFO and 32 x 32 Transmit FIFO* Independent data rates for Transmit and Receive* Label bit-order control* 32nd transmit bit can be data or parity* Self-Test Mode*

JSafe Enabled On-board Protection 8 Generic I/Os with UART, SPI & PWM features

* ARINC 429 is an optional feature

3 Description

The J-Testr CARS Peripheral Card provides the user with dual CAN serial transceivers, dual RS422 or RS485 serial transceivers and optional dual ARINC429 serial transceivers.

Each CAN controller supports Standard, Extended and Remote Frames and includes all the required timing/protocol adjustment to be fully compliant with both the ARINC825 and CANaerospace standards. An eight deep transmit and receive buffer, as well as 8 maskable identifier filters, allow the CAN transceiver to be configured to significantly reduce test software overhead. A monitor-only mode allows the test software to ‘sniff’ the transmission between


other CAN devices on the same bus, which can be useful when testing UUTs that have an internal CAN bus for cross device communication. Each CAN transceiver has selectable 120-Ohm termination to suit any bus topology.

The RS422/485 transceivers each allow either full duplex differential operation (RS422 mode), or half duplex differential operation (RS485 mode). The differential transmitters can be configured to have different slew rates, depending on the required application speed. This can often be beneficial to reduce reflections if the bus is either long or the connections are not optimal for high-speed use. Large transmit and receive buffers allow very large data packages to be send over the bus, at speed, with little or no test software intervention. Each RS4xx transceiver/receiver has selectable 120-Ohm termination to suit any bus topology.

The optional dual ARINC429 transceivers each have a fully independent transmitter and receiver allowing users to test avionic UUTs which have dual, redundant, communication busses. Each ARINC429 transceiver has a 32 deep transmit and receive message buffer, as well as programmable label recognition, which allows the device to be configured to significantly reduce test software overhead. Other configurations such as label bit order, parity enable on the 32nd transmit bit and a Self-Test Mode give the user great implementation flexibility.

All the serial transceivers on the CARS peripheral card have built-in electrical protection and are fully compatible with the internal J-Testr “J-Safe” mechanism.

Finally, as with all bus connected peripherals, the CARS peripheral provides 8 general purpose ‘User’ I/Os which can be used to control and/or read custom circuitry on the interposer or the UUT. The User IOs provide special hardware functions such as Go-JSafe, 8bit PWMs, SPI communications and a serial UART that can be multiplexed to any of the User IO pins.


3.1 Connections The connector for the CARS peripheral Card is a 64Way PCIe connector with the below pin out.

A1 Reserved B1 Reserved

A2 GND B2 GND

A3 Reserved B3 Reserved

A4 GND B4 GND

A5 Reserved B5 No Connect A6 GND B6 GND

A7 User IO 0 B7 User IO 1



A10 User IO 6 B10 User IO 7 A11 User IO 0 B11 GND

A12 GND B12 GND

A13 CAN_0+ B13 CAN_1+

A14 CAN_0- B14 CAN_1-

A15 GND B15 GND

A16 GND B16 GND

A17 RS422_0 RX+ B17 RS422_1 RX+

A18 RS422_0 RX- B18 RS422_1 RX-

A19 GND B19 GND

A20 GND B20 GND

A21 RS422_0 TX+ [RS485_0+] B21 RS422_1 TX+ [RS485_1+]

A22 RS422_0 TX- [RS485_0+] B22 RS422_1 TX- [RS485_1-]

A23 GND B23 GND

A24 GND B24 GND

A25 ARINC429_0 RXA B25 ARINC429_1 RXA

A26 ARINC429_0 RXB B26 ARINC429_1 RXB

A27 GND B27 GND

A28 GND B28 GND

A29 ARINC429_0 TXA B29 ARINC429_1 TXA

A30 ARINC429_0 TXB B30 ARINC429_1 TXB

A31 GND B31 GND

A32 GND B32 GND


3.2 Connector Location The connector has 0 degrees of rotation and is mounted with the below offset from the interposer slot reference hole:

To PCIe alignment hole - 36.15mm

To Pin A1 - 25.5mm

Important Note: PCIe alignment hole should be 2.2mm +/-0.05mm for alignment

3.3 J-Testr Slot Location

J-Testr Slot Usage

0 Ok

1 Ok

2 Ok

3 Ok

4 Ok

5 Ok

6 Ok

7 Ok

The J-Testr CARS peripheral card can be located in any J-Testr slot. The card is not heat sensitive and can be used as a barrier, if required, between potentially hotter peripheral cards (e.g. load or supply cards) and/or between cards that are more temperature sensitive (ADC/Measurement).


4 Transceivers Master Reset Control

The RS422/485, CAN and ARINC429 transceivers all have a master reset.

The RS422/485 transceivers have individual ‘master reset’ controls and both the CAN and ARINC have a shared ‘master reset’ control between both individual transceivers as shown below:

The master resets are controlled from the ‘COMS_MASTER_CONTROL_ADDR’ resister shown below:

Bit Read/Write Name Description

15 to 12 Read Only Reserved

11 Read Only RS4xx_1_MRst_Act RS422/485 Transceiver 1 Master Reset Actual State

‘1’ = Reset // ‘0’ = Not Reset

10 Read/Write RS4xx_1_MRst_Req RS422/485 Transceiver 1 Master Reset Request State


09 Read Only RS4xx_0_MRst_Act RS422/485 Transceiver 0 Master Reset Actual State


08 Read/Write RS4xx_0_MRst_Req RS422/485 Transceiver 0 Master Reset Request State



05 Read Only ARINC_MRst_Act Both ARINC429 Transceivers Master Reset Actual State


04 Read/Write ARINC_MRst_Req Both ARINC429 Transceivers Master Reset Request State



01 Read Only CAN_MRst_Act Both CAN Transceivers Master Reset Actual State


00 Read/Write CAN_MRst_Req Both CAN Transceivers Master Reset Request State



The request bits ‘request’ the ‘master reset’ to enter the state set, however the transceiver may not be able to enter the requested state due to other influences, such as a J-Safe condition being present. The ‘actual’ bits can be used to verify that the ‘master reset’ is in the state requested.

Note: The master reset request bits for all transceivers are forced to the active ‘1’ state upon a J-Testr power up or system reset and must be cleared to ‘0’ after releasing the system reset to use the transceivers.


5 RS422 / RS485 Transceivers

5.1 Overview There are two RS422 / RS485 transceivers. They are identified using the number/suffix ‘0’ or ‘1’, and this document uses a ‘?’ in some places to generically refer to either ‘0’ or ‘1’. The transceivers have identical functionality and controls. The terminology ‘RS4xx’ is used for clarity and simplicity to mean RS422 and/or RS485.

5.2 RS422 and RS485 Selection RS422 vs RS485 operating mode is selected using the ‘Half_Duplex’ bit in the ‘RS4xx_?_CONTROL_0_ADDR’ register.

NoR

X_O

f_H

DTX

Hal

f_D

uple

x

Slew

Rate

_Sel

ect_

1

Slew

Rate

_Sel

ect_

0

YZTe

rmEn

_Act

YZTe

rmEn

_Req

ABTe

rmEn

_Act

ABTe

rmEn

_Req

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

RS4xx_?_CONTROL_0_ADDR

In hardware the RS422/RS485 transceivers have two differential communication lines as shown below:

When a transceiver is selected as RS422, by clearing the ‘Half_Duplex’ bit in the ‘RS4xx_?_CONTROL_0_ADDR’ register, the communication lines are configured as below:

AB = RS422 RX RS422 Receive pair YZ = RS422 TX RS422 Transmit pair

When a transceiver is selected as RS485, by setting the ‘Half_Duplex’ bit in the ‘RS4xx_?_CONTROL_0_ADDR’ register, the communication lines are configured as below:

AB = Not Used YZ = RS485 TX/RX RS485 Transmit/Receive pair


5.3 Termination Both the AB and YZ differential pairs of the RS422/485 Transceiver can have 120-Ohm termination enabled using the below bits in the ‘RS4xx_?_CONTROL_0_ADDR’ register:

NoR

X_O

f_H

DTX

Hal

f_D

uple

x

Slew

Rate

_Sel

ect_

1

Slew

Rate

_Sel

ect_

0

YZTe

rmEn

_Act

YZTe

rmEn

_Req

ABTe

rmEn

_Act

ABTe

rmEn

_Req

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8


ABTermEn_Req (Bit0) - Request termination on AB differential pair (1 = Enabled // 0 = Disabled) YZTermEn_Req (Bit2) - Request termination on YZ differential pair (1 = Enabled // 0 = Disabled)

The ‘RS4xx_?_CONTROL_0_ADDR’ register also contains bits to confirm that a termination enable request was successful, as below:

ABTermEn_Act (Bit1) - Actual termination state for AB differential pair (1 = Enabled // 0 = Disabled) YZTermEn_Act (Bit3) - Actual termination state for YZ differential pair (1 = Enabled // 0 = Disabled)

These bits are useful to verify if a terminator has been successfully enabled because there are some cases, like if a J-Safe condition exists, where the request bit will be overridden (but not changed) and the terminator disabled even if it is requested to be enabled.

Note: Even though it is possible to enable termination on both AB and YZ differential pairs, when in RS422 mode normally only the AB termination is used, if required, and when in RS485 mode, normally only the YZ termination is used, if required.


5.4 Slew Rate Control Slew rate control is provided to increase compatibility with multiple different UUT receiver types, and/or to reduce reflections caused by long or poorly impedance controlled wiring/connections.

The slew rate limiter has the effect of reducing the maximum possible data rate, and is set using the two ‘SlewRate_Select’ bits in the ‘RS4xx_?_CONTROL_0_ADDR’ register as below:

NoR

X_O

f_H

DTX

Hal

f_D

uple

x

Slew

Rate

_Sel

ect_

1

Slew

Rate

_Sel

ect_

0

YZTe

rmEn

_Act

YZTe

rmEn

_Req

ABTe

rmEn

_Act

ABTe

rmEn

_Req

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8


00 Fast Data rate (up to 10Mbps) 01 Medium Data rate (up to 500kbps) 10 Slow Data (up to 115kbps) 11 Slow Data (up to 115kbps) – same as ‘10’

5.5 Disabling Reception during Transmission The RS485 transceiver has a function that allows the user to disable reception of data whilst data is being transmitted. This is enabled by setting the ‘NoRX_Of_HDTX’ bit in the ‘RS4xx_?_CONTROL_0_ADDR’ register.

NoR

X_O

f_H

DTX

Hal

f_D

uple

x

Slew

Rate

_Sel

ect_

1

Slew

Rate

_Sel

ect_

0

YZTe

rmEn

_Act

YZTe

rmEn

_Req

ABTe

rmEn

_Act

ABTe

rmEn

_Req

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8


This function is only applicable in RS485 mode (with the ‘Half_Duplex’ bit = ‘1’) and is useful to stop the receive buffer being filled with the same data that is being transmitted. This avoids the user having to flush the receive buffer after every transmission, and means that any data in the receive buffer is known to come from other transmitters on the bus.


5.6 Bit Rate (BAUD) Control The bit rate for the RS422 / RS485 Transceiver is set using the ‘RS4xx_?_CONTROL_1_ADDR’ register.

CksP

erBi

t_7

CksP

erBi

t_6

CksP

erBi

t_5

CksP

erBi

t_4

CksP

erBi

t_3

CksP

erBi

t_2

CksP

erBi

t_1

CksP

erBi

t_0

Spee

d_Se

lect

CksP

erBi

t_14

CksP

erBi

t_13

CksP

erBi

t_12

CksP

erBi

t_11

CksP

erBi

t_10

CksP

erBi

t_9

CksP

erBi

t_8

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

The bit rate is configured by setting the number of ‘clocks’ per data bit, where the ‘clock’ resolution is either 5ns, for high speed mode, or 620ns, for low speed mode. The speed mode is selected using the ‘Speed_Select’ bit in the ‘RS4xx_?_CONTROL_1_ADDR’ register as below:

0 Low speed mode, using a 620ns ‘clock’ 1 High speed mode, using a 5ns ‘clock’

The number of ‘clock’ bits are then set using the 15-bit ‘CksPerBit’ value in the same ‘RS4xx_?_CONTROL_1_ADDR’ register.

Examples:

To set a bit rate of 1Mbps

Speed_Select = 1 (High Speed Mode with 5ns clock)

10Mbps = 1 second / 10,000,000 = 100ns

CksPerBit = 100ns / 5ns = 20

To set a bit rate of 50bps

Speed_Select = 0 (Low Speed Mode with 620ns clock)

50bps = 1 second / 50 = 20ms

CksPerBit = 20ms / 620ns = 32,258


5.7 Protocol setup The protocol data length, stop length, and parity can be fully configured on the RS422 / RS485 transceiver using the below bits in the ‘RS4xx_?_CONTROL_2_ADDR’ register as shown below:


07 to 06 Read/Write Parity_Select 2-Bit value to select the desired parity for sending and receiving

00 = Even

01 = Odd

10 = Space

11 = Mark

(Default = 0)

05 Read/Write Parity_Enable 0 = Disable Parity Checking

1 = Enable Parity Checking

(Default = 0)

04 to 03 Read/Write StopLen_Select 2-Bit value to select the desired number of stop bits to send

AND to select the checking regime for the stop bits.

00 = Send 1 Stop Bit (Receive and Check for 1)

01 = Send 1.5 Stop Bits (Receive and Check for 1.0)

10 = Send 2 Stop Bits (Receive and Check for 1)

11 = Send 2 Stop Bits (Receive and Check for 2)

(Default = 0)

02 to 00 Read/Write DataLen_Select 3-Bit value to select the desired data length. The value set by these bits is added to the minimum value of 5 bits.

000 = 5+0 = 5bit

001 = 5+1 = 6bits

010 = 5+2 = 7bits

011 = 5+3 = 8bits

100 = 5+4 = 9bits

101, 110, 111 = maximum 9bits

(Default = 3)


5.8 Receiver and Transmitter Enable The transmitter and/or receiver can be Enabled/Disabled using the ‘TX_Enable’ and ‘RX_Enable’ bits in the ‘RS4xx_?_CONTROL_2_ADDR’ register as shown below.

0 Disable Transmitter or Receiver (Default) 1 Enable Transmitter or Receiver

The user may, for example, wish to disable the receiver to stop it receiving data/garbage when a UUT is powered off, or to avoiding unnecessary filling of the receive buffer when incoming data is of no interest.

The transmitter can be disabled, for example, to allow the user to pre-fill the transmit buffer with data, and then send all the loaded data in one continuous burst/chunk without delays between each data byte. This can be particularly useful in functional test environments to fully stress receivers on UUTs.

5.9 Break The The RS422 / RS485 transceiver includes a transmit ‘Break’ function which will immediately force the RS4xx output to a ‘low’ state for as long as the ‘TX_Break’ bit is set at ‘1’.

Any data transmission in progress will continue to function in the background, hence in this condition all bits being transmitted whist ‘TX_Break’ is enabled will be lost. If this is not desired, use break combined with TX enabling/disabling.


5.10 Events The RS422 / RS485 transceiver provides information on events, that may have occurred, via event flags in the ‘RS4xx_?_CONTROL_2_ADDR’ register as shown below.

Flag Name Read/Write Description

TX_Done_Event Read/Write This event bit is set to '1' if the transmitter has just sent the last stop bit and there is no more data available in the transmit buffer. The transmitter may still be sending data from its transmit shift register even though the transmit buffer may be empty. This flag can be used to indicate that the transmit buffer is empty AND that there is no data 'on the wire' in the process of being transmitted

RX_OverRun_Event Read/Write This event bit is set to '1' if the receiver has just received a good frame (start bit, data, any parity, & valid stop bit) but the receive buffer was already full. Parity errors are ignored.

RX_Framing_Event Read/Write This event bit is set to '1' if the receiver has just received a frame but the stop bit was invalid (start bit, data, any parity, & invalid stop bit or bits). If a frame is received with one or more missing stop bits the data is NOT written to the buffer. Parity errors are ignored.

RX_Parity_Event Read/Write This event bit is set to '1' if the receiver has just received a frame but the parity bit was invalid (start bit, data, invalid parity, & good stop bits). If a frame is received with bad parity, the data IS still written to the buffer to allow the user to evaluate it.

These event bits are latched so that the information is preserved until the user specifically clears it. Writing a ‘1’ to an event bit will clear the event.

5.11 Data Transition and Reception Data is transmitted and received using the lower byte of the ‘RS4xx_?_DATA_ADDR’ register.

Dat

a_7

Dat

a_6

Dat

a_5

Dat

a_4

Dat

a_3

Dat

a_2

Dat

a_1

Dat

a_0

RX_B

uffe

r_Em

pty

RX_O

verR

un_E

vent

RX_F

ram

ing_

Even

t

RX_P

arity

_Eve

nt

Rese

rved

Rese

rved

Rese

rved

Dat

a_8

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

Write to this address to put the data into the transmit buffer. Read from this address to pull the data out of the receive buffer. If the receive buffer is empty, the returned data value is undefined.


The number of bits written or read depends on the data length configured for the transceiver. Lengths from 5 to 9 are possible. Unused bits written are ignored, and unused bits read will read as 0.

The same ‘RS4xx_?_DATA_ADDR’ register also contains current receiver status bits (read-only) as below:


15 Read Only RX_Buffer_Empty This bit gives live status of the receive buffer empty status. 0 = not empty, 1 = empty. An empty buffer may be read with no effect, but the data value read is undefined.

14 Read Only RX_OverRun_Event This bit is a read-only copy of the same named bit in the ‘RS4xx_?_CONTROL_2_ADDR’ register.

13 Read Only RX_Framing_Event This bit is a read-only copy of the same named bit in the ‘RS4xx_?_CONTROL_2_ADDR’ register.

12 Read Only RX_Parity_Event This bit is a read-only copy of the same named bit in the ‘RS4xx_?_CONTROL_2_ADDR’ register.

These bits can be used whilst continuously reading data to determine if the data being read is valid/corrupted, or no data is available (RX buffer is empty).

5.12 Buffers Both the transmitter and receiver have large FIFO buffers to help reduce test software overhead.

5.12.1 RX Buffer The receive buffer provides controls and information using the ‘RS4xx_?_RX_BUFF_ADDR’ address as below:

RX_U

sedB

ytes

_7

RX_U

sedB

ytes

_6

RX_U

sedB

ytes

_5

RX_U

sedB

ytes

_4

RX_U

sedB

ytes

_3

RX_U

sedB

ytes

_2

RX_U

sedB

ytes

_1

RX_U

sedB

ytes

_0/

RX_B

uffe

r_Fl

ush

RX_S

izeRe

ad_E

nabl

e

Rese

rved

Rese

rved

RX_U

sedB

ytes

_12

RX_U

sedB

ytes

_11

RX_U

sedB

ytes

_10

RX_U

sedB

ytes

_9

RX_U

sedB

ytes

_8

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

RS4xx_?_RX_BUFF_ADDR

Bit Read/Write Description

15 Read/Write RX_SizeRead_Enable This bit may be set to '1' to allow the size of the RX buffer to be read from bits 12 down to 0 of this address. When this bit is '0' (Default) the number of 'Used' bytes in the RX buffer can be read from bits 12 down to 0 of this address.

14 to 13 Reserved Reserved Write as '0' for future compatibility. Reserved for possible future features.

12 to 0 Read Only RX_UsedBytes IF(RX_SizeRead_Enable = 0)

Reports the number of 'Used' bytes (i.e. the number of bytes received) in the receive FIFO buffer.

IF(RX_SizeRead_Enable = 1)

Reports the size of the RX Buffer in bytes

0 Write Only RX_Buffer_Flush If '1' is written to this bit, then the RX FIFO is 'flushed'. Writing '1' to this bit is a one-shot event and the bit does not latch and does not need to be written back to '0'.


5.12.2 TX Buffer The transmit buffer provides controls and information using the ‘RS4xx_?_TX_BUFF_ADDR’ address as below:

TX_F

reeB

ytes

_7

TX_F

reeB

ytes

_6

TX_F

reeB

ytes

_5

TX_F

reeB

ytes

_4

TX_F

reeB

ytes

_3

TX_F

reeB

ytes

_2

TX_F

reeB

ytes

_1

TX_F

reeB

ytes

_0/

TX_B

uffe

r_Fl

ush

TX_S

izeRe

ad_E

nabl

e

Rese

rved

Rese

rved

TX_F

reeB

ytes

_12

TX_F

reeB

ytes

_11

TX_F

reeB

ytes

_10

TX_F

reeB

ytes

_9

TX_F

reeB

ytes

_8

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

RS4xx_?_TX_BUFF_ADDR


15 Read/Write TX_SizeRead_Enable This bit may be set to '1' to allow the size of the TX buffer to be read from bits 12 down to 0 of this address. When this bit is '0' (Default) the number of 'Free' bytes in the TX buffer can be read from bits 12 down to 0 of this address.


12 to 00 Read Only TX_FreeBytes IF(TX_SizeRead_Enable = 0)

Reports the number of 'Free' bytes (i.e. the space available) in the transmitter FIFO buffer.

IF(TX_SizeRead_Enable = 1)

Reports the size of the TX Buffer in bytes

00 Write Only TX_Buffer_Flush If '1' is written to this bit then the TX FIFO is 'flushed'. Writing '1' to this bit is a one-shot event and the bit does not latch and does not need to be written back to '0'.


6 CAN Transceiver

6.1 Overview The CAN transceiver, on the CARS peripheral, uses the Holt inc HI-3110 device to implement the CAN communications function. The HI-3110 contains all the functions and controls required to implement all possible CAN specification buses, as well as ARINC825 and CANaerospace specified buses.

The HI-3110 utilises a register based control scheme which is similar to that used by the J-Testr system.

The CARS peripheral card takes care of all the electrical interfacing to the HI-3110 and exposes a very simple communication interface to access the HI-3110 internal registers. The CAN transceiver block diagram is show below:

More information on the HI-3110 can be found in the HI-3110 datasheet, which can be found on the on the Holt Integrated Circuits website, www.holtic.com, or on the Eiger Design GmbH website.

Note: As with all J-Testr peripheral cards and functions, Eiger Design GmbH provide fully working ‘open source’ drivers such that the user can easily understand how to use all the CAN functions available. Please contact Eiger Design GmbH on [email protected] for more information.


6.2 HW Status Bits The HI-3110 has four hardware status bits that can be internally programmed to output different information, depending how they are configured, as per below:

INT - Active high. Programmable interrupt output

STAT - Active high. Programmable status output.

GP1 - General purpose pin 1, which can be programmed to reflect the values of interrupt and status flag bits.

GP2 - General purpose pin 2, which can be programmed to reflect the values of interrupt and status flag bits.

These bits have little value/use in test applications, however they are provided to the user as read-only bits through the ‘CAN_?_CONTROL_ADDR’ register, as below, just in case the user wishes to use them.

CAN_?_CONTROL_ADDR

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

TXEn

Term

En_A

ct

Term

En_R

eq

GP2

GP1

Stat Int

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

GP2 (Bit15) - HI-3110 GP2 Output Value GP1 (Bit14) - HI-3110 GP1 Output Value Stat (Bit13) - HI-3110 Stat Output Value Int (Bit12) - HI-3110 Int Output Value

6.3 HW Transmit Enable An external hardware ‘Transmit Enable’ is provided on the HI-3110 and can be accessed using the ‘TXEn’ bit in the ‘CAN_?_CONTROL_ADDR’ register as below

CAN_?_CONTROL_ADDR

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

TXEn

Term

En_A

ct

Term

En_R

eq

GP2

GP1

Stat Int

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

TXEn (Bit2) - Active High Transmit Enable pin on the HI-3110

The HW ‘Transmit Enable’ is logically ORed with the TXEN and TX1M bits in the HI-3110 CTRL1 register. When the TXEn pin is reset (‘0’), messages loaded to the FIFO will not be sent until TXEN or TX1M bits are set in the CTRL1 register.

In test applications it is extremely rare that the ‘HW Transmit Enable’ is required, given that the HI-3110 SW function does the same function, however it is provided in case the user wishes to use it.


6.4 Termination The CAN differential pair can have a 120-Ohm termination enabled using a bit in the ‘CAN_?_CONTROL_ADDR’ register as below:

CAN_?_CONTROL_ADDR

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

TXEn

Term

En_A

ct

Term

En_R

eq

GP2

GP1

Stat Int

Reve

rsed

Reve

rsed

Reve

rsed

Reve

rsed

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

TermEn_Req (Bit0) - Request termination on CAN Differential pair (1 = Enabled // 0 = Disabled) The same ‘CAN_?_CONTROL_ADDR’ register contains a bit to confirm that the termination enable request was successful as below:

TermEn_Act (Bit1) - Actual termination state for CAN Differential pair (1 = Enabled // 0 = Disabled)

The ‘TermEn_Act’ bit is useful to verify if the terminator has been successfully enabled because there are some cases, like if a J-Safe condition exists, where the request bit will be overridden (but not changed) and the terminator disabled even if it is requested to be enabled.

6.5 Transmit and Receive Data Buffers The communications/control interface between the CARS peripheral and the HI-3110 has a separate 32 byte transmit and 32 byte receive buffer. These buffers are placed within the CARS memory map as 16-bit words with the lower byte of the lowest word address being the lowest order byte of the buffer, and upper byte of the highest word address being the highest order byte of the buffer.

NOTE: Data can only be written into the write buffer when the associated ‘Go_Busy’ bit is indicating NOT busy. (See section 6.6 Data Control Interface).


The Transmit buffer mapping is shown below:

TX_Buffer_Byte1 TX_Buffer_Byte0

Most Significant Byte Lower Significant ByteJ-Testr 16bit Word

0707

015

TX_Buffer_Byte3 TX_Buffer_Byte2TX_Buffer_Byte5 TX_Buffer_Byte4TX_Buffer_Byte7 TX_Buffer_Byte6TX_Buffer_Byte9 TX_Buffer_Byte8

TX_Buffer_Byte11 TX_Buffer_Byte10TX_Buffer_Byte13 TX_Buffer_Byte12TX_Buffer_Byte15 TX_Buffer_Byte14TX_Buffer_Byte17 TX_Buffer_Byte16TX_Buffer_Byte19 TX_Buffer_Byte18TX_Buffer_Byte21 TX_Buffer_Byte20TX_Buffer_Byte23 TX_Buffer_Byte22TX_Buffer_Byte25 TX_Buffer_Byte24TX_Buffer_Byte27 TX_Buffer_Byte26TX_Buffer_Byte29 TX_Buffer_Byte28TX_Buffer_Byte31 TX_Buffer_Byte30

CAN_1 Address

0x200x210x220x230x240x250x260x270x280x290x2A0x2B0x2C0x2D0x2E0x2F

CAN_0 Address


The Receive buffer mapping is shown below:

RX_Buffer_Byte1 RX_Buffer_Byte0

CAN_1 Address Most Significant Byte Lower Significant ByteJ-Testr 16bit Word

0707

015

RX_Buffer_Byte3 RX_Buffer_Byte2RX_Buffer_Byte5 RX_Buffer_Byte4RX_Buffer_Byte7 RX_Buffer_Byte6RX_Buffer_Byte9 RX_Buffer_Byte8

RX_Buffer_Byte11 RX_Buffer_Byte10RX_Buffer_Byte13 RX_Buffer_Byte12RX_Buffer_Byte15 RX_Buffer_Byte14RX_Buffer_Byte17 RX_Buffer_Byte16RX_Buffer_Byte19 RX_Buffer_Byte18RX_Buffer_Byte21 RX_Buffer_Byte20RX_Buffer_Byte23 RX_Buffer_Byte22RX_Buffer_Byte25 RX_Buffer_Byte24RX_Buffer_Byte27 RX_Buffer_Byte26RX_Buffer_Byte29 RX_Buffer_Byte28RX_Buffer_Byte31 RX_Buffer_Byte30


CAN_0 Address



6.6 Data Control Interface The data control interface to the HI-3110 is done via the ‘CAN_?_COMMAND_ADDR’ register and the transmit and receive data buffers.

The HI-3110 works on instructions, with different instructions for register ‘Reads’ and ‘Writes’. Each instruction also has an associated data field size as shown in the below table extracted from the HI-3110 datasheet.


The HI-3110 OpCode/Instruction and associated data length is configured using the ‘CAN_?_COMMAND_ADDR’ register. The same register is used to initiate a communication with the HI-3110, allowing a single write to both set-up and start the communications.

The ‘CAN_?_COMMAND_ADDR’ register and its functions are shown below:


15 Read/Write Go_Busy Read indicates if the communication engine is currently busy. If ‘Go_Busy’ = '1' then the communications engine is ‘Busy’ doing a transfer with the HI-3110. Anything written to the ‘CAN_?_COMMAND_ADDR’ register whilst 'Busy' is IGNORED and LOST.

Writing a ‘1’ to this bit initiates a communication transfer as long as the communications is not currently ‘Busy’ and there is no ‘Cmd_Err’.

It is always highly recommended to check this flag before starting a communication

14 Read Only Cmd_Err Shows if there is an error ('1') with the "OpCode/Instruction" or "DLength" values currently loaded (i.e. previously written) into this register.

13 to 08 Read/Write DLength This is the requested number of data bytes (associated with the "OpCode/Instruction") to be written/read to/from the controller. Refer to the controller chip data sheet. The "DLength" value is checked against the allowed value listed in the HI-3110 datasheet for the associated "OpCode/Instruction". When writing to the transmit FIFO ("OpCode/Instruction" = 0x12) the controller chip allows multiple frames to be loaded in one SPI transaction, and the byte count per frame can vary, so the overall communication byte count can vary significantly. In this instance, the data length requested is only indicated as an error if it is outside the range of 4-32 bytes. Using an incorrect or disallowed length value will cause the "Cmd_Err" bit to be set to '1' and no communication transaction will occur.

07 to 00 Read/Write OpCode This is the command "OpCode/Instruction" to be written to the HI-3110. Refer to the controller chip data sheet. The "OpCode/Instruction" is checked against the values listed in the HI-3110 datasheet. Any values that are not listed, noted as reserved, or noted as not implemented in the HI-3110 datasheet are unsupported and will cause the "Cmd_Err" bit to be set to '1' and no communication will occur.


For command communication transactions (i.e. BOTH write AND read type OpCodes) the data written is sourced from the transmit buffer registers, and the data read is saved to the receive buffer registers. See section 6.5 Transmit and Receive Data Buffers

The data read back during a write type "OpCode/Instruction" communications transaction can be ignored but is stored in case it is ever useful for HI-3110 diagnostics. The data written during a read type "OpCode" communications transaction does not need to be 'zeroed out' since it should be ignored by the HI-3110.

6.6.1 Example Communications In this example we will show a communications transaction to read Control Register 1 (OpCode 0xD4) and write Control Register 1 (OpCode 0x16) for CAN device 0. The Instruction has a length of 1.

CAN_0_COMMAND_ADDR = 0x05

6.6.1.1 Read Read Register 0x05 // To read the ‘Go_Busy’ bit and check/wait for comms with the HI-3110 to become NOT busy

If (Go_Busy = ‘1’) then

Wait (with time-out) for Go_Busy to be ‘0’

Endif

If (Go_Busy = ‘0’) then // Check for not busy because may have got here due to a time-out waiting for not-busy

Write OpCode, DLength and ‘Go_Busy’ to Address 0x05 // 0x00D4 + 0x0100 + 0x8000 = 0x81D4

Read address 0x05 to check if the ‘Cmd_Err’ flag is set // optional, action as appropriate

If (Go_Busy = ‘1’) then // wait for communication to finish so that we know the read data is available

Wait (with time-out) for Go_Busy to be ‘0’

Endif

Read the lowest word address of the RX buffer and use the lower byte // The one-byte value is the lower byte

Endif

6.6.1.2 Write Read Register 0x05 // To read the ‘Go_Busy’ bit and check/wait for comms with the HI-3110 to become NOT busy

If (Go_Busy = ‘1’) then

Wait for Go_Busy to be ‘0’

Endif

If (Go_Busy = ‘0’) then // Check for not busy because may have got here due to a time-out waiting for not-busy

Write the data in the low byte of the lowest word address of the TX buffer // The one-byte value is the lower byte

Write OpCode, DLength and ‘Go_Busy’ to Address 0x05 // 0x0016 + 0x0100 + 0x8000 = 0x8116

Read Address 0x05 to check if the ‘Cmd_Err’ flag is set // optional, action as appropriate#

Endif

Note: Full ‘Open source’ example drivers as available from Eiger Design GmbH


6.7 Setting Bit Rate When setting the bit rate of the CAN device the user must be aware that the HI-3110 is clocked from an external 40MHz clock.

The bit rate of the HI-3110 is highly configurable and can be set however the user requires. However some recommended settings for popular bit rates are shown below:

HI-3110 Configurable elements are:

Baud Rate Pre-scaler (i.e. the BRP_Bits 5:0 in the HI-3110 Timing Register 0) Re-Sync Jump Width (i.e. the SJW_Bits 1:0 in the HI-3110 Timing Register 0) TSeg1 (Prop Seg + Phase Seg 1) (i.e. the TSeg1_Bits 3:0 in the HI-3110 Timing Register 1) TSeg2 (Phase Seg 2) (i.e. the TSeg2_Bits 2:0 in the HI-3110 Timing Register 1)

Bit Rate

Baud Rate

Pre-scaler (BRP_Bits 5:0)

(BRP = BRP_Bits + 1)

(Tq = 2*BRP/40MHz)

Re-sync

Jump Width (SJW_Bits 1:0)

(0 = 1Tq)

TSeg1 (TSeg1_Bits 3:0)

(0 = 1Tq)

Tseg2 (Tseg2_Bits 2:0)

(0 = 1Tq)

Note

1M 0 0 13 4 Prescale = Div2 => 20 Tq per bit

500K 1 0 13 4 Prescale = Div4 => 20 Tq per bit




83.33K 11 0 13 4 Prescale = Div24 => 20 Tq per bit



The user is also able to change the amount of samples taken per bit (1 or 3), however this does not affect the bit rate and in test applications either setting will work fine., Please see the HI-3110 datasheet for more detail.

Note: Full ‘Open source’ example drivers as available from Eiger Design GmbH


7 ARINC Transceiver

7.1 Overview The ARINC429 capability of the CARS peripheral is optional and may not be fitted and/or enabled. Please contact Eiger Design GmbH on [email protected] for more information.

The ARINC429 capability, if fitted/enabled, uses the Holt inc HI-3585 device to implement the ARINC429 communications functions. The HI-3585 contains all the functions and controls required to implement the ARINC429 serial buses.

The HI-3585 utilises a register based control scheme which is similar to that used by the J-Testr system.

The CARS peripheral card takes care of all the electrical interfacing to the HI-3585 and exposes a very simple communication interface to access the HI-3585 internal registers. This communication interface is almost identical to that used for controlling the HI-3110 CAN transceiver (See section 6 CAN Transceiver).

More information on the HI-3585 can be found in the HI-3585 datasheet, which can be found on the on the Holt Integrated Circuits website, www.holtic.com, or on the Eiger Design GmbH website.

Note: As with all J-Testr peripheral cards and functions, Eiger Design GmbH provide fully working ‘open source’ drivers such that the user can easily understand how to use all the ARINC429 functions available. Please contact Eiger Design GmbH on [email protected] for more information on the optional ARINC429 transceivers.


8 Scratchpad Register

A scratch pad register is provided on all J-Testr Bus controlled devices. This register allows the user to read and write information without any effect to the device. This is useful for communication testing purposes and general debugging. This register is cleared to 0x0000 after a reset.

9 Global Triggers

Every J-Testr bus connected peripheral card provides a write-only ‘GLOBAL_TRIGGERS_ADDR’ which is always located at address 0xFD in the memory mapped address space of every peripheral, and the motherboard. This address is decoded such that the user can write this address (0xFD) in the address space of ANY peripheral, or the motherboard and the effect is the same. Effectively every peripheral and the motherboard simultaneously 'listens' on the 0xFD address in its own address space, and also 'listens' to all the other 0xFD addresses within every other card's address space.

Writing this address (within any card's address space) provides the user a means to issue ‘Global Triggers’ to all bus connected peripherals in the J-Testr system, including the Motherboard ‘System’ device. Certain J-Testr peripheral cards have functions that can be activated upon receipt of a global trigger. This allows synchronisation of certain events across several cards in the system. eg PSU sequencing. Global triggers are activated by writing '1' to the required bit, or even multiple bits. There are 16 Global triggers, one for each bit in the ‘GLOBAL_TRIGGERS_ADDR’ register as below:

Glo

bal T

rigg

er 1

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

GLOBAL_TRIGGERS_ADDR

Glo

bal T

rigg

er 0

Glo

bal T

rigg

er 3

Glo

bal T

rigg

er 2

Glo

bal T

rigg

er 5

Glo

bal T

rigg

er 4

Glo

bal T

rigg

er 7

Glo

bal T

rigg

er 6

Glo

bal T

rigg

er 9

Glo

bal T

rigg

er 8

Glo

bal T

rigg

er 1

1

Glo

bal T

rigg

er 1

0

Glo

bal T

rigg

er 1

3

Glo

bal T

rigg

er 1

2

Glo

bal T

rigg

er 1

5

Glo

bal T

rigg

er 1

4

The trigger itself is a ‘momentary’ event that occurs every time the associated trigger bit is written to '1'. The ‘GLOBAL_TRIGGERS_ADDR’ is write-only.


10 J-Safe mechanism

The J-Safe mechanism provides a fast reaction hardware signal to the whole J-Testr system to place the test system into a ‘safe state’ where all potential energy sources connected between the tester and the UUT are turned off and/or made high-impedance. This means for example that no current can be sourced/sunk through internal protection diodes, or other circuitry, on the UUT that may cause latent damage which can sometimes be very hard to detect.

The J-Safe signal is triggered by internal ‘critical events’ within a peripheral card.

All bus controlled (BC) devices, including the motherboard, can trigger and receive the J-Safe signal, as indicated by the below bits in the (common among all BC devices) ‘JSAFE_ADDR’ register

JSafe_RX - 1 = Device is receiving a J-Safe signal (Device is in J-Safe safe state) // 0 = No J-Safe signal JSafe_TX - 1 = Device caused the J-Safe condition // 0 = Device did not cause the J-Safe condition

The J-Safe mechanism also provides user configurable external & latched ‘GoJSafe’ trigger signal(s). These are configured by selecting the appropriate alternative function for any of the generic user IOs (See section 11 User IO and 11.2


Alternative Function Selection). When enabled, this signal is activated using a logic ‘low’ level, to enable multiple open collector sources to be wire-ored, and can be triggered by external circuitry on the interposer or direct from a UUT.

This allows the user to add their own additional customised safety circuits to the interposer, or even to use fault signals directly generated by a UUT. This means sensitive internal UUT supplies could be monitored using simple comparator circuits or POR devices, and could be used to trigger the rapid & system-wide J-Safe mechanism. An example would be an external over-voltage signal, using simple comparator circuit, monitoring the internal VccInt of a FPGA or other sensitive silicon devices on the UUT.

Users are also able to sense the presence of a J-Safe condition on the interposer since all ‘User IOs’ are set to high impedance when a J-Safe condition occurs. This could be detected and used to disconnect any external stimulation sources used within the test system, or even to provide an indicator or buzzer to alert an operator to the J-Safe condition. For advice on external protection circuits or any aspect of the J-Safe mechanism please contact [email protected].

This latched ‘GoJSafe’ signal event from the User IO(s) can be found in the ‘JSAFE_ADDR’ register as below:

UIO_GoJSafe_Event - 1 = User IO Go J-Safe event triggered // 0 = Go J-Safe event not triggered

The User IO Go-JSafe events must be cleared by writing logic ‘1’ to the UIO_GoJSafe_Event flag or by a system reset.

10.1 J-Safe condition triggers On the CARS peripheral card, the below critical events will trigger a J-Safe condition:

External Go-JSafe via the generic general purpose User IOs

To remove the J-Safe condition, the J-Safe condition root cause must be removed, and all latched J-Safe event flags must be cleared by writing logic ‘1’ to the flags or by a system reset.

10.2 J-Safe condition responses Whist this card is receiving a J-Safe condition from the system-wide J-Safe signal, it responds as follows

All UserIOs made high impedance <latched>1 All CAN & ARINC Transceivers are placed in Master Reset2 (to flush their transmit buffers and stop transmission) All RS4xx transmit buffers are flushed to abort any in-progress TX and ALL pending buffered TXs All terminators are disconnected2 1 Via the motherboard PERIPHERAL_IO_ENABLE_ADDR register being cleared when the motherboard detects the J-Safe condition. 2 Will return to the set state once the J-Safe condition is removed, but transceivers may need reconfiguring as they have been ‘reset’

10.3 Working with J-Safe The J-Safe mechanism has been designed to enable simple tracking of the cause of the condition.

Upon a test failure, it is recommended that the user checks the state of the ‘JSAFE_ADDR’ registers for all bus controlled devices to see if a J-Safe condition was detected. See example procedure below:

a) If the first ‘JSAFE_ADDR’ register read does not indicate a J-Safe condition, with the ‘JSafe_RX’ flag, then the user knows the J-Testr system is not in a J-Safe condition and can continue.

b) If the ‘JSAFE_ADDR’ register does indicate a J-Safe condition, the user can simply check to find which device caused the J-Safe condition by checking the ‘JSafe_TX’ flag in each bus controlled device.

c) Once the device that caused the J-Safe condition is found, the device specific fault registers can be checked to find the detailed cause and to initiate any debug/printing/logging actions as required.

d) Clear any latched faults using the appropriate mechanism depending on the card type, or do a system reset (preferred).


11 User IO

11.1 Basic IO Operation The CARS Peripheral Card has 8 general purpose ‘User IOs’ which are controlled using the ‘USER_IO_OP_PIN_ADDR’ and ‘USER_IO_MODE_ALTFNEN_ADDR’.

Each pin has the below flags:

Output <OP> => Controls the output polarity of the pin

Pin <Pin> => Actual live state of the User IO pin

Mode <Mode> => Selects if the pin is Push/Pull (1) or Open Collector (0)

Alterative Function Enable <AltFnEn> => Selects if the User IO pin is to be selected for use as another function The above flags are in the LSB and the HSB of the ‘USER_IO_OP_PIN_ADDR’ and ‘USER_IO_MODE_ALTFNEN_ADDR’ registers as shown below:

User

IO 7

OP

Bit

User

IO 6

OP

Bit

User

IO 5

OP

Bit

User

IO 4

OP

Bit

User

IO 3

OP

Bit

User

IO 2

OP

Bit

User

IO 1

OP

Bit

User

IO 0

OP

Bit

Use

r IO

7 P

in B

it

Use

r IO

6 P

in B

it

Use

r IO

5 P

in B

it

Use

r IO

4 P

in B

it

Use

r IO

3 P

in B

it

Use

r IO

2 P

in B

it

Use

r IO

1 P

in B

it

Use

r IO

0 P

in B

it

HSB LSBBi

t 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

USER_IO_OP_PIN_ADDR

User

IO 7

Mod

e Bi

t

User

IO 6

Mod

e Bi

t

User

IO 5

Mod

e Bi

t

User

IO 4

Mod

e Bi

t

User

IO 3

Mod

e Bi

t

User

IO 2

Mod

e Bi

t

User

IO 1

Mod

e Bi

t

User

IO 0

Mod

e Bi

t

Use

r IO

7 A

ltFnE

n Bi

t

Use

r IO

6 A

ltFnE

n Bi

t

Use

r IO

5 A

ltFnE

n Bi

t

Use

r IO

4 A

ltFnE

n Bi

t

Use

r IO

3 A

ltFnE

n Bi

t

Use

r IO

2 A

ltFnE

n Bi

t

Use

r IO

1 A

ltFnE

n Bi

t

Use

r IO

0 A

ltFnE

n Bi

t

HSB LSB

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

USER_IO_MODE_ALTFNEN_ADDR

The below table shows the possible ‘User IO’ operation modes:

Output <OP>

Mode <Mode>

Alternative Function Enable <AltFnEn>

Output drive High 1 1 0

Output drive Low 0 X 0

Open Collector Floating <Input> 1 0 0

Open Collector drive Low 0 0 0

Alternative Function X X 1

11.2


11.3 Alternative Function Selection Each user IO pin can be placed into an alternative function mode by setting the AltFnEn Bit as seen in section 11.1 Basic IO Operation.

Once this bit is selected the user can set the alternative function required in the alternative function signal selection registers ‘USER_IO_3TO0_ALTFN_SIGSEL_ADDR’ and ‘USER_IO_7TO4_ALTFN_SIGSEL_ADDR’.

Each User IO line has a 4-bit nibble value to select up to 16 possible special functions as below:

Index Pin Function Alternative Function Device Direction 0 PWM Output 0 PWM Generator 0 Output 1 PWM Output 1 PWM Generator 1 Output 2 PWM Output 2 PWM Generator 2 Output 3 PWM Output 3 PWM Generator 3 Output 4 UART_0_TX UART 0 Output 5 UART_0_RX UART 0 Input 6 SPI 0 Select SPI 0 Output (nCS, SCLK, MOSI)

Input (MISO) 7 Hi-Z None Input 8 Hi-Z None Input 9 Hi-Z None Input

10 Hi-Z None Input 11 Hi-Z None Input 12 Hi-Z None Input 13 Hi-Z None Input 14 Hi-Z None Input 15 GoJSafe J-Safe Input

The USER_IO_3TO0_ALTFN_SIGSEL_ADDR’ and ‘USER_IO_7TO4_ALTFN_SIGSEL_ADDR’ register breakdown is shown below:

HSB LSB

USER_IO_7TO4_ALTFN_SIGSEL_ADDR

IO 5

AltF

n Si

g Se

l 3

IO 5

AltF

n Si

g Se

l 2

IO 5

AltF

n Si

g Se

l 1

IO 5

AltF

n Si

g Se

l 0

IO 4

AltF

n Si

g Se

l 3

IO 4

AltF

n Si

g Se

l 2

IO 4

AltF

n Si

g Se

l 1

IO 4

AltF

n Si

g Se

l 0

IO 7

AltF

n Si

g Se

l 3

IO 7

AltF

n Si

g Se

l 2

IO 7

AltF

n Si

g Se

l 1

IO 7

AltF

n Si

g Se

l 0

IO 6

AltF

n Si

g Se

l 3

IO 6

AltF

n Si

g Se

l 2

IO 6

AltF

n Si

g Se

l 1

IO 6

AltF

n Si

g Se

l 0

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8


11.4 User IO Addresses As the UserI O function is common among all J-Testr bus connected peripheral cards their base addresses can be found in the information address (0x00) at the index location 0x10.

The User IO addresses are in a block of 4 as below: USER_IO_OP_PIN_ADDR = Base address

USER_IO_MODE_ALTFNEN_ADDR = Base address + 1

USER_IO_3TO0_ALTFN_SIGSEL_ADDR = Base address + 2

USER_IO_7TO4_ALTFN_SIGSEL_ADDR = Base address + 3 This scheme of providing the function base address via the fixed 'information' address helps support common drivers across all peripheral cards whilst allowing the base address to be different on different peripheral cards if necessary for future designs.


12 UART Function

A UART function allows for communications with external equipment or the UUT itself. The UART uses standard 8N1 or 8N21 (8bits, No Parity and 1or2 stop Bits) format and has selectable baud rates.

Both 2048 Byte transmit and 2048 byte receive buffers are provided to allow for fast and simple communication transfers without excessive software flow controls.

The UART TX/RX function can be selected to be used on any User IO pins

1 Other formats available on request.

12.1 Setup The setup of the UART is completed using the ‘USER_IO_UART_0_CTRL_ADDR’ register as detailed in the below figure: (Reserved bits should be written as '0' for future compatibility.)

Rese

rved

Rese

rved

Rese

rved

Baud

_Sel

ect

TX_

Don

e_Ev

ent

RX_O

verR

un_E

vent

RX_F

ram

ing_

Even

t

Rese

rved

TX_B

reak

TX_2

Stop

Bits

TX_E

nabl

e

RX_E

nabl

e

HSB LSBBi

t 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

USER_IO_UART_0_CTRL_ADDR

12.1.1 Baud Rate Setting The UART supports 20 different baud rates that can be read/written, at any point, to the ‘Baud_Select’ bits as shown in the below table:

Baud_Select Value (Decimal)

UART Speed (Bits/Sec)

0 50 1 75 2 110 3 150 4 300 5 600 6 1_200 7 2_400 8 4_800 9 9_600

10 14_400 11 19_200 12 28_800 13 31_250 14 38_400 15 57_600 16 115_200 17 230_400 18 250_000 19 460_800

Others Reserved. Do not use.


12.1.2 RX_Enabling The UART receiver can be enabled/disabled by writing logic ‘1’ and ‘0’ respectively to the ‘RX_Enable’ bit.

When the UART receiver is disabled all data received at the RXD pin will be ignored. If the receiver is in the process of receiving a byte when RX is disabled, then the current byte is received normally, and then the disable takes effect.

12.1.3 TX_Enabling The UART transmitter can be enabled/disabled by writing logic ‘1’ and ‘0’ respectively to the ‘TX_Enable’ bit.

When the UART transmitter is disabled all data written to the UART will be buffered (buffer space permitting) and will only be sent out when the transmitter in enabled. This feature allows the user to load the transmitter buffer with a ‘Packet’ of information and then send it all in one continuous data stream. If the transmitter is in the process of sending a byte when TX is disabled, then the current byte is sent normally, and then the disable takes effect.

12.1.4 TX_2StopBits The UART format can be changed between 8N1 and 8N2 by writing ‘0’ and ‘1’ respectively to the ‘TX_2StopBits’ bit. Sending 2 stop bits can sometimes be useful for providing some extra 'inter-character delay' even for receivers capable of receiving just 1 stop bit. (NOTE: the receiver only requires 1 stop bit irrespective of this bit setting, but the receiver will obviously accept frames with more than 1 stop bit).

12.1.5 TX_Break The transmit ‘Break’ function will immediately force the TXD pin ‘low’ for as long as the ‘TX_Break’ bit is set at ‘1’.

Any data transmission in progress will continue to function in the background, hence in this condition all bits being transmitted whist the ‘TX_Break’ is high will be lost. If this is not desired, use break combined with TX enabling/disabling.

12.1.6 Flags The ‘USER_IO_UART_O_CTRL_ADDR’ contains the below read flags:

Flag Name Read/Write Description

TX_Done_Event1 Read/Write The transmitter has just sent the last stop bit and there is no more data available in the transmit buffer. The transmitter may still be sending data from it’s transmit shift register even though the transmit buffer may be empty. This flag can be used to indicate that the transmit buffer is empty AND that there is no data 'on the wire' in the process of being transmitted.

RX_OverRun_Event1 Read/Write The receiver has just received a good frame (start bit, data, & valid stop bit) but the receive buffer was full

RX_Framing_Event1 Read/Write The receiver has just received a frame but the stop bit was invalid (start bit, data, & invalid stop bit). If a frame is received with no stop bit the data is NOT written to the buffer.

1 Bit is set to '1' by the event, it remains set until cleared. Writing a '1' to this bit will clear this event.


12.2 Transmitting Data for transmission is provided to the UART by writing data to bits 7 to 0 of the ‘USER_IO_UART_0_DATA_ADDR’ register.


15 Read Only RX_Buffer_Empty This bit gives live status of the receive buffer empty status. 0 = not empty, 1 = empty. An empty buffer may be read with no effect, but the data value read is undefined. This bit may be useful when continuously reading data to detect if all the data in a 'block' has been read, and/or if the value just read is valid or if it should be ignored and thrown away.

14 Read Only RX_OverRun_Event This bit is a read-only copy of the same named bit in the 'CTRL_ADDR' of the UART. This bit may be useful when continuously reading data to detect if data has been lost and the operation should be aborted or retried

13 Read Only RX_Framing_Event This bit is a read-only copy of the same named bit in the 'CTRL_ADDR' of the UART. This bit may be useful when continuously reading data to detect if data has been corrupted and the operation should be aborted or retried.


7 to 0 Read/Write UART Data Write data to the transmit buffer, or read data from the receive buffer.

12.2.1 TX Buffering Transmit data is buffered by a 2048byte (2K) FIFO buffer, the control/status of the transmit buffer can be written/read from the ‘USER_IO_UART_0_TX_BUFF_ADDR’ register as below:


15 Read/Write TX_SizeRead_Enable This bit may be set to '1' to allow the size of the TX buffer to be read from bits 12 down to 0 of this address. When this bit is '0' (Default) the number of 'Free' bytes in the TX buffer can be read from bits 12 down to 0 of this address.


12 to 00 Read Only TX_FreeBytes IF(TX_SizeRead_Enable = 0) Reports the number of 'Free' bytes (i.e. the space available) in the transmitter FIFO buffer. IF(TX_SizeRead_Enable = 1) Reports the size of the TX Buffer in bytes

00 Write Only TX_Buffer_Flush If '1' is written to this bit then the TX FIFO is 'flushed'. Writing '1' to this bit is a one-shot event and the bit does not latch and does not need to be written back to '0'.


12.3 Receiving Data is received from the UART by reading data from bits 7 to 0 of the ‘USER_IO_UART_0_DATA_ADDR’ register.

When reading this register the user is provided with useful flags to help determine data availability & integrity:


15 Read Only RX_Buffer_Empty This bit gives live status of the receive buffer empty status. 0 = not empty, 1 = empty. An empty buffer may be read with no effect, but the data value read is undefined. This bit may be useful when continuously reading data to detect if all the data in a 'block' has been read, and/or if the value just read is valid or if it should be ignored and thrown away.

14 Read Only RX_OverRun_Event This bit is a read-only copy of the same named bit in the 'CTRL_ADDR' of the UART. This bit may be useful when continuously reading data to detect if data has been lost and the operation should be aborted or retried

13 Read Only RX_Framing_Event This bit is a read-only copy of the same named bit in the 'CTRL_ADDR' of the UART. This bit may be useful when continuously reading data to detect if data has been corrupted and the operation should be aborted or retried.


7 to 0 Read/Write UART Data Write data to the transmit buffer, or read data from the receive buffer.

12.3.1 RX Buffering Received data is buffered by a 2048byte (2K) FIFO buffer, the control/status of the received buffer can be written/read from the ‘USER_IO_UART_0_RX_BUFF_ADDR’ register as below:

Bit Read/Write Description

15 Read/Write RX_SizeRead_Enable This bit may be set to '1' to allow the size of the RX buffer to be read from bits 12 down to 0 of this address. When this bit is '0' (Default) the number of 'Used' bytes in the RX buffer can be read from bits 12 down to 0 of this address.


12 to 0 Read Only RX_UsedBytes IF(RX_SizeRead_Enable = 0) Reports the number of 'Used' bytes (i.e. the number of bytes received) in the receive FIFO buffer. IF(RX_SizeRead_Enable = 1) Reports the size of the RX Buffer in bytes

0 Write Only RX_Buffer_Flush If '1' is written to this bit then the RX FIFO is 'flushed'. Writing '1' to this bit is a one-shot event and the bit does not latch and does not need to be written back to '0'.


12.4 UART Addresses The UART function is common among all J-Testr bus connected peripheral cards hence their base addresses can be found in the information address (0x00) at the index location 0x12.

The UART Generator addresses are in a block of 4 as below:

USER_IO_UART_0_CTRL_ADDR = Base address

USER_IO_UART_0_DATA_ADDR = Base address + 1

USER_IO_UART_0_RX_BUFF_ADDR = Base address + 2

USER_IO_UART_0_TX_BUFF_ADDR = Base address + 3 This scheme of providing the function base address via the fixed 'information' address helps support common drivers across all peripheral cards whilst allowing the base address to be different on other peripheral cards if necessary in future designs.


13 SPI Function

A general purpose SPI master function allows for communications with user defined components added to the interposer or communications to the UUT itself. The SPI master function has been designed to be extremely flexible giving the user full control over the following SPI parameters:

Clock Frequency, Polarity, and Phase Data bit quantity from 1 bit to infinite Most or least significant bit transmitted/received first Direct or automatic control over the nCS line Adjustable nCS to SClk Setup and SClk to nCS Hold Delay

13.1 User IO Pin Configuration for SPI The SPI signals can be configured on either the most significant nibble or the least significant nibble of the User IO’s in the fixed User IO locations as below:

User IO Pin SPI Function IO Configuration

7 MISO (Master In/Slave Out) Hi-Z input only

6 MOSI (Master Out/Slave In) Push/pull output

5 SClk (Serial Clock) Push/pull output

4 nCS (Active-low Chip Select) Push/pull output

3 MISO (Master In/Slave Out) Hi-Z input only

2 MOSI (Master Out/Slave In) Push/pull output

1 SClk (Serial Clock) Push/pull output

0 nCS (Active-low Chip Select) Push/pull output

Writing ‘SPI 0 Select’ (0x6) to the appropriate User IO alternative function selection register will select the SPI function as shown in the table above. This mechanism allows each SPI signal type to be assigned to two User IO locations. If two User IOs are assigned with the same SPI output signal (nCS/SClk/MOSI), then the SPI signal is output from both of the User IO pins. If two User IOs are assigned with the same SPI input signal (MISO), then the lower numbered User IO takes priority and is used. E.g. if MISO is assigned on BOTH User IOs 3 & 7, then User IO 3 is used as MISO and User IO 7 is ignored. If no User IO is associated with MISO, then the received value defaults to ‘0’.

13.2 SPI Configuration The SPI function is configured using the ‘USER_IO_SPI_0_CTRL_ADDR’ register as detailed in the below figure: NOTE: Writing this register will immediately override any SPI data transfer that may be in progress, reset the SPI state machine, clear any received data, and de-assert nCS.

(Reserved bits should be written as '0' for future compatibility.)

Rese

rved

SClk

_Pha

SClk

_Fre

q

SClk

_SH

D

Rese

rved

HSB LSB

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

USER_IO_SPI_0_CTRL_ADDR

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

Rese

rved

SClk

_Pol


13.2.1 Serial Clock Frequency The SPI function supports 16 different serial clock frequencies via the ‘SClk_Freq’ bits as shown in the below table:

SClk_Freq Value

(Decimal)

SPI Frequency (MHz)

0 0.100 (Default)

1 0.250

2 0.500

3 0.758

4 1.000

5 1.250

6 1.563

7 2.083

8 2.500

9 3.125

10 4.167

11 5.000

12 6.250

13 8.333

14 12.500

15 25.0001

1 25.00MHz operation is not recommended due to the 100R protection resistor on the User I0s potentially slowing the signal edges too much. However 25.00MHz operation may be possible (if necessary) with careful layout and short traces.

13.2.2 Serial Clock Polarity and Phase The SPI serial engine supports all SPI modes of operation as shown in the waveforms below:

Figure 1 - SPI Clock Polarity and Phase

The ‘SClk_Pol’ bit controls the ‘polarity’ of the serial clock as below:

0 -> Serial clock idle state is low. 1 -> Serial clock idle state is high.


The ‘SClk_Pha’ bit controls the ‘phase’ when data will be propagated and sampled as below:

0 -> Data is sampled first, then propagated. 1 -> Data is propagated first, then sampled.

13.2.3 Serial Clock Setup and Hold Delay The delays between the active-low chip select (nCS) line going low and the first clock edge (Setup delay) and between the last clock edge and the chip select line going high (Hold delay) can be adjusted using the ‘SClk_SHD’ bits.

The table below show the available options.

SClk_SHD Value

(Decimal)

Setup/Hold Delay

0 0.5 SPI Clock Period (Default)

1 1 SPI Clock Period

2 2 SPI Clock Periods

3 3 SPI Clock Periods

Normally the default 0.5 SPI clock period is sufficient for the setup and hold delay, however if the nCS line is heavily loaded or the SPI clock is being run fast then adding extra delay may help improve communication reliability.

13.3 SPI Data Communications Once the SPI function has been configured, all data communication can be handled from the ‘USER_IO_SPI_0_DATA_ADDR’ register shown below:

Rese

rved

Dat

a

Rese

rved

HSB LSB

Bit 0

Bit 2

Bit 1

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 9

Bit 1

1

Bit 1

0

Bit 1

2

Bit 1

3

Bit 1

4

Bit 1

5

Bit 8

USER_IO_SPI_0_DATA_ADDR

nCS_

Req

Go_

Busy

MSB

itNum

MSB

it1st

This register provides the below features during the SPI communication:

Data value to transmit (Write) and data value received (Read). Data bit quantity to be sent & received. (Read/Write) Data transfer bit order. (Read/Write) nCS control. (Read/Write) Data transfer ‘Busy’ status (Read), and data transfer ‘Go’ control (Write).


13.3.1 Data Value, Size & Bit-Order Control The data to be transmitted by the SPI function is written to the ‘Data’ bits situated in the LSB of the ‘USER_IO_SPI_0_DATA_ADDR’ register. Data received by the SPI master function can subsequently be read from this register. The received data is only valid/available to read after a transfer has been completed.

In most applications the data transfer size is some multiple of 8-bit bytes. However, if this is not the case, the user is able to select the most significant bit of the ‘Data’, effectively shortening its size, by setting the 3bit value in the ‘MSBitNum’ location as below:

MSBitNum Value

(Decimal)

Bits Amount

Sent

Actual Bits Sent

0 1 0

1 2 0,1

2 3 0,1,2

3 4 0,1,2,3

4 5 0,1,2,3,4

5 6 0,1,2,3,4,5

6 7 0,1,2,3,4,5,6

7 8 (All Bits) 0,1,2,3,4,5,6,7

Even though most SPI protocols transmit data with the most significant bit (MSb) first, the SPI function does give the option for the data to be transmitted/received with the least significant bit (LSb)first for applications that require it. This is controlled by the MSBit1st bit as below:

MSBit1st Bit Effect

0 Least significant bit (always bit #0) transmitted first

1 Most significant bit (defined by ‘MSBitNum‘) transmitted first

13.3.2 nCS Control When the ‘Go_Busy’ bit is written as ‘0’, the nCS line can be directly controlled using the ‘nCS_Req’ bit of the ‘USER_IO_SPI_0_DATA_ADDR’ register without triggering a data transfer (ie with no SClk or MOSI transitions). Writing ‘nCS_Req’ as ‘1’ will make the nCS output ‘High’, and writing ‘0’ will make the nCS output ‘Low’. This feature is sometimes useful for applications that require the nCS to be activated for a long time before a data transfer is started, or for a long time after a data transfer is completed. An example of this is an ADC that requires the nCS line to be asserted first to activate a conversion, with a long delay to allow the conversion to complete before retrieving the data.

When the ‘Go_Busy’ bit is written as ‘1’, the nCS line can be automatically controlled using the ‘nCS_Req’ bit of the ‘USER_IO_SPI_0_DATA_ADDR’ register whilst an associated data transfer occurs. In this automatic control mode, the nCS line is always made/kept low before the data transfer starts, and the ‘SClk_SHD’ setup/hold delay is automatically applied between nCS being asserted and the first edge of SClk, and between the last edge of SClk and nCS being de-asserted. The value of the ‘nCS_Req’ bit indicates what state to leave the nCS line in after the transfer is completed.


13.3.3 Data Transfer Control When read, the ‘Go_Busy’ bit indicates if the SPI function is currently ‘Busy’ transmitting/receiving data. This ‘Busy’ flag should always be read & checked for ‘Not Busy’ before writing to the ‘USER_IO_SPI_0_DATA_ADDR’ register. Anything written to the ‘USER_IO_SPI_0_DATA_ADDR’ register whilst 'Busy' is active is IGNORED and LOST. Similarly, any of the data read from the lower 8 bits of ‘USER_IO_SPI_0_DATA_ADDR’ whilst 'Busy' is active is undefined and invalid.

When written, the ‘Go_Busy’ bit acts as a ‘Go’ bit to trigger a data transfer. Writing ‘1’ triggers a data transfer, and writing ‘0’ allows direct control of the nCS line without a data transfer.

Data is transmitted/received by writing the ‘Go_Busy’ bit to ‘1’ when writing the data and other parameters to the same register. Upon setting this bit the SPI function will take automatic control of the nCS line depending on the current state of the nCS line and the state of the ‘nCS_Req’ bit as below:

nCS_Req bit Effect when ‘Go_Busy’ bit is written as ‘0‘ (Direct control of nCS)

0 Make (or keep) nCS low.

1 Make (or keep) nCS high.

nCS_Req bit Effect when ‘Go_Busy’ bit is written as ‘1‘ (Automatic control of nCS)

0 Make (or keep) nCS low,

If nCS was previously high, delay by the ‘SClk_SHD’ value before issuing the first SClk edge,

Transmit & receive all the requested data bits,

Keep nCS low.

1 Make (or keep) nCS low,

If nCS was previously high, delay by the ‘SClk_SHD’ value before issuing the first SClk edge,

Transmit & receive all the requested data bits,

Delay by the ‘SClk_SHD’ value from the last SClk edge,

Make nCS high.

If automatic de-activation of nCS is required:- When sending multiple data blocks (i.e. whole 8-bit bytes or N-bit ‘blocks’) only the last data block should be written with the ‘nCS_Req’ bit set to ‘1’ (and ‘Go_Busy’ = ‘1’). However, if only a single data block is required, then the first, and only, block should be written with the ‘nCS_Req’ bit set to ‘1’ (and ‘Go_Busy’ = ‘1’). Effectively, setting the ‘nCS_Req’ bit set to ‘1’ indicates the last data block is being written so that the SPI function knows to ‘automatically’ make the nCS line high when the data transfer has completed.

If ‘manual’ de-activation of nCS is required:- Send all blocks of data with ‘nCS_Req’ bit set to ‘0’ and then at an appropriate time later use direct ‘manual’ control of nCS to de-asstert nCS by writing the ‘Go_Busy’ bit is as ‘0’ and the ‘nCS_Req’ bit as ‘1’.

Note: The ‘Go_Busy’ and ‘nCS_Req’ bits, and the data value/size/bit-order parameters, must always be written to the desired value in the same single write when triggering a SPI transmit/receive or when directly controlling nCS. Otherwise unexpected effects may be seen with nCS. i.e. writing code in a way that does multiple writes to the ‘USER_IO_SPI_0_DATA_ADDR’ to manipulate individual sections/bits of the register may produce unexpected and undesired effects.


13.3.4 Example SPI Communication

If we consider the above SPI waveform we will setup the SPI engine to send the required 24-bit Data with a value 0xAA55FF at a frequency of 5MHz.

From the waveform we can see that the data is to be sent with:

Clock polarity of ‘0’ Clock phase of ‘1’ Setup and hold delay of 0.5 SPI clock period Most significant bit first

Procedure (not including User IO Alt Function setup for SPI)

Set ‘USER_IO_SPI_0_CNTR_ADDR’ to 0b 0000 0000 0010 1011 (0x002B) Reserved = 0000 0000 - Write ‘0’s for future compatibility

SClk_SHD = 00 - SClk setup and hold = 0.5 Clks SClk_Pha = 1 - SClk phase is ‘1’ SClk_Pol = 0 - SClk polarity is ‘0’ SClk_Freq = 1011 (Decimal=11) - SClk Frequency is 5MHz

Set ‘USER_IO_SPI_0_DATA_ADDR’ to 0b 1000 1111 1010 1010 (0x8FAA) Go_Busy = 1 - ‘Go’ send Data nCS_Req = 0 - Keep the nCS low after sending

Reserved = 00 - Write ‘0’s for future compatibility MSBit1st = 1 - Send the data most significant bit first

MSBitNum = 111 - Most significant bit is bit 7 (Send all 8 bits) Data = 10101010 - Data = 0xAA

Read ‘Go_Busy’ Bit until ‘0’ (or appropriate delay), and optionally store received data value.

Set ‘USER_IO_SPI_0_DATA_ADDR’ to 0b 1000 1111 0101 0101 (0x8F55) Go_Busy = 1 - ‘Go’ send Data nCS_Req = 0 - Keep the nCS low after sending


MSBitNum = 111 - Most significant bit is bit 7 (Send all 8 bits) Data = 01010101 - Data = 0x55


Set ‘USER_IO_SPI_0_DATA_ADDR’ to 0b 1100 1111 1111 1111 (0xCFFF) Go_Busy = 1 - ‘Go’ send Data nCS_Req = 1 - Return the nCS high after sending


MSBitNum = 111 - Most significant bit is bit 7 (Send all 8 bits) Data = 11111111 - Data = 0xFF



13.4 SPI Addresses The SPI function is common among all J-Testr bus connected peripheral cards hence its base address can be found in the information address (0x00) at the index location 0x14.

The SPI addresses are in a block of 2 as below:

USER_IO_SPI_0_CTRL_ADDR = Base address

USER_IO_SPI_0_DATA_ADDR = Base address + 1

This scheme of providing the function base address via the fixed 'information' address helps support common drivers across all peripheral cards whilst allowing the base address to be different on other peripheral cards if necessary in future designs.


14 PWM Generator

This Peripheral contains four identical PWM generators that provide the user with a flexible yet simple mechanism to generate PWM signals that can be output from any User IO pin.

14.1 Function The user is able to adjust the ‘duty’ and the ‘period’ of the PWM signals using two 16 bit registers as below: USER_IO_PWM_?_PERIOD_ADDR

USER_IO_PWM_?_DUTY_ADDR The ‘USER_IO_PWM_?_PERIOD_ADDR’ address sets the period of the PWM in 20nS increments, this if effectively the value at which a free running counter for each PWM will wrap and start again at zero. The ‘USER_IO_PWM_?_DUTY_ADDR’ address sets the count value at which the PWM changes the PWM output bit state from high (1) to low (0). The logic is: -

IF (Free-running-counter < Duty) THEN PWM O/P = Hi, else PWM O/P = Lo.

E.g. for period set to 99 decimal (count 0-99-0-99-0....) (counting 0 to 99 = 100 clocks of 20nS = 2uS period) Setting a duty of 37 decimal gives a High PWM O/P for 37 clocks of 20nS (on counts 0-36) and a Low PWM O/P for 63 clocks of 20nS (on counts 37-99).

Setting Duty of zero (0) gives solid Low O/P

Setting Duty > Period gives solid High O/P (which is possible for all periods except 65,535 since both period and duty are limited to 16 bit numbers) The PWM Generator gives the ability to have a high speed low resolution PWM or a low speed very high 16Bit resolution PWM by controlling the value set in the ‘USER_IO_PWM_?_PERIOD_ADDR’ register.

Examples:

100 Bit PWM Generator (0 to 99)

USER_IO_PWM_?_PERIOD_ADDR = 99

USER_IO_PWM_?_DUTY_ADDR = 0 to 100 (>100 can be set but makes no difference)

Frequency = 100 x 20nS = 500KHz



USER_IO_PWM_?_DUTY_ADDR = 0 to 256 (>256 can be set but makes no difference)

Frequency = 256 x 20nS = 195,31KHz



USER_IO_PWM_?_DUTY_ADDR = 0 to 65535 (cannot set > 65535 since register is 16-bit)

Frequency = 65536 x 20nS = 762.94Hz


14.2 PWM Generator Addresses The PWM Generator function is common among all J-Testr bus connected peripheral cards hence their base addresses can be found in the information address (0x00) at the index location 0x11.

The PWM Generator addresses are in a block of 8 as below:

USER_IO_PWM_0_PERIOD_ADDR = Base address

USER_IO_PWM_0_DUTY_ADDR = Base address + 1

USER_IO_PWM_1_PERIOD_ADDR = Base address + 2





USER_IO_PWM_3_DUTY_ADDR = Base address + 7 This scheme of providing the function base address via the fixed 'information' address helps support common drivers across all peripheral cards whilst allowing the base address to be different on different peripheral cards if necessary for future designs.

15 User EEPROM

The CARS Peripheral card, like all J-Testr peripheral cards, contains a 4K byte EEPROM where the bottom half is reserved for J-Testr system and the top half is available for the user.

Figure 2 shows the memory map for the EEPROM.

Figure 2 - EEPROM Memory Map

This EEPROM area can be used for whatever purpose the user deems fit, examples would usage data, asset number, etc.

Access to the Peripheral EEPROM is only via the system motherboard; please consult the J-Testr Motherboard Technical Data for details


16 Electrical Characteristics

Min Typ. Max Comments

RS4xx Transceiver

Differential Driver Output (No Load)

- - 5V

Differential Driver Output (RS-422) 1.75V - - RDIFF = 100 Ohm

Differential Driver Output (RS-485) 1.25V - - RDIFF = 54 Ohm

Driver Common-Mode Output Voltage

- - 3V

Input Current (A and B) - - +125uA

-75uA

VIN = 12V

VIN = -7V

Output Leakage (Y and Z) Full Duplex

- - +125uA

-100uA

VIN = 12V

VIN = -7V

Receiver Maximum Common Mode Input Voltage

+/-10V Higher common mode voltage will start to activate on-board protection circuitry

Receiver Differential Threshold Voltage

-200mV -125mV -50mV -7V ≤ VCM ≤ +12V

Receiver Input Hysteresis - 25mV -

Receiver Input Resistance 96K Ohms - - -7V ≤ VCM ≤ +12V

Driver Rise or Fall Time (115Kbps) 667ns 1320ns 2500ns RDIFF = 54Ω, CL1 = CL2 = 100pF

Driver Skew (115Kbps) -3ns +/-200ns

Driver Rise or Fall Time (500Kbps) 200ns 530ns 750ns RDIFF = 54Ω, CL1 = CL2 = 100pF

Driver Skew (500Kbps) -3ns +/-100ns

Driver Rise or Fall Time (10Mbps) 14ns 25ns RDIFF = 54Ω, CL1 = CL2 = 100pF

Driver Skew (10Mbps) -2.5ns +/-10ns

Selectable Termination 115Ohms 120.8 Ohms 125 Ohms Both AB and YZ Differential Pairs

Protection Impedance - 7.1ohm 8.2ohm For each RX and TX line

CAN Transceiver

CANH dominant output voltage 3V 3.6V 4.25V RDIFF = 60 Ω

CANL dominant output voltage 0.5V 1.4V 1.75V RDIFF = 60 Ω

Dominant differential output voltage

1.5V - 3V 45 Ω < RDIFF < 65 Ω, RCM1 = RCM2 = 300 Ω

Recessive differential output voltage

-50mV 0 50mV No Load

Recessive output voltage 2 2.55 3 No Load

Dominant differential input voltage

0.9V - - − 12 V < VCANH, VCANL < + 12 V

Recessive differential input voltage

- 0 0.5V − 12 V < VCANH, VCANL < + 12 V

Differential input hysteresis - 70mV - − 12 V < VCANH, VCANL < + 12 V

Short circuit output current -200mA

-

-

-

-

200mA

VCANH = -58 V

VCANL = +58 V

Maximium Bit Rate - - 1000KHz

Selectable Termination 115Ohms 120.8 Ohms 125 Ohms

Protection Level -58V - +58V


ARINC429 Transceiver

ARINC output voltage (Ref to GND)

One or Zero

Null

4.5V

-0.25V

5V

-

5.5V

+2.5V

No load and magnitude at pin

ARINC output voltage (Differential)

One or Zero

Null

9V

-0.5V

10V

-

11V

+0.5V

No load and magnitude at pin

ARINC output current 80mA - - Momentary current

Differential Input Voltage

ONE

ZERO

NULL

6.5V

-13.0V

-2.5V

10

-10

0

13

-6.5

2.5

Common mode voltages < 30V

Input Resistance

Differential

To GND

To VDD

-

-

-

140Kohms

140Kohms

100KOhms

-

-

-

Input Current

Input Sink

Input Source

-

-450uA

-

-

200uA

-

Input Capacitance - - 20pF

User IO Logic Levels (Fixed 3.3V IO)

High-level input (VIH) 2.0V - 5.5V Level shifter provides 5V tolerance.

Low-level input (VIL) -0.5V - 0.8V

Input Leakage Current (ILI) -15uA - +15uA 0V =< Vin <= 5V

High-level Output voltage (VOH) 2.4V 3.3V – 150mV/mA

3.4V Min value @IOH source = 3.5mA

High-level source current (IOH) - - 3.5mA

Low-level Output voltage (VOL) - 0V+

120mV/mA

0.65V Max value @IOL sink = 3.5mA

Low-level sink current (IOL) - - 3.5mA

IO Protection

Default Protection limits -2V - 8V Extendable - See section Error! Reference source not found. Error! Reference source not found.

Protection time - 10s -

User EEPROM Space

Memory Space (Bytes) - 2K -

Memory Address range 0x800 - 0xFFF

Data Retention (Years) 200 - -

Endurance (Million erase / write cycles)

1 - -

Misc.

Plug Cycles - - 100


17 Control Registers

All registers in the J-Testr system are addressed as 16bits wide values. The below acronyms and symbols will be used in this section: LSB = Lower Byte of the 16Bit register

HSB = Higher Byte of the 16Bit register

<R/W> = Read / Write

<R> = Read Only

<W> = Write Only

17.1 Register Descriptions

17.1.1 FPGA_INFORMATION_ADDR This location allows reading of various FPGA version numbers, function base addresses, and other information.

LSB => Information Data Out/In <R/W>

HSB => Information Index <R/W> (Default = 0x00)

Writing to the HSB selects the information ‘index’ required to be read. Once written, the requested information will be available for reading on the LSB.

The FPGA_INFORMATION_ADDR and all information indexes are fixed and common among all bus connected J-Testr peripheral cards allowing common driver/routine support.

Information Indexes:

0x00 -> Card Type LSB 0x01 -> Card Type HSB 0x02 -> Firmware Major Version 0x03 -> Firmware Minor Version 0x04 -> Firmware Variant LSB 0x05 -> Firmware Variant HSB 0x06 – 0x08 -> Reserved1 0x09 -> Common function TEMPERATURE_SENSORS_ADDR address location2 0x0A – 0x0F -> Reserved1 0x10 -> Common function USER_IO_OP_PIN_ADDR address location (User IO Base Address) 2 0x11 -> Common function USER_IO_PWM_0_PERIOD_ADDR address location (PWM Base Address) 2 0x12 -> Common function USER_IO_UART_0_CTRL_ADDR address location (UART Base Address) 2 0x13 -> Reserved1

0x14 -> Common function USER_IO_SPI_0_CTRL_ADDR address location (SPI Base Address) 2 Ox15– 0xfe -> Reserved1 0xFF -> Information Out = inverted Information In (can be used for basic bus test) 1 Reserved index locations return values are undefined. 2 If a 'Common Function' index location returns 0x00 then this common function is not available in the installed Firmware.


17.1.2 COMS_MASTER_CONTROL_ADDR Communications Master Control Register

Bits 15-12 => Unused <Write as '0’ for future compatibility> Bit 11 => RX4xx_1_MRst_Act <R> 1= RX4xx_1 Master Reset Actually Active

0= RX4xx_1 Master Reset Actually In-active Bit 10 => RX4xx_1_MRst_Req <R/W> 1= RX4xx_1 Master Reset Request Active

0= RX4xx_1 Master Reset Request In-active (Default = 1)

Bit 09 => RX4xx_0_MRst_Act <R> 1= RX4xx_0 Master Reset Actually Active 0= RX4xx_0 Master Reset Actually In-active

Bit 08 => RX4xx_0_MRst_Req <R/W> 1= RX4xx_0 Master Reset Request Active 0= RX4xx_0 Master Reset Request In-active (Default = 1)

Bits 07-06 => Unused <Write as '0’ for future compatibility> Bit 05 => ARINC_MRst_Act <R> 1= ARINC Master Reset Actually Active

0= ARINC Master Reset Actually In-active Bit 04 => ARINC_MRst_Req <R/W> 1= ARINC Master Reset Request Active

0= ARINC Master Reset Request In-active (Default = 1)

Bits 03-02 => Unused <Write as '0’ for future compatibility> Bit 01 => CAN_MRst_Act <R> 1= CAN Master Reset Actually Active

0= CAN Master Reset Actually In-active Bit 00 => CAN_MRst_Req <R/W> 1=CAN Master Reset Request Active

0= CAN Master Reset Request In-active (Default = 1)

(See section 4 Transceivers Master Reset Control)

17.1.3 CAN_?_CONTROL_ADDR CAN Transceiver Control Register Bit 15 => GP2 <R> 1= HI-3110 GP2 Line ‘High’ 0= HI-3110 GP2 Line ‘Low’ Bit 14 => GP1 <R> 1= HI-3110 GP1 Line ‘High’ 0= HI-3110 GP1 Line ‘Low’ Bit 13 => Stat <R> 1= HI-3110 Stat Line ‘High’ 0= HI-3110 Stat Line ‘Low’ Bit 12 => Int <R> 1= HI-3110 Int Line ‘High’ 0= HI-3110 Int Line ‘Low’ Bits 11-03 => Unused <Write as '0’ for future compatibility> Bit 02 => TXEn <R/W> 1= HI-3110 TXEn Line driven ‘High’ (Enabling Transmit)

0= HI-3110 TXEn Line driven ‘Low’ (Default = 0)

Bit 01 => TermEn_Act <R> 1= CAN Termination ‘Actually’ Enabled 0= CAN Termination ‘Actually’ Disabled

Bit 00 => TermEn_Req <R/W> 1= CAN Termination ‘Requested’ to be Enabled 0= CAN Termination Disabled (Default = 0)

(See section 0


HW Status Bits, 6.3 HW Transmit Enable and 0


Termination)

17.1.4 CAN_?_COMMAND_ADDR CAN Transceiver Command Register

Bit 15 => Go_Busy <R> 1= Currently ‘Busy’ sending command to HI-3110 0= Not Busy, clear to send command <W> 1= Send Command to HI-3110 0= Do Nothing (Default 0) Bit 14 => Cmd_Err <R> 1= Command Error (Invalid OpCode or DLength) 0= No Command Error (Valid OpCode and DLength) Bits 13-08 => DLength <R/W> Number of data bytes to be sent/received to/from

HI-3110 (associated with the OpCode) Bits 07-00 => OpCode <R/W> Command ‘OpCode’ to be written to the HI-3110 (See section 6.6 Data Control Interface)

17.1.5 CAN_?_WR_DATA_BYTES_??to??_ADDR CAN Command Transmit Buffer Registers

The write buffer can only be written when the associated ‘Go_Busy’ bit is indicating NOT busy.

For ALL command transactions with the HI-3110 CAN controller (i.e. BOTH write AND read type OpCodes) these addresses are for specifying the data bytes that will be written to the associated CAN controller during the command transaction. The lower byte (bits 0-7) of the lowest word address is the lowest order byte of the buffer (and is sent first), and the upper byte of the highest word address is the highest order byte of the buffer.

(See section 6.5 Transmit and Receive Data Buffers)

17.1.6 CAN_?_RD_DATA_BYTES_??to??_ADDR CAN Command Receive Buffer Registers

For ALL command transactions with the HI-3110 CAN controller (i.e. BOTH write AND read type OpCodes) these addresses are for reading the data bytes that were read back from the associated CAN controller during the command transaction. The lower byte (bits 0-7) of the lowest word address is the lowest order byte of the buffer (and is received first), and the upper byte of the highest word address is the highest order byte of the buffer.

(See section 6.5 Transmit and Receive Data Buffers)

17.1.7 ARINC_?_CONTROL_ADDR ARINC429 Transceiver Control Register Bit 15 => TFlag <R> 1= HI-3585 TFlag Line ‘High’ 0= HI-3585 TFlag Line ‘Low’ Bit 14 => RFlag <R> 1= HI-3585 RFlag Line ‘High’ 0= HI-3585 RFlag Line ‘Low’ Bits 13-00 => Unused <Write as '0’ for future compatibility> (See section 0


ARINC Transceiver)


17.1.8 ARINC_?_COMMAND_ADDR ARINC429 Transceiver Command Register

Bit 15 => Go_Busy <R> 1= Currently ‘Busy’ sending command to HI-3585 0= Not Busy, clear to send command <W> 1= Send Command to HI-3585 0= Do Nothing (Default 0) Bit 14 => Cmd_Err <R> 1= Command Error (Invalid OpCode or DLength) 0= No Command Error (Valid OpCode and DLength) Bits 13-08 => DLength <R/W> Number of data bytes to be sent/received to/from

HI-3585 (associated with the OpCode) Bits 07-00 => OpCode <R/W> Command ‘OpCode’ to be written to the HI-3585 (See section 0


ARINC Transceiver)

17.1.9 ARINC_?_WR_DATA_BYTES_??to??_ADDR ARINC429 Command Transmit Buffer Registers

The write buffer can only be written when the associated ‘Go_Busy’ bit is indicating NOT busy.

For ALL command transactions with the HI-3585 ARINC429 controller (i.e. BOTH write AND read type OpCodes) these addresses are for specifying the data bytes that will be written to the associated ARINC429 controller during the command transaction. The lower byte (bits 0-7) of the lowest word address is the lowest order byte of the buffer (and is sent first), and the upper byte of the highest word address is the highest order byte of the buffer.

(See section 0


ARINC Transceiver)

17.1.10 ARINC_?_RD_DATA_BYTES_??to??_ADDR ARINC429 Command Receive Buffer Registers

For ALL command transactions with the HI-3585 ARINC429 controller (i.e. BOTH write AND read type OpCodes) these addresses are for reading the data bytes that were read back from the associated ARINC429 controller during the command transaction. The lower byte (bits 0-7) of the lowest word address is the lowest order byte of the buffer (and is received first), and the upper byte of the highest word address is the highest order byte of the buffer.

(See section 0


ARINC Transceiver)


17.1.11 RS4xx_?_CONTROL_0_ADDR RS4xx Transceiver Control Register 0 Bits 15-08 => Unused <Write as '0’ for future compatibility> Bit 07 => NoRX_Of_HDTX < R/W > 1= Disables reception in half duplex mode 0= Reception enabled in half duplex mode (Default = 0) Bit 06 => Half Duplex <R/W> 1= Enables RS485 Half Duplex Operation 0= Enables RS422 Full Duplex Operation

(Default = 1) Bit 05-04 => SlewRate_Select <R/W> 00 = 10Mbps 01 = 500kBps 10 = 115kbps 11 = 115kbps

(Default = 00) Bit 03 => YZTermEn_Act <R> 1= RS4xx YZ Termination ‘Actually’ Enabled

0= RS4xx YZ Termination ‘Actually’ Disabled Bit 02 => YZTermEn_Req <R/W> 1= RS4xx YZ Termination ‘Requested’ to be Enabled

0= RS4xx YZ Termination Disabled (Default = 0)

Bit 01 => ABTermEn_Act <R> 1= RS4xx AB Termination ‘Actually’ Enabled 0= RS4xx AB Termination ‘Actually’ Disabled

Bit 00 => ABTermEn_Req <R/W> 1= RS4xx AB Termination ‘Requested’ to be Enabled 0= RS4xx AB Termination Disabled (Default = 0)

(See sections 5.2 RS422 and RS485 Selection, 5.3 Termination, 5.4 Slew Rate Control and 5.5 Disabling Reception during Transmission)

17.1.12 RS4xx_?_CONTROL_1_ADDR RS4xx Transceiver Control Register 1 Bit 15 => Speed_Select < R/W > 1= High Speed Mode (5ns Clock) 0= Low Speed Mode (620ns Clock) (Default = 1) Bit 14-00 => CksPerBit <R/W> 15-Bit value to select the desired data rate. (Default = 0x5161 = 9600baud)

(See section 5.6 Bit Rate (BAUD) Control)


17.1.13 RS4xx_?_CONTROL_2_ADDR RS4xx Transceiver Control Register 2 Bit 15 => TX_Done_Event1 < R/W > 1= Transmit done event occurred 0= No Event Bit 14 => RX_OverRun_Event1 <R/W> 1= Receive overrun event occurred 0= No Event Bit 13 => RX_Framing_Event1 <R/W> 1= Receive framing error event occurred 0= No Event Bit 12 => RX_Parity_Event1 <R/W> 1= Receive parity error event occurred 0= No Event Bit 11 => TX_Break < R/W > 0 = Normal operational Mode

1= Forces a 'Break' condition (TXD signal forced ‘low’) Bit 10 => Unused <Write as '0’ for future compatibility> Bit 09 => TX_Enable <R/W> 1= Transmitter Enabled

0= Transmitter Disabled (Default = 0)

Bit 08 => RX_Enable < R/W > 1= Receiver Enabled 0= Receiver Disabled (Default = 0)

Bits 07 to 06 => Parity_Select <R/W> 00 = Even 01 = Odd 10 = Space 11 = Mark

(Default = 00) Bit 05 => Parity_Enable <R/W> 1= Parity checking enabled

0= Parity checking disabled (Default = 0)

Bits 04 to 03 => StopLen_Select <R/W> 00 = Send 1 Stop Bit (Receive and Check for 1) 01 = Send 1.5 Stop Bits (Receive and Check for 1.0) 10 = Send 2 Stop Bits (Receive and Check for 1)

11 = Send 2 Stop Bits (Receive and Check for 2) (Default = 00)

Bits 02 to 00 => DataLen_Select <R/W> 000 = 5 Bit Data Length 001 = 6 Bit Data Length 010 = 7 Bit Data Length 011 = 8 Bit Data Length 100 to 111 = 9 Bit Data Length

(Default = 011) 1 Write ‘1’ to clear latched flags

(See sections 5.7 Protocol setup, 5.8 Receiver and Transmitter Enable, 5.9 Break and 5.10 Events)


17.1.14 RS4xx_?_DATA_ADDR RS4xx Transceiver Data register

Bit 15 => RX_Buffer_Empty <R> 1= Receive buffer is empty (The UART Data value is undefined) 0= Receive buffer is not empty

Bit 14 => RX_OverRun_Event1 <R> Bit 13 => RX_Framing_Event1 <R> Bit 12 => RX_Parity_Event1 <R> Bits 11-09 => Reserved. <Write as '0'> Bits 08-00 => UART Data <R/W> 5 to 9-Bit data value.

Write to this address to put the data into the transmit buffer. Read from this address to pull the data out of the receive buffer. The number of bits used depends on how the data length select bits for the UART are configured. Lengths from 5 to 9 are possible. Unused bits written are ignored, and unused bits read will read as 0.

1 Read only copy of the same named bits in register ‘RS4xx_?_CONTROL_2_ADDR’

(See sections 5.11 Data Transition and Reception)

17.1.15 RS4xx_?_RX_BUFF_ADDR RS4xx Transceiver receive buffer information address

Bits 15 => RX_SizeRead_Enable <R> (Default = 0) Bits 14-13 => Reserved. <Write as '0'> Bits 12-00 => RX_UsedBytes1 <R> Bit 00 => RX_Buffer_Flush <W>

1 'UsedBytes' when RX_SizeRead_Enable = ‘0’, or RX_Buffer_Size when RX_SizeRead_Enable = ‘1’.

(See section 5.12.1 RX Buffer)

17.1.16 RS4xx_?_TX_BUFF_ADDR RS4xx Transceiver transmit buffer information address

Bits 15 => TX_SizeRead_Enable <R/W> (Default = 0) Bits 14-13 => Reserved. <Write as '0'> Bits 12-00 => TX_FreeBytes1 <R> Bit 00 => TX_Buffer_Flush <W>

1 'FreeBytes' when TX_SizeRead_Enable = ‘0’, or TX_Buffer_Size when TX_SizeRead_Enable = ‘1’.

(See section 5.12.2 TX Buffer)

17.1.17 USER_IO_PWM_?_PERIOD_ADDR 16-bit PWM period sets the period in 20nS per bit resolution

Bits 15-00 => PWM_Period <R/W> (Default = 0x00)

(See section 14 PWM Generator)


17.1.18 USER_IO_PWM_?_DUTY_ADDR 16-bit PWM duty sets the count at which the PWM period counter changes the PWM O/P bit state.

Bits 15-00 => PWM_Duty <R/W> (Default = 0x00)

(See section 14 PWM Generator)

17.1.19 USER_IO_UART_0_CTRL_ADDR UART Control register

Bits 15-09 => Unused. <Read as '0'> Bit 15 => TX_Done_Event1 <R/W> (See section 12.1.6 Flags) Bit 14 => RX_OverRun_Event1 <R/W> (See section 12.1.6 Flags) Bit 13 => RX_Framing_Event1 <R/W> (See section 12.1.6 Flags) Bit 12 => Reserved. <Write as '0'> Bit 11 => TX_Break < R/W > (Default = 0) (See section 12.1.5 TX_Break) Bit 10 => TX_2StopBits < R/W > (Default = 0) (See section 12.1.4 TX_2StopBits) Bit 09 => TX_Enable < R/W > (Default = 0) (See section 12.1.3 TX_Enabling) Bit 08 => RX_Enable < R/W > (Default = 0) (See section 12.1.2 RX_Enabling) Bits 07-05 => Reserved. <Write as '0'> Bits 04-00 => Baud_Select <R/W> (Default = 0) (See section 12.1.1 Baud Rate Setting)

1 Write ‘1’ to clear latched flags

17.1.20 USER_IO_UART_0_DATA_ADDR UART Data register

Bit 15 => TX_Done_Event <R> (See section 12.3 Receiving) Bit 14 => RX_OverRun_Event1 <R> (See section 12.3 Receiving) Bit 13 => RX_Framing_Event1 <R> (See section 12.3 Receiving) Bits 12-08 => Reserved. <Write as '0'> Bits 07-00 => UART Data <R/W> (See section 12.2 Transmitting and 12.3 Receiving) 1 Read only copy of bits in register ‘USER_IO_UART_0_CTRL_ADDR’

17.1.21 USER_IO_UART_0_RX_BUFF_ADDR UART Receive buffer information address

Bits 15 => RX_SizeRead_Enable <R> (Default = 0) Bits 14-13 => Reserved. <Write as '0'> Bits 12-00 => RX_UsedBytes1 <R> Bit 00 => RX_Buffer_Flush <W>

1 'UsedBytes' when RX_SizeRead_Enable = ‘0’, or RX_Buffer_Size when RX_SizeRead_Enable = ‘1’.

(See section 12.3.1 RX Buffering)


17.1.22 USER_IO_UART_0_TX_BUFF_ADDR UART Transmit buffer information address

Bits 15 => TX_SizeRead_Enable <R/W> (Default = 0) Bits 14-13 => Reserved. <Write as '0'> Bits 12-00 => TX_FreeBytes1 <R> Bit 00 => TX_Buffer_Flush <W>

1 'FreeBytes' when TX_SizeRead_Enable = ‘0’, or TX_Buffer_Size when TX_SizeRead_Enable = ‘1’.

(See section 12.2.1 TX Buffering)

17.1.23 USER_IO_SPI_0_CTRL_ADDR SPI Control address

Bits 15-08 => Reserved. <Write as '0'> Bits 07-06 => SPI Serial Clock Setup and Hold Delay <R/W> => 0 - 0.5 SPI Clock period. (Default) => 1 - 1.0 SPI Clock period. => 2 - 2.0 SPI Clock period. => 3 - 3.0 SPI Clock period. Bits 05 => SPI Serial Clock Phase (SClk_Pha) <R/W> Bits 04 => SPI Serial Clock Polarity (SClk_Pol) <R/W> Bits 03-00 => SPI Serial Clock Frequency (SClk_Freq) <R/W> => 0 - 0.1 MHz (Default) => 1 - 0.250 MHz => 2 - 0.500 MHz => 3 - 0.758 MHz => 4 - 1.000 MHz => 5 - 1.250 MHz => 6 - 1.563 MHz => 7 - 2.083 MHz => 8 - 2.500 MHz => 9 - 3.125 MHz => 10 - 4.167 MHz => 11 - 4.167 MHz => 12 - 6.250 MHz => 13 - 8.333 MHz => 14 - 12.500 MHz => 15 - 25.000 MHz (not recommended)

(See section 13.2SPI Configuration)

17.1.24 USER_IO_SPI_0_DATA_ADDR SPI Data address

Bits 15 => Go and Busy Flag (Go_Busy) <R/W> => Go <W> => Busy <R> Bits 14 => Active-Low Chip Select Request (nCS_Req) <R/W> Bits 13-12 => Reserved. <Write as '0'> Bits 11 => Most Significant Bit First (MSBit1st) <R/W> Bits 10-08 => Most Significant Bit Number (MSBitNum) <R/W> Bits 07-00 => Data Out <W> Bits 07-00 => Data In <R>

(See section 13.3 SPI Data Communications)


17.1.25 USER_IO_OP_PIN_ADDR User IO output and pin state register

Bit 15 => UserIO_7 Pin Status <R> Bit 14 => UserIO_6 Pin Status <R> Bit 13 => UserIO_5 Pin Status <R> Bit 12 => UserIO_4 Pin Status <R> Bit 11 => UserIO_3 Pin Status <R> Bit 10 => UserIO_2 Pin Status <R> Bit 09 => UserIO_1 Pin Status <R> Bit 08 => UserIO_0 Pin Status <R> Bit 07 => UserIO_7 Output Bit <R/W> (Default = 1) Bit 06 => UserIO_6 Output Bit <R/W> (Default = 1) Bit 05 => UserIO_5 Output Bit <R/W> (Default = 1) Bit 04 => UserIO_4 Output Bit <R/W> (Default = 1) Bit 03 => UserIO_3 Output Bit <R/W> (Default = 1) Bit 02 => UserIO_2 Output Bit <R/W> (Default = 1) Bit 01 => UserIO_1 Output Bit <R/W> (Default = 1) Bit 00 => UserIO_0 Output Bit <R/W> (Default = 1)

(See section 11 User IO)

17.1.26 USER_IO_MODE_AltFnEn_ADDR User IO mode and alternative function enable register

Bit 15 => UserIO_7 AltFnEn Bit <R/W> (Default = 0) Bit 14 => UserIO_6 AltFnEn Bit <R/W> (Default = 0) Bit 13 => UserIO_5 AltFnEn Bit <R/W> (Default = 0) Bit 12 => UserIO_4 AltFnEn Bit <R/W> (Default = 0) Bit 11 => UserIO_3 AltFnEn Bit <R/W> (Default = 0) Bit 10 => UserIO_2 AltFnEn Bit <R/W> (Default = 0) Bit 09 => UserIO_1 AltFnEn Bit <R/W> (Default = 0) Bit 08 => UserIO_0 AltFnEn Bit <R/W> (Default = 0) Bit 07 => UserIO_7 Mode Bit <R/W> (Default = 0) Bit 06 => UserIO_6 Mode Bit <R/W> (Default = 0) Bit 05 => UserIO_5 Mode Bit <R/W> (Default = 0) Bit 04 => UserIO_4 Mode Bit <R/W> (Default = 0) Bit 03 => UserIO_3 Mode Bit <R/W> (Default = 0) Bit 02 => UserIO_2 Mode Bit <R/W> (Default = 0) Bit 01 => UserIO_1 Mode Bit <R/W> (Default = 0) Bit 00 => UserIO_0 Mode Bit <R/W> (Default = 0)

(See section 11 User IO)


17.1.27 USER_IO_3to0_AltFn_SigSel_ADDR Alternative function signal selection register for UserIOs 3 down to 0

Bits 15-12 => 4-Bit Alternative function signal select for UserIO 3 < R/W> (Default = 0)




PWM Output 0 -> 0x0 PWM Output 1 -> 0x1 PWM Output 2 -> 0x2 PWM Output 3 -> 0x3 UART 0 TX -> 0x4 UART 0 RX -> 0x5 SPI 0 -> 0x6 Reserved -> 0x7 to 0xE GoJSafe -> 0xF

17.2 (See section 11.2


Alternative Function Selection)

17.2.1 USER_IO_7to4_AltFn_SigSel_ADDR Alternative function signal selection register for UserIOs 7 down to 4





Alternate function signal select values:- PWM Output 0 -> 0x0 PWM Output 1 -> 0x1 PWM Output 2 -> 0x2 PWM Output 3 -> 0x3 UART 0 TX -> 0x4 UART 0 RX -> 0x5 SPI 0 -> 0x6 Reserved -> 0x7 to 0xE GoJSafe -> 0xF

17.3 (See section 11.2


Alternative Function Selection)

17.3.1 SCRATCHPAD_ADDR General purpose scratch-pad register (has no function). Cleared to 0x0000 by a system reset.

Bits 15-00 => Scratchpad value <R/W>

(See section 8 Scratchpad Register)


17.3.2 JSAFE_ADDR J-Safe protection system register

Bits 15-05=> Reserved. <Write as '0'> <R>

Bit 04 => UIO_GoJSafe_Event1 <R/W> 1 = Latched User IO ‘Go-JSafe’ Event, 0 = No ‘Go-JSafe’ Event

Bits 03-02=> Reserved. <Write as '0'> <R>

Bit 01 => GoJSafe_TX <R> 1 = J-Safe Transmitted (caused by this device), No J-Safe Transmitted

Bit 00 => GoJSafe_RX <R> 1 = J-Safe being Received, No J-Safe being Received

1 A User IO GoJSafe event can be cleared (back to '0') by writing '1' to this bit once the external cause has been removed.

(See section 10 J-Safe mechanism)


17.4 Memory Map Register Name Address Read / Write Note

FPGA INFORMATION 0x00 R/W

COMS_MASTER_CONTROL_ADDR 0x01 R/W

UNUSED 0x02-0x03

CAN_0_CONTROL_ADDR 0x04 R/W

CAN_0_COMMAND_ADDR 0x05 R/W

CAN_1_CONTROL_ADDR 0x06 R/W

CAN_1_COMMAND_ADDR 0x07 R/W

UNUSED 0x08-0x09

ARINC_0_CONTROL_ADDR 0x0A R/W

ARINC _0_COMMAND_ADDR 0x0B R/W

ARINC _1_CONTROL_ADDR 0x0C R/W

ARINC _1_COMMAND_ADDR 0x0D R/W

UNUSED 0x0E-0x0F

RS4xx_0_CONTROL_0_ADDR 0x10 R/W



UNUSED 0x13

RS4xx_0_DATA_ADDR 0x14 R/W

RS4xx_0_RX_BUFF_ADDR 0x15 R/W

RS4xx_0_TX_BUFF_ADDR 0x16 R/W

UNUSED 0x17



RS4xx_1_CONTROL_2_ADDR 0x1A R/W

UNUSED 0x1B

RS4xx_1_DATA_ADDR 0x1C R/W

RS4xx_1_RX_BUFF_ADDR 0x1D R/W

RS4xx_1_TX_BUFF_ADDR 0x1E R/W

UNUSED 0x1F

CAN_0_WR_DATA_BYTES_00to01_ADDR 0x20 R/W CAN 0 Write Buffer

CAN_0_WR_DATA_BYTES_02to03_ADDR 0x21 R/W










CAN_0_WR_DATA_BYTES_20to21_ADDR 0x2A R/W

CAN_0_WR_DATA_BYTES_22to23_ADDR 0x2B R/W

CAN_0_WR_DATA_BYTES_24to25_ADDR 0x2C R/W

CAN_0_WR_DATA_BYTES_26to27_ADDR 0x2D R/W

CAN_0_WR_DATA_BYTES_28to29_ADDR 0x2E R/W

CAN_0_WR_DATA_BYTES_30to31_ADDR 0x2F R/W

CAN_0_RD_DATA_BYTES_00to01_ADDR 0x30 R CAN 0 Read Buffer

CAN_0_RD _DATA_BYTES_02to03_ADDR 0x31 R


CAN_0_RD_DATA_BYTES_06to07_ADDR 0x33 R







CAN_0_RD_DATA_BYTES_20to21_ADDR 0x3A R

CAN_0_RD_DATA_BYTES_22to23_ADDR 0x3B R

CAN_0_RD_DATA_BYTES_24to25_ADDR 0x3C R

CAN_0_RD_DATA_BYTES_26to27_ADDR 0x3D R

CAN_0_RD_DATA_BYTES_28to29_ADDR 0x3E R

CAN_0_RD_DATA_BYTES_30to31_ADDR 0x3F R

CAN_1_WR_DATA_BYTES_00to01_ADDR 0x40 R/W CAN 1 Write Buffer










CAN_1_WR_DATA_BYTES_20to21_ADDR 0x4A R/W

CAN_1_WR_DATA_BYTES_22to23_ADDR 0x4B R/W

CAN_1_WR_DATA_BYTES_24to25_ADDR 0x4C R/W

CAN_1_WR_DATA_BYTES_26to27_ADDR 0x4D R/W


CAN_1_WR_DATA_BYTES_28to29_ADDR 0x4E R/W

CAN_1_WR_DATA_BYTES_30to31_ADDR 0x4F R/W

CAN_1_RD_DATA_BYTES_00to01_ADDR 0x50 R CAN 1 Read Buffer










CAN_1_RD_DATA_BYTES_20to21_ADDR 0x5A R

CAN_1_RD_DATA_BYTES_22to23_ADDR 0x5B R

CAN_1_RD_DATA_BYTES_24to25_ADDR 0x5C R

CAN_1_RD_DATA_BYTES_26to27_ADDR 0x5D R

CAN_1_RD_DATA_BYTES_28to29_ADDR 0x5E R

CAN_1_RD_DATA_BYTES_30to31_ADDR 0x5F R

ARINC_0_WR_DATA_BYTES_00to01_ADDR 0x60 R/W ARINC 0 Write Buffer

ARINC_0_WR_DATA_BYTES_02to03_ADDR 0x61 R/W









ARINC_0_WR_DATA_BYTES_20to21_ADDR 0x6A R/W

ARINC_0_WR_DATA_BYTES_22to23_ADDR 0x6B R/W

ARINC_0_WR_DATA_BYTES_24to25_ADDR 0x6C R/W

ARINC_0_WR_DATA_BYTES_26to27_ADDR 0x6D R/W

ARINC_0_WR_DATA_BYTES_28to29_ADDR 0x6E R/W

ARINC_0_WR_DATA_BYTES_30to31_ADDR 0x6F R/W

ARINC_0_RD_DATA_BYTES_00to01_ADDR 0x70 R ARINC 0 Read Buffer

ARINC_0_RD _DATA_BYTES_02to03_ADDR 0x71 R



ARINC_0_RD_DATA_BYTES_06to07_ADDR 0x73 R







ARINC_0_RD_DATA_BYTES_20to21_ADDR 0x7A R

ARINC_0_RD_DATA_BYTES_22to23_ADDR 0x7B R

ARINC_0_RD_DATA_BYTES_24to25_ADDR 0x7C R

ARINC_0_RD_DATA_BYTES_26to27_ADDR 0x7D R

ARINC_0_RD_DATA_BYTES_28to29_ADDR 0x7E R

ARINC_0_RD_DATA_BYTES_30to31_ADDR 0x7F R

ARINC_1_WR_DATA_BYTES_00to01_ADDR 0x80 R/W ARINC 1 Write Buffer










ARINC_1_WR_DATA_BYTES_20to21_ADDR 0x8A R/W

ARINC_1_WR_DATA_BYTES_22to23_ADDR 0x8B R/W

ARINC_1_WR_DATA_BYTES_24to25_ADDR 0x8C R/W

ARINC_1_WR_DATA_BYTES_26to27_ADDR 0x8D R/W

ARINC_1_WR_DATA_BYTES_28to29_ADDR 0x8E R/W

ARINC_1_WR_DATA_BYTES_30to31_ADDR 0x8F R/W

ARINC_1_RD_DATA_BYTES_00to01_ADDR 0x90 R ARINC 1 Read Buffer











ARINC_1_RD_DATA_BYTES_20to21_ADDR 0x9A R

ARINC_1_RD_DATA_BYTES_22to23_ADDR 0x9B R

ARINC_1_RD_DATA_BYTES_24to25_ADDR 0x9C R

ARINC_1_RD_DATA_BYTES_26to27_ADDR 0x9D R

ARINC_1_RD_DATA_BYTES_28to29_ADDR 0x9E R

ARINC_1_RD_DATA_BYTES_30to31_ADDR 0x9F R

RESERVED 0xA0-0xBF Manufacturers use only

UNUSED 0xC0-0xDF

USER_IO_PWM_0_PERIOD_ADDR 0xE0 R/W Address in Info 0x11 (Base Address)

USER_IO_PWM_0_DUTY_ADDR 0xE1 R/W

USER_IO_PWM_1_PERIOD_ADDR 0xE2 R/W






USER_IO_UART_0_CTRL_ADDR 0xE8 R/W Address in Info 0x12 (Base Address)

USER_IO_UART_0_DATA_ADDR 0xE9 R/W

USER_IO_UART_0_RX_BUFF_ADDR 0xEA R/W

USER_IO_UART_0_TX_BUFF_ADDR 0xEB R/W

USER_IO_SPI_0_CTRL_ADDR 0xEC R/W Address in Info 0x14 (Base Address)

USER_IO_SPI_0_DATA_ADDR 0xED R/W

UNUSED 0xEE-0xEF

USER_IO_OP_PIN_ADDR 0xF0 MSB: R

LSB: R/W

Address in Info 0x10 (Base Address)

USER_IO_MODE_AltFnEn_ADDR 0xF1 R/W

USER_IO_3to0_AltFn_SigSel_ADDR 0xF2 R/W

USER_IO_7to4_AltFn_SigSel_ADDR 0xF3 R/W

RESERVED 0xF4-0xF7 R Manufacturers use only

SCRATCHPAD_ADDR 0xF8 R/W

RESERVED 0xF9-0xFC R Manufacturers use only

GLOBAL_TRIGGERS_ADDR 0xFD W

JSAFE_ADDR 0xFE R

RESERVED 0xFF R Manufacturers use only


Index

1 FEATURES ........................................................................................................................................................... 1

2 DESCRIPTION ...................................................................................................................................................... 1

2.1 CONNECTIONS ......................................................................................................................................................... 3 2.2 CONNECTOR LOCATION ............................................................................................................................................. 4 2.3 J-TESTR SLOT LOCATION ........................................................................................................................................... 4

3 TRANSCEIVERS MASTER RESET CONTROL ........................................................................................................... 5

4 RS422 / RS485 TRANSCEIVERS ............................................................................................................................ 7

4.1 OVERVIEW.............................................................................................................................................................. 7 4.2 RS422 AND RS485 SELECTION .................................................................................................................................. 7 4.3 TERMINATION ......................................................................................................................................................... 8 4.4 SLEW RATE CONTROL ............................................................................................................................................... 9 4.5 DISABLING RECEPTION DURING TRANSMISSION.............................................................................................................. 9 4.6 BIT RATE (BAUD) CONTROL .................................................................................................................................... 10 4.7 PROTOCOL SETUP ................................................................................................................................................... 11 4.8 RECEIVER AND TRANSMITTER ENABLE ........................................................................................................................ 12 4.9 BREAK ................................................................................................................................................................. 12 4.10 EVENTS ................................................................................................................................................................ 13 4.11 DATA TRANSITION AND RECEPTION ........................................................................................................................... 13 4.12 BUFFERS .............................................................................................................................................................. 14

4.12.1 RX Buffer ................................................................................................................................................... 14 4.12.2 TX Buffer ................................................................................................................................................... 15

5 CAN TRANSCEIVER .............................................................................................................................................16

5.1 OVERVIEW............................................................................................................................................................ 16 5.2 HW STATUS BITS................................................................................................................................................... 17 5.3 HW TRANSMIT ENABLE .......................................................................................................................................... 17 5.4 TERMINATION ....................................................................................................................................................... 18 5.5 TRANSMIT AND RECEIVE DATA BUFFERS ..................................................................................................................... 18 5.6 DATA CONTROL INTERFACE ...................................................................................................................................... 20

5.6.1 Example Communications ......................................................................................................................... 24 5.7 SETTING BIT RATE .................................................................................................................................................. 25

6 ARINC TRANSCEIVER ..........................................................................................................................................26

6.1 OVERVIEW............................................................................................................................................................ 26

7 SCRATCHPAD REGISTER .....................................................................................................................................27

8 GLOBAL TRIGGERS .............................................................................................................................................27

9 J-SAFE MECHANISM ...........................................................................................................................................28

9.1 J-SAFE CONDITION TRIGGERS .................................................................................................................................... 29 9.2 J-SAFE CONDITION RESPONSES.................................................................................................................................. 29 9.3 WORKING WITH J-SAFE ........................................................................................................................................... 29

10 USER IO ..........................................................................................................................................................30

10.1 BASIC IO OPERATION ............................................................................................................................................. 30 10.2 ............................................................................................................................................................................... 30 10.3 ALTERNATIVE FUNCTION SELECTION .......................................................................................................................... 31


10.4 USER IO ADDRESSES .............................................................................................................................................. 32

11 UART FUNCTION ............................................................................................................................................33

11.1 SETUP .................................................................................................................................................................. 33 11.1.1 Baud Rate Setting ..................................................................................................................................... 33 11.1.2 RX_Enabling .............................................................................................................................................. 34 11.1.3 TX_Enabling .............................................................................................................................................. 34 11.1.4 TX_2StopBits ............................................................................................................................................. 34 11.1.5 TX_Break ................................................................................................................................................... 34 11.1.6 Flags .......................................................................................................................................................... 34

11.2 TRANSMITTING ...................................................................................................................................................... 35 11.2.1 TX Buffering .............................................................................................................................................. 35

11.3 RECEIVING ............................................................................................................................................................ 36 11.3.1 RX Buffering .............................................................................................................................................. 36

11.4 UART ADDRESSES ................................................................................................................................................. 37

12 SPI FUNCTION ................................................................................................................................................38

12.1 USER IO PIN CONFIGURATION FOR SPI ...................................................................................................................... 38 12.2 SPI CONFIGURATION .............................................................................................................................................. 38

12.2.1 Serial Clock Frequency............................................................................................................................... 39 12.2.2 Serial Clock Polarity and Phase ................................................................................................................. 39 12.2.3 Serial Clock Setup and Hold Delay ............................................................................................................. 40

12.3 SPI DATA COMMUNICATIONS .................................................................................................................................. 40 12.3.1 Data Value, Size & Bit-Order Control ........................................................................................................ 41 12.3.2 nCS Control ................................................................................................................................................ 41 12.3.3 Data Transfer Control ............................................................................................................................... 42 12.3.4 Example SPI Communication..................................................................................................................... 43

12.4 SPI ADDRESSES ..................................................................................................................................................... 44

13 PWM GENERATOR .........................................................................................................................................45

13.1 FUNCTION ............................................................................................................................................................ 45 13.2 PWM GENERATOR ADDRESSES ................................................................................................................................ 46

14 USER EEPROM ................................................................................................................................................46

15 ELECTRICAL CHARACTERISTICS .......................................................................................................................47

16 CONTROL REGISTERS ......................................................................................................................................49

16.1 REGISTER DESCRIPTIONS ......................................................................................................................................... 49 16.1.1 FPGA_INFORMATION_ADDR .................................................................................................................... 49 16.1.2 COMS_MASTER_CONTROL_ADDR ............................................................................................................ 50 16.1.3 CAN_?_CONTROL_ADDR ........................................................................................................................... 50 16.1.4 CAN_?_COMMAND_ADDR ....................................................................................................................... 52 16.1.5 CAN_?_WR_DATA_BYTES_??to??_ADDR ................................................................................................. 52 16.1.6 CAN_?_RD_DATA_BYTES_??to??_ADDR .................................................................................................. 52 16.1.7 ARINC_?_CONTROL_ADDR ....................................................................................................................... 52 16.1.8 ARINC_?_COMMAND_ADDR .................................................................................................................... 54 16.1.9 ARINC_?_WR_DATA_BYTES_??to??_ADDR .............................................................................................. 55 16.1.10 ARINC_?_RD_DATA_BYTES_??to??_ADDR ........................................................................................... 56 16.1.11 RS4xx_?_CONTROL_0_ADDR ................................................................................................................ 58 16.1.12 RS4xx_?_CONTROL_1_ADDR ................................................................................................................ 58 16.1.13 RS4xx_?_CONTROL_2_ADDR ................................................................................................................ 59


16.1.14 RS4xx_?_DATA_ADDR ........................................................................................................................... 60 16.1.15 RS4xx_?_RX_BUFF_ADDR ..................................................................................................................... 60 16.1.16 RS4xx_?_TX_BUFF_ADDR ..................................................................................................................... 60 16.1.17 USER_IO_PWM_?_PERIOD_ADDR ........................................................................................................ 60 16.1.18 USER_IO_PWM_?_DUTY_ADDR ........................................................................................................... 61 16.1.19 USER_IO_UART_0_CTRL_ADDR ............................................................................................................ 61 16.1.20 USER_IO_UART_0_DATA_ADDR ........................................................................................................... 61 16.1.21 USER_IO_UART_0_RX_BUFF_ADDR ...................................................................................................... 61 16.1.22 USER_IO_UART_0_TX_BUFF_ADDR ...................................................................................................... 62 16.1.23 USER_IO_SPI_0_CTRL_ADDR ................................................................................................................ 62 16.1.24 USER_IO_SPI_0_DATA_ADDR ............................................................................................................... 62 16.1.25 USER_IO_OP_PIN_ADDR ....................................................................................................................... 63 16.1.26 USER_IO_MODE_AltFnEn_ADDR .......................................................................................................... 63 16.1.27 USER_IO_3to0_AltFn_SigSel_ADDR ...................................................................................................... 64 16.1.28 USER_IO_7to4_AltFn_SigSel_ADDR ...................................................................................................... 65 16.1.29 SCRATCHPAD_ADDR ............................................................................................................................. 66 16.1.30 JSAFE_ADDR .......................................................................................................................................... 67

16.2 MEMORY MAP ...................................................................................................................................................... 68

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