US ATLASPHASE II Upgrade

SOW & BASIS of ESTIMATE (SOW & BoE)

Date of Est: 15-November-2015

Prepared by: Venetios Polychronakos V1.0

WBS number: 6.6.2.1 WBS Title: F/E (Front-end) Chip for the new sTGC detectors od the inner ring of the Big Wheel TGC and the new front end for the MDT

Scope of the proposed BNL Phase II Muon Upgrade work The ATLAS Phase II Upgrade “Scoping Document” includes two areas in which the proposed work would contribute:

1. Replacement of the inner ring of the TGC detector in the Big Wheels with sTGC similar to those being built for the New Small Wheels (NSW) of the Phase I upgrade.

2. New front end electronics for the existing MDT chambers in order to handle the new ATLAS Phase II Trigger/DAQ requirements

Building on our Phase-I development of the front end ASIC for both detector technologies of the New Small Wheels Phase-I upgrade we propose to develop and produce a front end suitable for both applications.

For the new sTGC of the Big Wheels the NSW version of the ASIC could, in principle, be used as is. However operating experience and the fact that they would have to work within the existing Level-1 trigger framework may dictate some changes and/or improvements.

For the MDT front ends some small modifications to the existing ASIC need to be made. These are rather minor and straight forward. We believe that one submission should be all that is needed. Note that, because of the large size of the VMM, all our submissions for fabrication are via dedicated runs and, therefore if successful, are also production runs. The Phase I version will already have all features that make it compatible with Phase II trigger and DAQ. Specifically:

1. It can handle the 1MHz Level-0 trigger and DAQ requirements.2. It has a 10 microsecond Level-0 latency buffer.3. It includes a 16-deep Level-0 FIFO4. And it has implemented the trigger BCID matching

All the above features can greatly simplify the design of the new Chamber Service Module (CSM) as will be described later.

The VMM already can digitize both amplitude and time eliminating the need for an additional TDC which does not yet exist. To make this point more clear, Table 1 shows a comparison of the VMM parameters with the current MDT front end (ASD) and, when appropriate, with the combination of the ASD and the TDC of the present design. In bold typeface are noted the modifications of the VMM that are necessary for use as MDT front ends. One can see that there are only two features that need to be added or modified. The peaking time which will improve the timing resolution although at 25 ns is already good enough, and the addition of a

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programmable dead time in order to veto multiple hits within the MDT drift time. Both of these are straight forward modifications.

Table 1 Comparison of VMM and combination ASD+TDC

Parameter ASD TDC VMMChannels 8 24 64Zin(Ohms) 120 50-75Gain [mV/fC] 12 0.5 - 16Gain [mV/pe] 3 0.125 - 4Charge linear range[pe] 500 250 – 8,000Charge resolution ~1 fC ~1 – 2fCShaper bipolar Bipolar (blr) or unipolarShaper order 2nd 3d (complex conjugate)Peaking time ~15 ns 25 – 200 nsPulse width 400 ns 200 – 800 nsDiscrimination yes yesProgrammable dead time 300 – 800 ns To be added for Phase IIThreshold DAC 8-bit 10-bitAmplitude measurement VtoTime (Wilkinson) Direct VoltageAmplitude ADC - 10-bitTime measurement Edge at threshold TAC at peak, Edge in VMM3Time walk <10 ns <2 nsTime resolution 0.2 – 0.8 ns 0.7 ns <1 nsTiming conversion 4-bit TDCTiming Dynamic range 13+4 fine 12 coarse +8 fineL0 Buffer memory 256 64+16 per channelPower per channel 35 mW 20 mW <10 mW

Trigger Primitives and readout at L0 acceptWe now look at the significant design simplification of the CSM by using the VMM front end.Figure 1 shows the block diagram of the proposed CSM. We assume at this point that ATLAS will decide to go to a single level 1 MHz trigger, L0. The decision has not been formalized yet but is expected. Furthermore, for the NSW, it has been decided to design for a single, 1 MHz, Level-0 even in the unlikely event that ATLAS decides to keep the 1 MHz L0, xxxkHz (400?) Level -1 by implementing the Lavel-1 part in software. Note that this is the decision of the NSW community endorsed by TDAQ. So the Level 1 label in Figure 1 is essentially the Level 0. Then note that all the blocks in the CSM are already included in the VMM. More specifically:

1. The trigger primitive (Channel address, time, BCID) is already digitized and 8b/10b encoded, e-link compatible and can be connect directly to a GBT. One GBT, depending on the location of the MDT chamber and the rate, can accommodate from 40 80-Mbps links to 10 320-Mbps links.

2. For the data readout after a level-zero accept the VMM already has a 64-deep latency buffer which can handle L0 latencies of up to 13 microseconds.

3. 16-word readout FIFO4. BCID matching logic.

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Figure 1 The proposed Phase II CSM/front end interface

An example of a simplified CSM conceptual design is shown in Figure 2.

Figure 2/Conceptual CSM schematic using VMM

Cost EstimateThe following assumptions were made in estimating the cost:

1. Technology: GF 130 nm CMOS 8RF-DM (Formerly IBM 8RF-DM) Expected to be

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available for several more years.2. Need 350,000 channels MDT (24 channels/VMM) + 384,000 sTGC (64 ch/VMM)+10%

and a yield of 130 VMM per 12” wafer. Makes a total of 175 wafers in production.3. Assume FY16 BNL labor rates including 34% burden, and 3% escalation for outyears.4. Two spins in custom runs. If first acceptable no second needed.5. Fabrication cost based on FY16 quotes. Note that technology becomes cheaper as it ages.

As an example, in NSW VMM3 is quoted about 20% cheaper than VMM2.6. Most of the design labor, testing firmware, etc. are provided by BNL Instrumentation

division at no cost to the project.7. Major procurements to be executed by a collaborating Institute with no indirect costs (e.g.

Harvard)8. Appended are quotes for fabrication and packaging.

APPENDIX 1

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Block diagram of the VMM ASIC

Key features and design parameters of the VMM ASIC Dual Polarity Adjustable Gain (0.5 – 16.0 mV/fC) Adjustable peaking Time (25-200 ns) Address in Real Time (Fast OR in effect - Mmegas Trigger) Prompt digitized (6-bit) Amplitude, Time-over-threshold, time-to--peak (TGC Trigger) Peak Detector, Time Detector (<1 ns) Discriminators with sub-hysteresis Neighbor enable logic (channel to channel and across ICs) Sparse readout w/smart token passing, Threshold trim, built-in calibration, channel mask, analog monitor, temp. sensor, Band Gap

Reference, 600 +- 150 mV custom LVDS 64 channels with 10-bit ADC for amplitude 8-bit for time. 64 channels ADC with 6-bit amplitude in real time (used in the sTGC trigger) Address of the strip with the earliest signal arrival per bunch crossing, Address in Real Time,

ART, used in the Mmegas trigger (effectively a fast OR) 40 MHz, 12-bit bunch crossing ID counter (BCID) with reset SEU immune 1616- bit configuration register

APPENDIX 2

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APPENDIX 3

IMEC Kapeldreef 75

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B-3001 Leuven, Belgium Ref No.: 150910_BGA_VMM_assepm Sep 10, 2015 CERN Attention: Venetios Polychronakos Subject : Quotation for wirebond assembly in LFBGA400 4L substrate 21x21 Dear Dr. Polychronakos, IMEC is pleased to provide the following price offer for the engineering and production assembly of your project VMM project. ( IBM wafers) A one-time discount of 3,000 USD is applicable on the (first) engineering assembly. Way of Working : 1. Customer generates Netlist, indicating which signals are critical and have special requirements 2. Netlist is reviewed by Imec and agreed upon between Imec and Customer 3. ASE designs the substrate 4. Substrate design is reviewed against the requirements and approved by Imec and Customer 5. ASE manufactures the substrates 6. ASE manufactures the packaged samples

Subcontractor: ASE Assembly Factory Assembly in: LFBGA 400 - 21x21 - 0.8 or 1.0 um pitch 4L substrate ITEM DESCRIPTION PRICE 1 NRE: Bonding scheme

preparation/validation/program 1,700 USD

2 NRE: Substrate design, wire bond (>300 balls)

6,000 USD

3 NRE: Substrate tooling, Wire bond _4_L_ _s_u_b_s_t_r_a_t_e_ _ _Including 1,000 (substrates + assemblies) for engineering assemblies. ( substrates valid for one year only ) _If more assemblies with the identical substrate are expected within 12months, it is advised to order additional substrates upfront at 1.61 USD/pc.

7,500 USD

4 NRE: Manual Ball mount kit. Note: For high volumes with aggressive delivery plan an AUTO ball mount kit may be required. Manual Ball mount kit deliver same quality but has impact on the throughput.

3,600 USD

5 Wafer grinding down to 8 Mils _8_” _w_a_f_e_r_s_ _ _1_2_” _w_a_f_e_r_s_ _

14 USD/w 29 USD/w

6 Set-up cost per new batch – engineering – valid for _F_i_r_s_t_ _a_s_s_e_m_b_l_y_ _o_f_ _n_e_w_ _p_r_o_d_u_c_t_ _ _P_a_r_t_s_ _d_e_l_i_v_e_r_e_d_ _i_n_ _t_r_a_y_s_ _ _M_P_W_ _w_a_f_e_r_s_ _(_ _m_u_l_t_i_p_l_e_ _d_i_e_ _p_e_r_ _w_a_f_e_r_ _)_ _

2,650 USD

7 Set-up cost per new batch – production – valid for _F_u_l_l_ _w_a_f_e_r_s_ _

1,600 USD

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8 Unit pricing LFBGA 400 21x21 4L _S_u_b_s_t_r_a_t_e_ _c_o_s_t_ _1_._6_1_ _U_S_D_ _ _A_s_s_e_m_b_l_y_ _o_n_l_y_ _0_._6_9_ _U_S_D_ _

2.3 USD/pc

9 _Production MoQ to be defined based on optimum substrate vendor. Expected to be ~ 50K substrates _MoQ not applicable on first (engineering) run ( item 3) _Substrates usable only for one year. For production assemblies the MoQ applies, customer need to pre-buy the substrates. at 70% of the unit cost.

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