© rep 8/16/2015 egre224 electronics - operational amplifiers page c2.1-1 introduction the basic...

© REP 04/19/23 EGRE224

Electronics - Operational Amplifiers

Page c2.1-1

Introduction

The basic operational amplifier or Op Amp is a very important circuit to study because it is so widely used.

Op Amps were initially made from discrete components like vacuum tubes and resistors with transistors eventually replacing vacuum tubes

In the mid 1960’s the first integrated circuit op amps were produced (A 709) It had quite a few transistors and resistors compared to the discrete versions it replaced Its characteristics were poor by today’s standards It was expensive, but

It was all on a single silicon chip and it ushered in a new era in analog electronic circuit design

It was more reliable than discrete op amps Engineers started using them in large quantities and the price dropped dramatically from over

ten dollars each to 30 cents each and the reliability continued to increase The op amp is a very versatile circuit and can be used in numerous other circuits. The

integrated circuit op amp characteristics come pretty close to that of an “ideal” amplifier. The near “ideal” behavior makes it much easier to design with op amps

By the end of this group of lecture sessions the reader should be able to design some fairly complex circuits using op amps

We will start by treating a op amp as a “building block” and describe its terminal characteristics and save a detailed discussion about what is inside an op amp for a later course (EGRE 307)

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Page c2.1-2

The Op Amp Terminals

The terminals of a circuit can be divided up into different groups based on their functions, for example the power supply terminals, the signal terminals, etc.

The op amp circuit has three signal terminals, two inputs (#1 , #2) and one output (#3) as shown on the figure below

The amplifier requires dc power to operate. Most op amps require two dc power supplies to operate. Most of the time the two supplies are equal in magnitude but opposite in polarity, for example a positive voltage supply +V (relative to ground) and a negative voltage supply -V (relative to ground) connected to terminals #4 and #5 as shown.

outputinputs -+

1

2

34

5

+V

-V

outputinputs -+

1

2

3

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Page c2.1-3

Op Amp Terminals, continued

An op amp can use a single power supply (+10V and ground for example) but the signal “reference” of the circuit for symmetrical behavior will then be at one half the upper supply voltage or +5V in this case.

The reference grounding point in op-amp circuits is just the common terminal of the two power supplies.

That is, no terminal of the op amp package is physically connected to ground In many cases the power supply connections will not be explicitly shown on the schematic. They will be omitted to reduce the “clutter” but the connections are still implied when you draw the triangular op amp symbol. An op amp may have other terminals for frequency compensation and for removing (or nulling) out offset voltages.Output signal ground

at +5V relative to real ground

inputs -+

1

2

34

5

+10V

0V

Output Signal ground is atsame level as real ground

inputs -+

1

2

34

5

+5V

-5V +10Voror

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Page c2.1-4

Exercise

What is the minimum number of terminals required for a single op amp?

Five - Two Inputs, Two power connections (either +/-, symmetric or + and Ground, non-symmetric) and one signal output referenced to ground (symmetric) or 1/2 the positive supply in a non-symmetric configuration

What is the minimum number of terminals required for an integrated circuit package which contains four op amps (assume all four share power supplies)? Fourteen, four pairs of inputs, two power connections and four outputs

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Page c2.1-5

The Ideal Op Amp

The op amp is designed to sense the difference between the voltage signals applied to its two inputs (v2-v1), and multiply this by a number A, and cause the resulting voltage A (v2-v1) to appear at the output terminal relative to ground. Note that v1 and v2 are also implied to be relative to ground as shown in the figure below.

The ideal op amp is not supposed to draw any current from the signal source (it willwill draw current from the power supply terminal which are not shown).

The input impedance is supposed to be infinite The output is supposed to act as an ideal voltage source independent of the current drawn by

any load placed on the op amp.

The output impedance is supposed to be zero

A(v2-v1)v1

v2I2=0

I1=0

Common terminalof the power supplies

2

1

3

The output has the same sign (is in phase with) the input v2 and is out of phase (opposite sign) as v1 . For this reason input terminal # 1 is called the inverting input (distinguished by a “-” sign) and input terminal # 2 is called the non-inverting input (distinguished by a “+” sign).

The op amp only responds to the difference signal v2-v1 and ignores any signal common to both inputs.

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Page c2.1-6

Common Signal vs. Differential Signal

The part of the signal that is the same for both inputs is called the common mode component and is not amplified

If both inputs see the same signal the DIFFERENCE (v2-v1) is zero and there is nothing to amplify and the output is zero. This means that the amplifier has rejected (not amplified) what the two signals had in common

An ideal opamp has infinite common-mode rejection

For the time being we will consider the opamp to be a differential input single - ended - output (output from terminal 3 to ground)

Vp-p

Vp-p12

on each sideout of phase

Vp-p

v2

v1

A(v2 - v1)

0

0on each side in phase

Vp-p

12

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Page c2.1-7

The Ideal Op Amp continued

The gain, AA is called the differential gain (based on the difference between terminals 2 and 1) The gain, A is also sometimes called the “open loopopen loop” gain as opposed to later on when we

add a feedback path from output to input and look at the “closed loopclosed loop” gain Opamps are direct-coupled (DC) or direct current (DC) amplifiers.

DC amplifiers have many applications but can also pose some practical problems IDEALIDEAL opamps amplify from zero frequency to infinite frequency, they are said to have infinite

bandwidth

A(v2-v1)v1

v2I2=0

I1=0

Common terminalof the power supplies

2

1

3

The gain of an ideal opamp should approach infinity, but then how could we make use of an ideal opamp since any difference times infinity would be infinity? We usually don’t use opamps in an open

loop configuration Feedback lowers the gain to practical

levels The value for A of a “real” opamp might be

on the order of a million

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Page c2.1-8

Exercise 2.2

Consider an op amp that is ideal except that its open-loop gain A=103. The op amp is used in a feedback circuit and the voltages appearing at two of its three signal terminals are measured. In each of the following cases, use the measured values to find the expected value of the voltage at the third terminal.

A) v2 = 0V, v3 = 2V

v1=-{(v3/A)-v2} = -{(2/1000)-0} = -0.002V

B) v2 = 5V, v3 = -10V

v1=-{(v3/A)-v2} = -{(-10/1000)-5} = 5.01V

C) v1 = 1.002V, v2 = 0.998V

v3=A(v2 - v1) = 1000(0.998-1.002) = 4.0V

D) v1 = -3.6V, v3 = -3.6V

v2={(v3/A)+v1} = {(-3.6/1000)+3.6} = 3.6036V

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Page c2.1-9

Exercise 2.3

The internal circuit of a particular op amp can be modeled by the circuit shown to the right.

Express v3 as a function of v1 and v2.

For the case when Gm = 10 mA/V, R =10k and = 100, find the value of the open-loop gain A.

3

v1

v2

vdvdR

Gmv1

Gmv2

2

1

123

1212

33

vvRGv

vvGvGvGi

RivRivvv

m

mmmR

RRdd

V

VA

RGvv

vA m

000,10

10,00001.0100 12

3

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Page c2.1-10

The Analysis of Circuits Containing Ideal Op Amps

The Inverting Configuration Resistor R2 is connected from the output terminal, 3, back to the invertinginverting or negative negative

terminal input terminal, 1. We say that R2 applies negative feedback, if R2 were connected between the output, 3, and the other input, 2, we would say that it was positive feedback.

We have grounded input number 2 and applied the input signal between terminal one and ground. This is known as a single sided input since terminal 2 does not contribute any information to the signal (since it is grounded).

The output is taken at terminal 3 relative to ground and is called a single sided output. Note that the impedance at terminal 3 (output) of an ideal opamp is infinite, thus the voltage vo will not depend on the value of the current that might be supplied to a load placed across vo.

output

input

-+

1

2

34

R2

vI

R1

+vo

-

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Page c2.1-11

Closed-Loop Gain (G) Analysis

G is defined as

We can draw the equivalent circuit for the opamp. Assume the opamp is powered up and working and the output is finite. With a finite output and infinite gain the difference between the inputs is negligibly small. Since terminal 2 is held at ground then terminal one also has to be at ground (forced there by the circuit NOT connected to ground).

Using our definition we write

-+

1

2

3

R2

vI

R1

+vo

-

-

+

1

2

3

R2

vI

R1

+vo

-

0

i1

i2

+_

A(v2-v1)v2-v1

I

O

v

vG

0or 1212 A

vvvvvvA O

O

We say that the two input terminals are tracking each other in potential

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Page c2.1-12

Virtual Ground

The circuit forces the two input terminals to be at virtually the same potential, they are “virtually” shorted together. A physical connection for charge movement does not exist but since they track each other in potential is like there is a connection (a virtual short circuit)

If terminal 2 is grounded then we can refer to terminal 1 as a “virtual” ground. It is forced to be at zero volts even though it is not directly connected to ground it acts like it is.

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Page c2.1-13

Back to the analysis

Since we now know v1 we can use Ohm’s law and find the current flowing through the resistor R1.

Since this current can not flow into the input terminal of an ideal op amp (infinite input resistance) it must flow through the resistor R2 to the low impedance terminal, 3 (output). We can now apply Ohm’s law to R2 and determine vo.

The negative sign for the closed loop gain indicates that the amplifier provides signal inversion

If we apply a 50mV peak-to-peak sine-wave input signal the output will be an amplified sine-wave with a 180 degree phase shift (inversion).

11

11 R

v

R

vvi II

1

22

1

1211

or

so 0but

R

R

v

vGR

R

vv

vRivv

I

OIO

O

© REP 04/19/23 EGRE224


Page c2.1-14

The Effect of Finite Open-Loop Gain

How do our results change if we let the open loop gain, A, be finite? If we let the output be denoted by vO, then the voltage difference between the inputs is

vO/A.

Since the positive input is grounded the negative input must be at - vO/A.

We can now find the current through resistor R1

The infinite input resistance of the op amp forces all of the current to flow through R2.

We can write another expression which contains vO.

Collecting terms and solving for the closed-loop gain G, we get

111

11 R

Avv

R

Avv

R

vvi

OI

OI

I

21

211 RR

Avv

A

vRivv

OIO

O

A

RRR

R

v

vG

I

O

1

2

1

2

11

Note: As AA approaches infinity, GG approachesthe ideal value that we previously derived

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Page c2.1-15

Input and Output Resistance

As A approaches infinity the voltage at the inverting terminal approaches zero (our virtual ground)

In order to minimize the effect of A on G we should make

If we assume an ideal op amp with an infinite input resistance the overall input resistance of the closed loop circuit (containing the ideal op amp) will be

The value of the open loop gain, A, has very little effect on the input resistance For a high input resistance we need R1 high, but if we want the gain to also be high we

might require R2 to be very large (maybe impracticably large). Can you think of a way to increase the input resistance?

The output of the inverting configuration is taken at the terminal of an ideal voltage source (whose value is (v2-v1)A) which can supply infinite current, Rout=V/I is zero.

AR

R

1

21

1

1

R

Rvv

i

vR

I

I

I

Ii

+vI

_

+_

Putting the previous results together we have the following model of the inverting closed loop amplifier circuit (using an ideal opamp)

Ri=R1

Ro=0

IvR

R

1

2

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Page c2.1-16

Example 2.1

Consider the inverting amplifier configuration shown below with R1=1k and R2=100k.

A) Find the closed-loop gain for the cases A=103, 104, 105. In each case determine the percentage error in the magnitude of G relative to the ideal value of R2/R1 (obtained with A that is infinite). Also determine the voltage v1 that appears at the inverting input terminal when vI = 0.1 V.

We can use the equation for the closed loop gain, Greal in terms of the open loop gain, A and compare the results to the ideal closed loop gain Gideal.

100/11

100(error)

1

2

1

2

1

2

1

2

RR

RR

ARRR

R

G

GG

ideal

idealreal

mV

mV

mV

vGA real

10.0 %10.0 90.99 10

99.0 %00.1 00.99 10

08.9 %17.9 83.90 10

5

4

3

1

Vv

A

Gv

A

vv I

IO 1.0 where1

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Page c2.1-17

Example 2.1 continued

B) If the open-loop gain A is cut in half, from 100,000 to 50,000, what is the corresponding percentage change in the magnitude of the closed-loop gain G?

For A=100,000 G was 99.9, so cutting the open loop gain in half from 100,000 to 50,000 only changed the closed loop gain by -0.1 percent

Using negative feedback in a low gain configuration makes the circuit much more impervious to possible variations in the open-loop gain of the op amp.

8.99

000,501001

1

100

11 1

2

1

2

A

RRR

R

v

vG

I

O

© REP 04/19/23 EGRE224


Page c2.1-18

Example 2.2

We are going to analyze a different inverting op amp circuit (see below) Part A) Derive an expression for the closed-loop gain vO/vI

We can now write an expression for the voltage at node “X”

-+

R2

vI

R1

+vo

-

R3

R4

vI i1

0

i2 i4

i3

Ideal

0

OOI

v

A

vv

111

11

0

R

v

R

v

R

vvi III

112 R

vii I

X

II

x vR

RR

R

vRivv

1

22

1221 0

I

x vRR

R

R

vi

31

2

33

0

I

I vRR

R

R

viii

31

2

1324

431

2

11

244 Rv

RR

R

R

vv

R

RRivv I

IIxO

3

4

2

4

1

2

3

2

1

4

1

2 11R

R

R

R

R

R

R

R

R

R

R

R

v

v

I

O

© REP 04/19/23 EGRE224


Page c2.1-19

Exercise 2.4 (design)

Using the circuit shown below design and inverting amplifier having a gain of -10 and an input resistance of 100k. Give the values of R1 and R2.

output

input

-+

1

2

34

R2

vI

R1

+vo

-

M1

10010

2

2

1

2

R

k

R

R

R

v

vG

I

O

ground at virtual is 1) (terminalinput inverting thesince 100k1 RRi

© REP 04/19/23 EGRE224


Page c2.1-20

Exercise 2.5 Transresistance Amplifier

The circuit shown below can be used to implement a transresistance amplifier. Find the value of the input resistance Ri, the transresistance Rm, and the output resistance Ro.

output

input -+

1

2

34

+vo

-

10k

ground at virtual is 1) (terminalinput inverting thesince 01 RRi

kkv

v

i

vR

O

O

I

Om 10

10/

low so is resistanceoutput

Amp Op thesince ignored isresistor 10k theso

Amp Op Ideal theof definition thefrom 0

OR

© REP 04/19/23 EGRE224


Page c2.1-21

Exercise 2.5 Transresistance Amplifier continued

Part b) If a signal source of 0.5 mA in parallel with a 10k resistor (see below) is connected to the input of this amplifier find its output voltage.

output

-+

1

2

34

+vo

-

RF 10k

RS

10k0.5mA

Since terminal 2 is grounded terminal 1 is forced to a virtual groundthis means that both sides of the source resistance Rs are at ground andno current flows through it. The entire 0.5 mA must flow through RF the feedback resistor since the input impedance of the op amp is infinitelylarge. Therefore VmAiRv FO 5000,105.0

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Page c2.1-22

The Inverting Configuration with General Impedances

The Inverting Configuration Replace resistors R1 and R2 with impedances Z1 and Z2 as shown below.

output

input

-+

1

2

34

Z2

vI(s)

Z1

+vo(s)

-

frequency of signalinput theof phase and magnitude physical The

ere wh1

2 sjsZ

sZ

sv

svsG

I

O

© REP 04/19/23 EGRE224


Page c2.1-23

Example 2.3

Derive an expression for the transfer function of the circuit shown below. Express the transfer function in a standard form for Bode Plots (see page 32 of Sedra and Smith 4th edition).

-+

1

2

3

R2

vI

R1

+vo

-

C2

22211

1 and , Let sCRZRZ

122

1

1

22

2

2

1

22

1

1

1

1

RsCRRsv

sv

R

sCR

sC

R

R

sCR-

sv

sv

I

O

I

O

22

1

2

1 RsC

RR

sv

sv

I

O

In Bode Plot Form 1

2

R

RK The dc gain is

The corner frequency is 22

0

1

RC

© REP 04/19/23 EGRE224


Page c2.1-24


We could arrive at the same results regarding the circuit with impedances by using our knowledge of the frequency dependent behavior of the capacitor.

The capacitor behaves as an open circuit at low frequencies. With the capacitor essentially removed the circuit is the same as the resistive configuration we have already analyzed and the gain is just -(R2/R1).

At high frequencies the capacitor acts like a short-circuit and resistor R2 will become shorted out reducing the gain to zero at some point (frequency).

Design the circuit so that the dc gain is 40 dB with a corner (-3dB) frequency of 1kHz and an input resistance of 1k.

The input resistance is simply R1 = 1k since the inverting input is at ground

We can now find the capacitance value which causes the corner frequency (f0) to be at 1kHz.

VVA

AdB

10010

40log20 in Gain

2040

12

1

2 100 100 RRR

RV

VAdc

kkRR 1001100100 12

nFC

RCf

59.1

000,100000,12

1C

12

2

222

0

© REP 04/19/23 EGRE224


Page c2.1-25


Recall that the gain of a low pass single time constant circuit will fall off at -20dB per decade, so that if the gain is 40 db at f0=1kHz then the gain will be zero dB two decades higher at f=100kHz.

We also know that there is a -90 degree phase shift for frequencies more than ten times the corner frequency, but we have to recall that in the case of the inverting configuration there is already a -180 degree (inversion) shift so that the total phase shift is -270 degrees.

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Page c2.1-26

The Inverting Integrator

Consider the inverting configuration with an impedance due to the capacitor used to provide the feedback We apply a time-varying input signal vI(t). The virtual ground at terminal 1 causes the input signal to appear across the resistor and a current i I(t) to flow. This current flow through the capacitor C since the

input impedance of the ideal op amp is infinitely high. A charge will begin to accumulate on capacitor C. If we assume that the circuit began operating at time t=0 then at some arbitrary time t, the charge on the capacitor will be given by

The capacitor voltage will be where

-+

1

2

3vI(t)

R

+vo(t)

-

C

dttiQt

t

I

0

dttiC

Vtvt

t

ICC

0

1 0at is tCVC

The output voltage is

The output is proportional to the time integral of the input. The product RC is the integrator time constant

C

t

t

IO VdttvRC

tv 0

1

© REP 04/19/23 EGRE224


Page c2.1-27

Another way to analyze the inverting integrator

Looking at the frequency domain

And

The integrator transfer function has a magnitude of

The phase angle () is +90 degrees Constructing a Bode plot of the transfer function shows that as w doubles the

magnitude of the response is cut in half. You can prove to yourself that this is a -6 dB decrease for each octave (eight-fold) increase in frequency and a -20 dB decrease for each decade increase in frequency.

The frequency at which the integrator gain becomes zero dB is known as the integrator frequency and is simply the reverse of the integrator time constant.

sC

sZRsZ1

and 21

CRjjV

jV

sCRsV

sV

i

o

i

o

1

1

CRV

V

i

o

1

dB I

O

v

v1/CR

-20 dB per decade

(log scale)

© REP 04/19/23 EGRE224


Page c2.1-28

Some additional comments about the integrator

As seen on the integrator behaves like a low-pass filter with a corner frequency of zero At zero frequency (dc) the gain is infinite (open loop gain of an ideal opamp) The feedback element is a capacitor and at dc it would be an open circuit (no feedback

or an open loop) Any tiny dc level in the input will theoretically produce a very large output. What really

happens is that the op amp’s output usually saturates at a level very close to the positive or negative power supply levels of the op amp depending on the polarity of the tiny dc level.

We can reduce the gain of the dc signal by placing a high valued resistor in parallel with the capacitor. The high value should have little effect (no longer ideal though) on the integrator but it will provide a dc feedback path.

© REP 04/19/23 EGRE224


Page c2.1-29

Example 2.4

Find the output produced by a Miller integrator in response to an input pulse of 1-V height and 1-ms width. Let R=10k and C=10nf.

From our earlier work we know the response will be of the form

Substituting in the given values we find

ms 10for 0 11

0

tdtRC

tvt

t

O Assume that the initial voltageon the capacitor is zero

ms 10for 10 tttvO

tvO

tvI

1ms0

-10V

1V

t

t

© REP 04/19/23 EGRE224


Page c2.1-30


The 1V signal through a 10k resistor produces a constant 0.1mA current through the capacitor which causes the voltage to increase linearly

If the integrator capacitor is shunted by a 1-M resistor, how will the response be modified? The current will now be supplied into a single time constant network of Rf in

parallel with C. Appendix F gives a review of single time constant circuits and the resulting output

responses. The solution to the differential equation that arises is

Where is the final value of the output

and is the initial value which is zero

Therfore

CRt

OOOOfevvvtv

0

VmAIRv fO 100000,000,11.0

Ov

0Ov

ms 10 1100 10

tetv

t

O

-9.5V1100ms 1 101

evO

tvO

-9.5V

t

01ms

© REP 04/19/23 EGRE224


Page c2.1-31

The Differentiator (noise magnifier, rarely used)

-+

1

2

3vI(t)

R

C

+vo(t)

-

dt

tdvCRtv I

O

dt

tdvCti I RsZ

sCsZ 21 and

1

CRjjV

jVsCR

sV

sV

i

o

i

o

CRV

V

i

o

11

2 sCRsC

R

Z

Z

sV

sV

i

o

90

CR is the differentiator time constant

© REP 04/19/23 EGRE224


Page c2.1-32

Like a single time constant high-pass filter Spike at the output every time there is a sharp change in the input

dB I

O

v

v 1/CR

+20 dB per decade

(log scale)

-+

1

2

3vI(t)

R

C

+vo(t)

-

Improvement,but makes it non-ideal

© REP 04/19/23 EGRE224


Page c2.1-33

The Weighted Summer

-+

1

2

3

Rf

v1

R1

+vo

-

v2

R2

v3

R3

i

i1

i2

i3

0V

i

3

33

2

22

1

11

R

vi

R

vi

R

vi

321 iiii

fO iRv 0

3

32

21

1

vR

Rv

R

Rv

R

Rv fffO

© REP 04/19/23 EGRE224


Page c2.1-34

Exercise 2.6

Consider a symmetrical square wave of 20-V peak-to-peak, zero average, and two milli-second period applied to a Miller integrator. Find the value of the time constant RC such that the triangular waveform at the output has a 20 Volt peak-to-peak amplitude.

Refer back to example 2.4

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Page c2.1-35

The Non-Inverting Configuration

The Non-Inverting Configuration The input signal vi is applied directly to the positive input terminal while one terminal of R1 is

grounded

Analysis, Assuming that the op amp is ideal with infinite gain, a virtual short circuit exists between

the two input terminals and the difference input signal is

since the voltage at the inverting terminal (is equal to that at the non-inverting terminal) is equal to vI we can determine the current through resistor R1.

output

input

-+

1

2

34

R2

vI(s)

R1

+vo(s)

-

Virtual short

AvvvA

vvv o

o since 0 since and 1212

© rep 8/16/2015 egre224 electronics - operational amplifiers page c2.1-1 introduction the basic...

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