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Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, McKee, and Sirer.

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Page 1: , l ] u t Z } } v } u µ ^ ] v } v o o h v ] À ] Ç · 2018-05-17 · , l ] u t z } } v ^ ï ð í ì } u µ ^ ] v } v o o h v ] À ] Ç 7kh volghv duh wkh surgxfw ri pdq\ urxqgv

Hakim WeatherspoonCS 3410

Computer ScienceCornell University

The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, McKee, and Sirer.

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Which is not considered part of the ISA?

A. There is a control delay slot.B. The number of inputs each instruction can

have. C. Load-use stalls will not be detected by the

processor. D. The number of cycles it takes to execute a

multiply.E. Each instruction is encoded in 32 bits.

2

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Which is not considered part of the ISA?

A. There is a control delay slot.B. The number of inputs each instruction can

have. C. Load-use stalls will not be detected by the

processor. D. The number of cycles it takes to execute a

multiply.E. Each instruction is encoded in 32 bits.

3

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Prelim todayStarts at 7:30pm sharpGo to location based on netidFind locations on piazza

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Write-BackMemory

InstructionFetch Execute

InstructionDecode

extend

registerfile

control

alu

memory

din dout

addrPC

memory

newpc

inst

IF/ID ID/EX EX/MEM MEM/WB

imm

BA

ctrl

ctrl

ctrl

BD D

M

computejump/branch

targets

+4

forwardunit

detecthazard

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6

int x = 10;x = 2 * x + 15;

Ccompiler

addi r5, r0, 10muli r5, r5, 2addi r5, r5, 15

MIPSassembly

001000000000010100000000000010100000000000000101001010000100000000100000101001010000000000001111

machinecode

assembler

CPU

Circuits

Gates

Transistors

Silicon

op = addi r0 r5 10

op = addi r5 r5 15

op = r-type r5 r5 shamt=1 func=sll

r0 = 0r5 = r0 + 10r5 = r5<<1 #r5 = r5 * 2r5 = r15 + 15

AB

32 32RF

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7

int x = 10;x = 2 * x + 15;

Ccompiler

addi r5, r0, 10muli r5, r5, 2addi r5, r5, 15

MIPSassembly

001000000000010100000000000010100000000000000101001010000100000000100000101001010000000000001111

machinecode

assembler

CPU

Circuits

Gates

Transistors

Silicon

Instruction SetArchitecture (ISA)

High Level Languages

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Instruction Set Architectures• ISA Variations, and CISC vs RISC• Peek inside some other ISAs:

• X86• ARM

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Is MIPS the only possible instruction set architecture (ISA)? What are the alternatives?

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ISA defines the permissible instructions• MIPS: load/store, arithmetic, control flow, …• ARMv7: similar to MIPS, but more shift, memory, &

conditional ops• ARMv8 (64-bit): even closer to MIPS, no conditional ops• VAX: arithmetic on memory or registers, strings, polynomial

evaluation, stacks/queues, …• Cray: vector operations, …• x86: a little of everything

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Accumulators• Early stored-program computers had one register!

• One register is two registers short of a MIPS instruction!• Requires a memory-based operand-addressing mode

– Example Instructions: add 200 // ACC = ACC + Mem[200] Add the accumulator to the word in memory at address 200 Place the sum back in the accumulator

EDSAC (Electronic Delay Storage Automatic Calculator) in 1949

Intel 8008 in 1972was an accumulator

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Next step, more registers…• Dedicated registers

– E.g. indices for array references in data transfer instructions, separate accumulators for multiply or divide instructions, top-of-stack pointer.

• Extended Accumulator– One operand may be in memory (like previous accumulators). – Or, all the operands may be registers (like MIPS).

Intel 8086“extended accumulator”Processor for IBM PCs

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Next step, more registers…• General-purpose registers

– Registers can be used for any purpose– E.g. MIPS, ARM, x86

• Register-memory architectures– One operand may be in memory (e.g. accumulators)– E.g. x86 (i.e. 80386 processors)

• Register-register architectures (aka load-store)– All operands must be in registers– E.g. MIPS, ARM

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The number of available registers greatly influenced the instruction set architecture (ISA)

Machine Num General Purpose Registers Architectural Style Year

EDSAC 1 Accumulator 1949

IBM 701 1 Accumulator 1953

CDC 6600 8 Load-Store 1963

IBM 360 18 Register-Memory 1964

DEC PDP-8 1 Accumulator 1965

DEC PDP-11 8 Register-Memory 1970

Intel 8008 1 Accumulator 1972

Motorola 6800 2 Accumulator 1974

DEC VAX 16 Register-Memory, Memory-Memory 1977

Intel 8086 1 Extended Accumulator 1978

Motorola 6800 16 Register-Memory 1980

Intel 80386 8 Register-Memory 1985

ARM 16 Load-Store 1985

MIPS 32 Load-Store 1985

HP PA-RISC 32 Load-Store 1986

SPARC 32 Load-Store 1987

PowerPC 32 Load-Store 1992

DEC Alpha 32 Load-Store 1992

HP/Intel IA-64 128 Load-Store 2001

AMD64 (EMT64) 16 Register-Memory 2003

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The number of available registers greatly influenced the instruction set architecture (ISA)

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How to compute with limited resources?

i.e. how do you design your ISA if you have limited resources?

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People programmed in assembly and machine code!• Needed as many addressing modes as possible• Memory was (and still is) slow

CPUs had relatively few registers• Register’s were more “expensive” than external mem• Large number of registers requires many bits to index

Memories were small• Encouraged highly encoded microcodes as instructions• Variable length instructions, load/store, conditions, etc

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People programmed in assembly and machine code!E.g. x86

• > 1000 instructions!– 1 to 15 bytes each– E.g. dozens of add instructions

• operands in dedicated registers, general purpose registers, memory, on stack, …

– can be 1, 2, 4, 8 bytes, signed or unsigned• 10s of addressing modes

– e.g. Mem[segment + reg + reg*scale + offset]

E.g. VAX • Like x86, arithmetic on memory or registers, but also

on strings, polynomial evaluation, stacks/queues, …

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The number of available registers greatly influenced the instruction set architecture (ISA)

Complex Instruction Set Computers were very complex

• Necessary to reduce the number of instructions required to fit a program into memory.

• However, also greatly increased the complexity of the ISA as well.

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How do we reduce the complexity of the ISA while maintaining or increasing performance?

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John Cock• IBM 801, 1980 (started in 1975)• Name 801 came from the bldg that housed the project• Idea: Possible to make a very small and very fast core• Influences: Known as “the father of RISC

Architecture”. Turing Award Recipient and National Medal of Science.

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Dave Patterson• RISC Project, 1982• UC Berkeley• RISC-I: ½ transistors & 3x

faster• Influences: Sun SPARC,

namesake of industry

John L. Hennessy• MIPS, 1981• Stanford• Simple, full pipeline• Influences: MIPS computer

system, PlayStation, Nintendo

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MIPS Design Principles

Simplicity favors regularity• 32 bit instructions

Smaller is faster• Small register file

Make the common case fast• Include support for constants

Good design demands good compromises• Support for different type of interpretations/classes

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MIPS = Reduced Instruction Set Computer (RlSC)• ≈ 200 instructions, 32 bits each, 3 formats• all operands in registers

– almost all are 32 bits each• ≈ 1 addressing mode: Mem[reg + imm]

x86 = Complex Instruction Set Computer (ClSC)• > 1000 instructions, 1 to 15 bytes each• operands in dedicated registers, general purpose

registers, memory, on stack, …– can be 1, 2, 4, 8 bytes, signed or unsigned

• 10s of addressing modes– e.g. Mem[segment + reg + reg*scale + offset]

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RISC• Single-cycle execution• Hardwired control

• Load/store architecture• Few memory addressing

modes• Fixed-length insn format

• Reliance on compiler optimizations

• Many registers (compilers are better at using them)

26

CISC• many multicycle operations• microcoded multi-cycle

operations• register-mem and mem-mem• many modes

• many formats and lengths

• hand assemble to get good performance

• few registers

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RISC PhilosophyRegularity & simplicityLeaner means fasterOptimize the common case

Energy efficiencyEmbedded SystemsPhones/Tablets

CISC RebuttalCompilers can be smartTransistors are plentifulLegacy is importantCode size countsMicro-code!

Desktops/Servers

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• Android OS on ARM processor

• Windows OS on Intel (x86) processor

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What is one advantage of a CISC ISA?

A. It naturally supports a faster clock.B. Instructions are easier to decode. C. The static footprint of the code will be

smaller.D. The code is easier for a compiler to

optimize.E. You have a lot of registers to use.

29

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What is one advantage of a CISC ISA?

A. It naturally supports a faster clock.B. Instructions are easier to decode. C. The static footprint of the code will be

smaller.D. The code is easier for a compiler to

optimize.E. You have a lot of registers to use.

30

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The number of available registers greatly influenced the instruction set architecture (ISA)

Complex Instruction Set Computers were very complex- Necessary to reduce the number of instructions required to fit a program into memory.- However, also greatly increased the complexity of the ISA as well.

Back in the day… CISC was necessary because everybody programmed in assembly and machine code! Today, CISC ISA’s are still dominant due to the prevalence of x86 ISA processors. However, RISC ISA’s today such as ARM have an ever increasing market share (of our everyday life!).ARM borrows a bit from both RISC and CISC.

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How does MIPS and ARM compare to each other?

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All MIPS instructions are 32 bits long, has 3 formats

R-type

I-type

J-type

op rs rt rd shamt func

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt immediate

6 bits 5 bits 5 bits 16 bits

op immediate (target address)6 bits 26 bits

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All ARMv7 instructions are 32 bits long, has 3 formats

R-type

I-type

J-type

opx op rs rd opx rt

4 bits 8 bits 4 bits 4 bits 8 bits 4 bits

opx op rs rd immediate

4 bits 8 bits 4 bits 4 bits 12 bits

opx op immediate (target address)

4 bits 4 bits 24 bits

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• while(i != j) {• if (i > j)• i -= j;• else• j -= i;• }Loop: BEQ Ri, Rj, End // if "NE" (not equal), then stay in loop

SLT Rd, Rj, Ri // "GT" if (i > j), BNE Rd, R0, Else // …SUB Ri, Ri, Rj // if "GT" (greater than), i = i-j; J Loop

Else: SUB Rj, Rj, Ri // or "LT" if (i < j)J Loop // if "LT" (less than), j = j-i;

End:

In MIPS, performance will be slow if code has a lot of branches

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• while(i != j) {• if (i > j)• i -= j;• else• j -= i;• }LOOP: CMP Ri, Rj // set condition "NE" if (i != j)

// "GT" if (i > j), // or "LT" if (i < j)

SUBGT Ri, Ri, Rj // if "GT" (greater than), i = i-j; SUBLE Rj, Rj, Ri // if "LE" (less than or equal), j = j-i; BNE loop // if "NE" (not equal), then loop

= ≠ < >0 1 0 0

= ≠ < >0 0 0 1

= ≠ < >1 0 1 0

= ≠ < >0 1 0 0

In ARM, can avoid delay due to Branches with conditional instructions

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Shift one register (e.g. Rc) any amountAdd to another register (e.g. Rb)Store result in a different register (e.g. Ra)

ADD Ra, Rb, Rc LSL #4Ra = Rb + Rc<<4Ra = Rb + Rc x 16

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All ARMv7 instructions are 32 bits long, has 3 formatsReduced Instruction Set Computer (RISC) properties

• Only Load/Store instructions access memory• Instructions operate on operands in processor registers• 16 registers

Complex Instruction Set Computer (CISC) properties• Autoincrement, autodecrement, PC-relative addressing• Conditional execution• Multiple words can be accessed from memory with a

single instruction (SIMD: single instr multiple data)

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All ARMv8 instructions are 64 bits long, has 3 formatsReduced Instruction Set Computer (RISC) properties

• Only Load/Store instructions access memory• Instructions operate on operands in processor registers• 32 registers and r0 is always 0

NO MORE Complex Instruction Set Computer (CISC) properties

• NO Conditional execution• NO Multiple words can be accessed from memory with

a single instruction (SIMD: single instr multiple data)

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ISA defines the permissible instructions• MIPS: load/store, arithmetic, control flow, …• ARMv7: similar to MIPS, but more shift, memory, &

conditional ops• ARMv8 (64-bit): even closer to MIPS, no conditional ops• VAX: arithmetic on memory or registers, strings, polynomial

evaluation, stacks/queues, …• Cray: vector operations, …• x86: a little of everything

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The number of available registers greatly influenced the instruction set architecture (ISA)

Complex Instruction Set Computers were very complex+ Small # of insns necessary to fit program into memory.- greatly increased the complexity of the ISA as well.

Back in the day… CISC was necessary because everybody programmed in assembly and machine code! Today, CISC ISA’s are still dominant due to the prevalence of x86 ISA processors. However, RISC ISA’s today such as ARM have an ever increasing market share (of our everyday life!).ARM borrows a bit from both RISC and CISC.

41


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