© intec 2000 packaging of parallel optical interconnects modules with on chip optical access...

© intec 2000

Packaging of parallel optical interconnects modules with on chip optical access

François Marion / Julien Routin (LETI)

Ronny Bockstaele / Olivier Rits (IMEC)

http://www.intec.rug.ac.be/IODATE WORKSHOP, Paris CNIT, February 20, 2003

Summary

Packaging for today Flip chip technology BGA package Alignment techniques for

fiber connector

Packaging for the future• CSP package development• Flip/chip over glass sheet

PCB

Packaged CMOS chipswith direct on chip optical access

DTA Digital technology assessment testbed

PCB

backplane

Optical pathways Optical pathways


Packaging for today

Packaging specifications

Electrical interface 296 I/O’s, LVDS signals

Optical interface 64 optical in, 64 optical out

Mechanical interface alignment of fiber connector : +/-5µm

Thermal interface 10W thermal dissipation

Hermeticity semi-hermetic packaging

Packaging specifications

PACKAGED chip


296 electrical I/Os

64 optical outputs

64 optical inputs

Thermal sink 10W

+/-5µmmechanical

guide

Packaging for today Packaging specifications


Develop reliable flip-chip technology for direct coupling of large arrays opto-chips on CMOS

Provide custom BGA package

Provide alignment aids for optical connector passive

alignment


DIFFERENT TASKS


Develop flip chip technology : wafer bumpingPackaging for today

DTA1 CMOS

Bumps for glass board F/C

Bumped CMOS chip

Bumps for opto chips F/C

Bumps for silicon benches F/C


Develop flip chip technology : wafer scale hybridizationPackaging for today


Post-process on CMOS wafer

Hybridize VCSEL+ photodiodechips

Bump CMOS

Underfill

THIN for butt coupling

Antireflectivecoating

Dicing + hybridizeAlignment plate

50µm

Develop flip chip technology : wafer scale hybridization

bench

bench

PIN detector

VCSEL

F/C optos and µbench on DTA1 CMOS

Packaging for today


CUSTOM BGA PACKAGE

Provide BGA packagePackaging for today


High speed I/O’s (diff pairs)

Lo

w

spe

ed

I/O

’s

SnPb bumps(302)

Provide BGA package

Controlled geometryX,Y Z

Thermal sink

Packaging for today


Silicon bench alignement

INDEX alignement

Develop alignment techniquePackaging for today


Silicon bench for X,Y,Z alignment

Guiding pins+/- 5µm X,Y misalignment versus optos

Develop silicon bench alignment techniquePackaging for today


Develop silicon bench alignment techniquePackaging for today

AssemblageIO.exe


INDEX ALIGNMENT• Alignment is based on measurement of coordinates, not based on

mechanical contact

• Then attach using UV-curable adhesive

Package on (,) stage

Spacer plate on (X,Y,Z,) stage

CMM measuringhead

Assembly of the package using index alignment


CSP package

New concept

-Package size reduced to 15*15mm (vs. 26*28mm for « today BGA »)-Alignment pins placement made easier-NO wirebonds (increased speed)-Optics included in pathway =

-connector made easier-optical coupling made easier-hermeticity made easier

Packaging for tomorrow

CSP package

CMOS +optos

Direct hybridization of CMOS+opto on customized CSP ceramic

To PCB Optics in pathway

CSP package


ULTIMATE : direct flip chip over glass sheet PCB

Chip on optical (glass sheet) boardPackaging for tomorrow

Silicon CMOS

Electrooptical PCB

Glass waveguide

Copper traces(Electronic)

Optical waveguides(photonic)


CONCLUSION

Conclusion :

Packaging for to-day = first packaged modules delivered

Packaging for tomorrow = development on going:

CSP (chip scale packaging)

Chip On Board packaging (glass sheet board)

© intec 2000 packaging of parallel optical interconnects modules with on chip optical access...

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