© h. heck 2008section 4.31 module 4:metrics & methodology topic 3: source synchronous timing...

© H. Heck 2008 Section 4.3 1

Module 4: Metrics & MethodologyTopic 3: Source Synchronous Timing

OGI EE564

Howard HeckTsetup Thold

clk

in


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Where Are We?

1. Introduction

2. Transmission Line Basics

3. Analysis Tools

4. Metrics & Methodology1. Synchronous Timing

2. Signal Quality

3. Source Synchronous Timing

4. Recovered Clock Timing

5. Design Methodology

5. Advanced Transmission Lines

6. Multi-Gb/s Signaling

7. Special Topics


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Contents

Synchronous Bus Limitations Source Synchronous Concept & Advantages Operation Timing Equations Maximum Transfer Rate Summary References Appendix: Timing Equation Derivation


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Common Clock Limitations

Max frequency is defined by min cycle time Min cycle time is limited by maximum delays. Can we find a way to remove the dependence on

absolute delays?

min,max

1cycleTf

skewsetupflightdrivercycle TTTTT max,max,min,

clk

D QCLK

D QCLK

a b

FR

OM

CO

RE

TO

CO

RE


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Source Synchronous Signaling Concept

The transmitting agent sends the clock (a.k.a. strobe), along with the data signal.

Overview: • Drive the clock and data signals with a known phase relationship.• Design the clock and data signals to be identical in order to preserve

the phase relationship.

• As long as the phase relationship can be maintained, the lines can be much longer.

D Q

PLL

D QDeskew

PLL

D Q

Delay Line

Data

I/O Clock

Sys Clock Sys Clock


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Suppose that we transmit a data signal 1 ns prior to transmitting the strobe.

You’re given a 500 ps receiver setup requirement. You find that the flight time for the data signal varies

between 5.5 ns and 5.7 ns. The flight time for the clock signal also varies between

5.5 ns and 5.7 ns, independent from the data.

Can we meet the setup requirement?

Source Synchronous Concept Example

CLK/CLK#@ Tx

DATA@ Tx

CLK/CLK#@ Rx

DATA@ Rx

Tsu= 500 ps

5.7 ns

5.5 ns

1.0 ns

300 ps


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Source Synchronous Advantage

From the preceding example, it should be apparent that source synchronous performance depends on relative, rather than absolute delays.• True for drivers and interconnect, though we must still meet

the absolute setup/hold requirements for the receiver.

In real systems, the difference in delay between signals can be made much smaller than the absolute delays.

Therefore, with source synchronous signaling we can expect • to achieve higher performance • to be able to use longer traces


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Transfer Rate Comparison

SynchronousSource Synchronous

FSB 200 MHz 1600 MT/s

Graphics 66 MHz 533 MT/s

Memory 133 MHz1600 MT/s

800 MT/s (RDRAM)


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Operation Typically, there is

one strobe signal (or pair of signals) per two bytes of data signals.• Varies by design

Signal relationships at the transmitter are shown below.

Setup Hold

CLK

DATA

STROBE

Setup Hold

D Q

PLL

D Q

90o

Deskew

PLL

D Q

Delay Line

Data

I/O Clock

Sys Clock Sys Clock

D Q

PLL

D QDeskew

PLL

D Q

Delay Line

Data

I/O Clock

Sys Clock Sys Clock


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Source Synchronous Operation

TvaTvb

ThTsu

Tsuskew

STROBE/STROBE

DATA

Thmar

Thskew

Tsumar

t

@ DRIVER

@ RECEIVER

Tsuskew: flight time skew for setup

Tsumar: setup margin

Tvb: min driver phase offset (setup)

Thskew: flight time skew for hold

Thmar: hold margin

Tva: min driver phase offset (hold)


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Source Synchronous Equations

TvaTvb

ThTsu

Tsuskew

STROBE/STROBE

DATA

Thmar

Thskew

Tsumar

t

@ DRIVER

@ RECEIVER

The sum of the timings at the receiver must not exceed the phase offsets at the driver:

the transmitter design requires minimum offsets:sumarsuskewsuvb TTTT hmarhskewhva TTTT

suskewsuvb TTT hskewhva TTT

[4.3.1] [4.3.2]

[4.3.3] [4.3.4]


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Source Synchronous Equations #2

We must also satisfy the following relationship:

This determines our maximum transfer rate.

min,max

1bitT

TR

vbvabit TTT min, Tbit: data bit width

TRmax: max transfer rate[4.3.6]

[4.3.5]

TvaTvb

ThTsu

Tsuskew

STROBE/STROBE

DATA

Thmar

Thskew

Tsumar

t

@ DRIVER

@ RECEIVER


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Question

Based on what we’ve covered in the previous slides, what are the implications to:The transmitter design?The receiver design?The interconnect design?


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Example

Tsu = 500 ps, Th = 500 ps

The target transfer rate is 500 MT/s.What are reasonable flight time skew targets?

CLK/CLK#@ Tx

DATA@ Tx

CLK/CLK#@ Rx

DATA@ Rx

Tsu = 0.5 ns

x + 0.5 ns

x ns

1.0 ns

x ns

1.0 ns

x - 0.5 ns

Th = 0.5 ns

SETUP HOLD


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Source Synchronous Timing Summary Synchronous timings are limited by absolute delays. Source synchronous timings use a strobe eliminate

dependence on absolute delay. Performance depends on our ability to maintain known

phase relationship between data & strobe

As a result, source synchronous interfaces typically operate at 2x-8x the clock frequency. Expect that ratio to scale much higher in the future.

Matching of delays (transmitter & interconnect) is a key design consideration for designing high speed source synchronous interfaces.


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References

S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition.

W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.

R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1st edition, 1995.

H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.

H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, 1993.

S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.


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Appendix: Source Synchronous Timing Equation Derivation


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Source Synchronous Bus Operation

PLL

D Q

SystemClock

Driver Chip

Strobe

D Q

Data

From Core

n

From Core

Clock Distribution Tree

n

PLL

Q D

Receiver Chip

Str

ob

e

Q D

Data


To Core

DELAY

n


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Operation #2

The transmitted strobe (and data) signals are generated from the on-chip bus clock.

Typically, the strobe is phase shifted by ½ cycle from the data signal. Duty cycle variations will cause variation on the phase

relationship

The timing path starts at the flip-flop of the transmitting agent and ends at the flip-flop of the receiving agent.

The strobe signal is used as the clock input of the receiver flip-flop.

PLL

D Q

SystemClock

Driver Chip

Strobe

D Q

Data

From Core

n

From Core


n

PLL

Q D

Receiver Chip

Str

ob

e

Q D

Data


To Core

DELAY

n


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Setup Timing Diagram & Loop Analysis

Tco(STB)

Tsumar

DCLK

TBCLK /4

TBCLK

BCLK

STB/STBDRIVER

DATADRIVER

DATARECEIVER

RECEIVER STB/STB

Tflight(DATA) Tsu

Tco(DATA)

t

Tflight(STB)

04 DATATDATATTTSTBTSTBTTflightcosumarsuflightco

BCLK [4.3.1a]


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Setup Analysis

For a “double pumped” bus, the difference between Tco(DATA) and Tco(STB) is typically set to one-half of the cycle time (TDCLK/2 = TBCLK/4) to center the strobe in the data valid window. Double pumped: source synchronous transfer rate is 2x the central

clock rate. This relationship is typically specified as Tvb (data “valid before”

strobe ), which signifies the minimum time for which the data at the transmitter is valid prior to transmission of the strobe.

Mathematically:

Simplify the loop equation:

04 DATATDATATTTSTBTSTBTTflightcosumarsuflightco

BCLK

[4.3.1a]

4maxmin,BCLK

cocovbTSTBTDATATT [4.3.2a]

0min, DATATTTSTBTT flightsumarsuflightvb [4.3.3a]


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Setup Analysis #2

Both data & strobe propagate over the interconnect. Goal: identical flight times.

In reality, there will be some difference in flight times between data and strobe. trace length, loading, crosstalk, ISI, etc.

Define flight time skew for the setup condition:

Simplify the loop equation:

sumarflightflightsuvb TDATATSTBTTT min, [4.3.4a]

[4.3.5a]

sumarsuskewsuvb TTTT min, [4.3.6a]


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Notes on the Setup Equation

You may see the timing equation written in other forms.

The way I defined Tvb makes it a negative quantity. Others may define it to be positive.

I defined Tsuskew to be a positive quantity.

sumarsuskewsuvb TTTT min, [4.3.7a]


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Hold Timing Diagram & Loop Analysis

t

DATADRIVER

DCLK

Tflight(STB)

Tco(STB) Tco(DATA)

Th

Thmar

DATARECEIVER

TBCLK/4

BCLK

TBCLK

STB/STBDRIVER

RECEIVER STB/STB Tflight(DATA)

04 STBTSTBTTTDATATDATATTcoflightholdhmarflightco

BCLK


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Hold Analysis

Just as for the setup case, we need to specify the minimum phase relationship between data and strobe:

04 STBTSTBTTTDATATDATATTcoflightholdhmarflightco

BCLK

In addition, define the flight time skew for the hold case:

In addition, define the flight time skew for the hold case:

Note that the Thskew is defined such that it is a negative quantity, while Tva is defined to be positive.

[4.3.8a]

4minmin,BCLK

cocovaTSTBTDATATT [4.3.9a]

min

STBTDATATT flightflighthskew [4.3.10a]

hmarhskewholdva TTTT min, [4.3.11a]


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Maximum Transfer Rate

The maximum transfer rate can be determined using the definitions for Tva and Tvb.

minmin,4 STBTDATATTT cocovaBCLK

maxmin,4 STBTDATATTT cocovbBCLK

We can calculate the limit of TBCLK (for a double pumped bus) by adding the two equations above.

min,min,min, 4 vavbBCLK TTT

DATA

Tva,min

STB/STB

-Tvb,min

Tcycle,min

[4.3.12a]


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Higher Transfer Rates (e.g. “Quad Pumped”)

The setup and hold equations remain the same. What changes are the Tva and Tvb definitions:

BCLK

DATADRIVER

RECEIVER

STB/STBDRIVER

DATARECEIVER

TholdTflight(DATA)

Tco(STB)

Tflight(STB)

Tco(DATA)

Tmargin

DCLK

TBCLK/8

TBCLK

STB/STB

BCLK

DATADRIVER

RECEIVER

STB/STBDRIVER

DATARECEIVER

Tsetup

Tco(STB)

Tflight(STB)Tco(DATA)

Tmargin

DCLK

TBCLK/8

TBCLK

STB/STB

Tflight(DATA)

8maxBCLK

cocovbTSTBTDATATT

8minBCLK

cocovaTSTBTDATATT

[4.3.13a]

[4.3.14a]

© h. heck 2008section 4.31 module 4:metrics & methodology topic 3: source synchronous timing...

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