中華大學碩士論文 -...

中華大學

碩士論文

題目應用於無線通訊系統中之 5GHz頻率合成器

5GHz Synthesizer Application in Communication

系所別電機工程學系碩士班

　　　學號姓名M09101002 黃佳清

指導教授田慶誠博士

中華民國　九十四　年　一　月

2

摘要

在無線的通訊系統中頻率合成器一直扮演著很重要的角色而頻率合

成器的組成包括高頻的電壓控制振盪器雙模預除器等低頻的包括相位頻

率偵測器充電幫埔和迴路濾波器等

本論文使用台積電 TSMC 018um製程模擬應用於通訊系統中 5GHz頻段的頻率合成器並且使用安捷倫的 ADS 做為模擬的軟体以下簡要說明各章節內容

第一章緒論說明本論文之研究動機及其相關背景

第二章頻率合成器之簡介主要元件的介紹同時也介紹射頻 PLL 電路

之設計考量

第三章利用 TSMC RF CMOS 018um製程的model並使用模擬軟體 ADS來進行模擬與設計

第四章 RF IC LAYOUT 建議

第五章結論

3

ABSTRSCT

Frequency synthesizer has been an important part of radioCommunication system Frequency synthesizer is consist of high frequentcomponent such as VCO (Voltage Control Oscillator) and DMP (DualModule Prescaler) and low frequent component such as PFD (Phase

Frequency Detector) Charge Pump and Loop Filter

The main topic of this thesis is to use RF CMOS 018um manufactureprocess of TSMC (Taiwan Semi-conductor Manufacture Company) tosimulate 5GHz Frequency Synthesizer which is widely used in generalcommunication system The whole simulation is conducted on ADS(Advanced Design System) of Agilent

Here is the brief introduction of this thesis

Chapter 1 Introduction explanation of the main motivation and relatedbackground of the research

Chapter 2 Introduction of Frequency Synthesizer- the introduction ofmain component of Frequency Synthesizer and the design consideration

Chapter 3 Circuit Simulation- to use RF CMOS 018um manufactureprocess of TSMC to simulate 5GHz Frequency Synthesizer

Chapter 4 RF IC LAYOUT Guide

Chapter 5 Conclusion

4

誌謝

在二年研究所的學涯中首先我必需感謝我的指導教授田慶誠博士

由於他的指導與協助才得於完成今天的論文除了在論文的指導外

更是我們往後人生中的亦師亦友也是我們的百科全書包括做人處事

打拼事業都再再使我由衷的謝謝他

再來我必需感謝我的同學學敏阿柏阿 B嘉豪宗憲黃新家銓和太多我所無法一一提及的同學研究室所有共同打拼的戰友及學弟們

有了大家的包容和照顧小弟有幸能伴大家渡過這兩年多黃金般的歲月

大家往後加油了

最後我想最需要感謝的就是我的老婆小 baby(妤涵)和我的家人有了你

們的支持和鼓勵才有今天的我更上一層樓我將感謝所有包容我鼓

勵我和所有的所有幫助過我的人謝謝你們了

5

目錄

中文摘要 2

ABSTRACT 3

誌謝 4

目錄 5

圖表目錄 7

第一章緒論 11

第二章頻率合成器之簡介 13

2-1何謂 PLL Synthesizer 及其動作原理 13

2-2 主要元件的介紹 16

2-2-1相位頻率偵測器(Phase Frequency Detector PFD) 16

2-2-2充電幫浦(Charge Pump) 22

2-2-3迴路濾波器(Loop filter) 24

2-2-4預除器(Prescalar) 30

2-3射頻PLL電路之設計考量 31

第三章電路模擬 33

3-1相位頻率偵測器模擬 33

3-1-1實驗電路模擬環境 33

6

3-1-2 PFD模擬結果 34

3-1-3電路改良及模擬結果 Glitch Free 35

3-1-4模擬結果 36

3-2充電幫埔(Charge Pump) 模擬 39

3-2-1充電幫浦電路與模擬設定 40

3-2-2模擬結果 (相位頻率偵測器+充電幫浦) 41

3-3預除器(pre scalers )除三十二三十三 47

3-3-1除四除五電路與模擬 47

3-3-2預除器模擬結果 49

3-4十四位元移位暫存器及栓鎖正反器 55

3-4-1 14bit Shift 模擬 55

3-4-2移位暫存器和栓鎖電路 57

第四章 RF IC LAYOUT 建議 62

第五章結論 79

參考文獻 80

7

圖表目錄

圖 11 通訊系統收發器方塊圖 12

圖 12 頻率合成器方塊圖 13

圖 21 數位式比較器代表OR 16

表 21 OR 真值表 16

圖 22(a)相位頻率偵測器示意圖

(b)輸入輸出波型表示圖 17

圖 23相位頻率偵測電路圖 17

圖 24 相位頻率偵測器三態圖 18

圖 25 傳統式的相位頻率偵測器 19

圖 26 相位頻率偵測器 Dead Zone 示意圖 20

圖 27電荷幫浦的簡單模型 22

圖 28 電荷分享示意圖 23

圖 29 一階迴路濾波器 24

圖 210 二階迴路濾波器 27

圖 211 除八電路 30

圖 212 除四除五電路 30

8

圖 213 除四除五 waveform 30

圖 214 PLL電路方塊圖 31

圖 215 PLL迴路濾波器設計 32

圖 216 迴路濾波器 Response 32

圖 31 正緣及負緣觸發的TSPC DFF 33

圖 32 相位頻率偵測器電路圖 33

圖 33 相位頻率偵測器模擬設定 34

圖 34 DIV頻率領先REF 34

圖 35 REF頻率領先DIV 35

圖 36 電路改良 Glitch Free 35

圖 37 PFD Dead Zone 36

圖 38 PFD Glitch free模擬結果 37

圖 39 Simple mos current mirrors 39

圖 310 Cascade current mirrors 39

圖 311充電幫浦電路 40

圖 312充電幫浦模擬設定 40

圖 313充電幫浦電流 41

圖 314鎖定時無輸出 42

圖 315迴授頻率領先時放電 43

9

圖 316參考頻率領先時充電 44


圖 318參考相位領先時充電 46

圖 319加入 NAND 的 TSPC DFF 47

圖 320 TSPC DFF 47


圖 322 除四除五模擬設定 48

圖 323 除四模擬結果 49

圖 324除五模擬結果 49

圖 325除八電路設計(Divideramptemp) 50

圖 326除三十二三十三電路設計(Divider32_33_dis) 50

圖 327除三十二模擬結果 51

圖 328除三十三模擬結果 51

圖 329 Preamp+除頻器 52

圖 330 Preamp 電路 52

圖 331 Preamp 模擬結果 53

圖 332 Preamp+除三十二模擬結果 53

圖 333 Preamp+除三十三模擬結果 54

圖 334 十四位元移位暫存器 55

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圖 335 移位暫存器 SELL 56

圖 336 ALTERA 移位暫存器 56

圖 337移位暫存器 data shift 56



圖 340 Data Latch 後資料 58

圖 341栓鎖正反器電路 59

圖 342可程式計數器 60

圖 343計數器SELL 60

圖 344可程式計數器模擬設計 61

圖 345可程式計數器模擬結果 61

11

第一章緒論

九０年代後期起由於網際網路的通用化帶動PC轉為網路集中式而

無線通訊技術的快速發展以及全球性電信自由化也加速網路通訊的發

展以及網際網路的普通化使資訊通訊及網路迅速進入消費者個人

家庭及辦公室

在所謂科技結合資訊通訊及消費電子三大領域以系統科技結合個人

電腦系統通訊系統及家電系統形成在使用者端的資訊家電或(IA）或網際網路家電（Internet Appliances IA）系統

此外網路骨幹（Network Backbone）部份也會開始連結到公眾服務電話網

路廣播電視有線電視無線網路等形成網網相連到天邊的通用網

路各式各樣的軟硬體科技都匯集在網路中網路服務及應用科技亦快

速發展以提供高品質服務及開發高創意應用

在個人電腦時代半導體積體電路技術扮演著很重要的角色藉由半導

體技術的發展高性能中央處理器（CPU）及記憶體積體電路才能迅速的

研發成功帶動個人電腦性能提升和廣泛使用

在後PC 時代半導體積體電路技術依然將扮演極重要的角色半導體技

術在1999 年量產進入018 微米未來發展趨勢仍是線寬縮小密度提昇

電晶體數量增加且功能逐步強大在此趨勢下單一晶片集積的電晶

體數將超過在10 億以上而可以將整個系統在單一晶片上實現因此單晶片系統(SOC）就成為二十一世紀全世界所矚目的重點關鍵核心技術單晶片系統就是建立於矽晶片之大型系統內含內嵌式軟體（Embedded-Software）微處理器（Micro Processor）數位訊號處理器（DSP）邏輯IC類比IC介面IC還有無線通訊用的RF-IC 等運用高效率設

計技術設計實現在加上應用服務管理軟體等相關知識內涵後即可

廣泛應用於資訊通訊及消費電子3C整合產品在網際網路數位聚合

及單晶片系統三大推動力之下形成後PC 時代科技與產業的革命使資訊通訊及消費電子聚合成3C 一體的二十一世紀後PC 新興時代科技與產業

12

在這一個二十一世紀知識暴發的時代裡科技技術不斷的進步無線通

訊已經偷偷的在我們的世界中佔有一席之地了我們的週遭愈漸充刺著

無線的產品也使的射頻頻譜愈來愈擁擠因此許多的通訊系統選擇在 ISM免授權頻帶如藍芽(Bluetooth) 24Ghz無線區域網路(WLAN) 24Ghz 和52Ghz 而在通訊系統硬体實現中包含幾個重要的區塊(block)包含有從天線進來的 LNA MIXERVCODACADCAGC 等而要信號(升頻)或接收(降頻)則都需要一個 LO(Local oscillator)本地振盪參考頻

率來與MIXER 做用所以本論文即為 RF 通訊中的一個重要元件

圖 11 通訊系統收發器方塊圖

13

VCOKvco

PhasefrequencyDetector

Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV

參考頻率振盪器參考頻率除頻器

頻率預除器及除頻器

相位頻率偵測器

低通濾波器

電壓控制振盪器

ChargePum p Vct

電荷幫埔

Dn

Up

第二章頻率合成器之簡介

2-1何謂 PLL Synthesizer 及其動作原理

新一代本地頻率振盪器架構中最主要的核心少不了相位鎖定迴路〈PhaseLocked LoopPLL〉這個部分鎖相迴路發展至今已有幾十年的歷史了

大部分用來作為對時脈或頻率的精確控制舉凡電視收音機等無線電波

的頻率調諧或是 CD與 PC等數位產品的時脈控制的場合皆可以使用 PLL來設計頻率控制迴路以簡化電路的複雜度增加精確性

一個頻率合成器是可以讓設計者產生多種不同頻率他最主要的應用

是在產生本地振盪(LO)訊號來與混波器做混波使 RF訊號升頻或降頻

頻率合成器的動作原理是在一個鎖相迴路中完成由相位頻率偵測器(PFD)把迴授回來的頻率及其相位(DIV)跟所輸入的參考頻率(REF)做一個比較比較參考頻率與回饋頻率兩者間的差別然後把結果輸出為 Up 和 Dn 的訊號當參考頻率高於回饋頻率時PFD Up端會輸出 Up脈波反之若是

參考頻率低於回饋頻率時PFD Dn 端會輸出 Up脈波對電荷幫埔做充放

圖 12 頻率合成器方塊圖

14

電流的動作而電荷幫埔的輸出對迴路濾波器做充放電的動作轉換成

為最後一階電壓控制振盪器(Voltage Control Oscillator VCO)的控制電壓使之產生直流位準的改變Vct 直流訊號的輸出藉此直流輸入至電

壓控制振盪器(VCO)的 Vtune 使其改變頻率如此追蹤參考頻率經過一

段時間後即達到 VCO 穩定的輸出使之與參考頻率同步保持一致的相位

與頻率狀態當回饋輸入頻率(F-DIV)與參考輸入頻率(F-REF)的頻率與相

位一致時也就是整個相位迴路已經鎖定了(Locked)

在數位應用時時脈產生器藉著 PLL 的相位鎖定特性於 PLL 的兩個輸

入端與輸出端若將參考輸入頻率(F-REF)與回饋輸入頻率(F-DIV)之後分別接上除頻電路如上圖中的 N與 R的除頻器當 PLL 處於穩定鎖定的狀態時PFD的兩的輸入端頻率與相位應為相等如式子(2-1-1)

F-REF R = F-DIV N helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip(2-1-1)

所以

F-DIV= F-REF N Rhelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip

因為實際的輸出端還可以接一個除頻電路 Q所以時脈產生器的輸出頻率就會變成如式子(2-1-2)

Fout = ( F-REF N ) ( R Q)helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip(2-1-2)

電路設計工程師們藉由改變時脈產生器中除頻電路的參數搭配變動

NRQ 之間的比率便可以很容易的由一個基準的參考頻率訊號源

產生出電路中所需要的各種頻率時脈訊號

PLL 在時脈電路中除了應用在時脈產生器之外還可以發揮其相位鎖

定的特性進而延伸發展出各種時脈電路相關的應用元件

例如

要求非常高的時脈訊號品質訊號的數位電路上的零延遲緩衝器〈ZeroDelay Buffer〉

15

電子電路板上許多元件都需要使用時脈訊號來做同步的運作但是由

時脈產生器所提供的時脈訊號可能在數量上並不足以供應所有元件之

所需因此必須另外加裝訊號分配器〈Distributor〉或訊號緩衝器〈Buffer〉來獲得額外的時脈訊號訊號分配器可以複製原有單一的時脈訊號來源

產生許多組與原時脈相同的輸出訊號而訊號緩衝器則可以增強時脈訊

號的電流供應能力驅動低阻抗或是並聯接續的後端元件

但是外加的訊號分配器或訊號緩衝器都有一個無法避免的缺點那就是

對原始時脈訊號或多或少造成一定程度的傳遞延遲現象 (PropagationDelay)

假設有一些元件例如微處理器直接由時脈產生器提供時脈訊號而其餘

的週邊元件例如記憶體與晶片等則因為需要較多的訊號而透過訊號分

配器來提供時脈訊號此時就會因為訊號分配器造成的信號延遲而使

記憶體或晶片與微處理器之間達不到同步的狀態致使電路無法正常運

作這種情況更因電路運作速度越來越高元件對時序〈Timing〉誤差的容許時間縮小而更加明顯

內含 PLL電路所設計出來的零延遲緩衝器〈Zero Delay BuffersZDBs〉利用 ZDB 內部或外部信號回授的機制使緩衝器輸出端的訊號與參考訊

號來源的時脈訊號達到相位同步並鎖定的目的

ZDB 不但能輸出沒有延遲的時脈信號我們更可以利用一些小技巧來提

前或延後輸出訊號的相位像是在佈線時將負回授的線路加長或是加

上延遲線路增加回授負載電容量等使 ZDB 負回授端反饋的信號落後

參考時脈訊號源就會迫使的 ZDB 輸出端的訊號相位提前以保持負回授端與參考時脈訊號相位的一致反之若縮短負回授的線路使負回授

端反饋的信號提前就會使 ZDB輸出端訊號的相位往後延遲

ZDB 可控制輸出時脈相位的功能加大機板在佈線時的彈性使各元件間接收到的時脈訊號都可以保持相位的同步甚至如外接式的設備像

是 USBIDE 光碟機等都可利用 ZDB 使時脈訊號相位提前防止因連

接線路過長所造成的時序延遲現象

16

2-2 主要元件的介紹

2-2-1相位頻率偵測器(Phase Frequency Detector PFD)

在鎖相迴路中相位頻率偵測器對系統主要的影響有

(1)相位誤差由於 Dead Zone 的存在或本元件本身的偏移誤差將使得鎖相迴路的輸出產生誤差

(2)鎖定時間在鎖相迴路中鎖定時間與相位頻率偵測器充電幫埔和濾波

器有相對的關係

(3)Vtune 的變化量當相位頻率偵測器的輸出至充電幫浦時如果變化量

過大則容易造成電壓控制振盪的輸出頻率不再穩定使相位誤差變大

最後失鎖然後再重新鎖定

(一)功能說明相位頻率偵測器(Phase Frequency Detector PFD)或稱為相位頻率比較器(Phase Frequency Comparator PFC)即是比較基準參考頻率(F-REF)及迴授頻率（F-DIV）兩者之間的相位關係與頻率的差異並檢知

出兩者的相位的落差量及頻率的高低值然後將差異的量用電壓脈波表

示出來

基本上要將二種信號比較可以使用乘法器這跟一般電視機的聲音解

調器或 FM-接收機的檢波器很相似相位檢波器頻率混波器(Mixer)同步檢波器等都是包合在這一類中比較器的方法可以分為類比式和

數位式的類比式的以頻率混波器為代表而數位式的則以採用 OR Gate

OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2

圖 21 數位式比較器代表 OR

表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK

相位頻率偵測器F-REF

F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up

圖 22(a)相位頻率偵測器簡意圖

(b)輸入輸出波型表示圖

圖 23相位頻率偵測電路圖

18

圖 23 即是一般的 PFD 電路圖以兩個 D 型邊緣觸發正反器來檢知兩個

信號時脈邊緣的相位差（在此也可當作時間差）當 F-REF 超前 F-DIV時Up高電位輸出當 F-DIV超前 F-REF時Dn高電位輸出

圖 2-2(b)PFD 動作示意圖 (左) F-DIV 相位領先 F-REF

(右)為 F-REF 頻率大於 F-DIV

圖 2-2(b)左 F-REF 與 F-DIV 的頻率相同但其相位不同 F-DIV 領先 F-REF其輸出 Up 持續為低電位而 Dn 產生一個脈波其脈波的寬度則

為 F-DIV 減 F-REF反之同理

圖 2-2(b)右 F-REF的頻率大於 F-DIV所以 Dn 輸出為低電位而 Up 產生一個脈波其脈波的寬度則為 F-REF減 F-DIV反之同理

當 F-REF 和 F-DIV 頻率及相位相同時則 Up 與 Dn 則同時為低電位不會輸出任何的脈波

由以上之結果我們可以把相位頻率偵測器的動作歸納為一個三態的狀態

表現可用以下的圖 2-4表示

A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2

圖 24 相位頻率偵測器三態圖

19

我們將上圖分為三個步驟來說明

(1) 當 INIT 的狀態時處於狀態 0Up=0Dn=0 同時為零此時若參考

頻率 A 由低電位至高電位時則觸發(trigger)使 Up 的輸出為 1跳至狀態 1反之如迴授頻率 B由低電位至高電位的則 Dn的輸出為 1跳至狀態 2

(2) 當處於狀態１時Up=１Dn=0此時如果參考頻率 A 由低電位至高電位時則仍處於狀態１當迴授頻率 B 由低電位至高電位時則Up=1Dn=1同時為 1短時間馬上發生重置(RESET )則回到狀態 0

(3) 當處於狀態 2 時Up=0Dn=1此時如果參考頻率 B 由低電位至高電位時則仍處於狀態2當迴授頻率A由低電位至高電位時則Up=1Dn=1同時為 1短時間馬上發生重置(RESET )則回到狀態 0

(二_)傳統相位頻率偵測器

U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV

圖 25 傳統式的相位頻率偵測器

20

a 當輸出訊號 up 為 1 時則表示參考頻率的頻率或相位領先使充電

幫埔充電致使 vco 的控制電壓(vtune)上升頻率随之上升一直到

迴授頻率與參考頻相等為止才停止動做

b 當輸出訊 dn 為 1 時則表示迴授頻率的頻率或相位領先使充電幫

埔放電致使 vco 的控制電壓(vtune)下降頻率随之下降一直到迴

授頻率與參考頻相等為止才停止動做

c 當 up 為 0 dn為 0 時此時則鎖相迴路為鎖定的狀態

(三)重要的性能參數

(a)Dead Zone 沒有輸出時的輸入範圍

當參考頻率與迴授頻率相等時其輸出所能反應的最小相位差

即為 Dead Zone而其存在的原因為

(b)邏輯閘有路徑的延遲所以無法產生無限小的脈波

(c)充電幫埔打開的延遲

因為元件有閘的延遲(Gate delay)所以當參考頻率與迴授頻率相位差小

於邏輯閘所反應時間時其輸出以然是無法正確的反應輸入的相位差

或頻率差如圖 2-5 傳統式的相位頻率偵測器其從輸入至輸出至少有六

個閘的延遲所以其輸出具有較大的 Dead Zone 較低的操作速度與靈

敏度

21

理論上來說 Dead Zone是愈小愈好但是因為振盪器本身就有相位誤差所以如果一味的追求零 Dead Zone 而使的電路架構擴大這可能是需要評

估的事

(d)最高操作頻率

這一個參數是表是當參考頻率與迴授頻率相位差在 90 ο 相位頻率偵測器

的輸出仍然是正確時的最高頻率當參考訊號大於最高操作頻率並不

代表鎖相迴路無法鎖定只是會有較大的相位誤差

(e)相位偏移

當鎖相迴路處於穩定時理想上相位偏移量為零度但是因為有佈局方

面的誤差與充電幫浦充放電的不匹配所以多少仍會有相位的偏移而

相位的偏移會造成迴路的相位誤差與時域的 jitter

圖 26 相位頻率偵測器 Dead Zone 示意圖

22

2-2-2充電幫浦(Charge Pump)

充電幫浦的功能是將相位頻率偵測器所比較出來的兩頻率的誤差值電

壓脈波轉換為一類比式的電壓值對其後部的迴路濾波器做充放電而

充電幫浦可分為電流式的與電壓式的架構電路因為電壓式的電路易受

其電源 VDD 的變化而影響輸出所以一般均採用電流式的充電幫浦因

其可以使用電流鏡來做為一個穩定的電流不易被影響

(一)電荷幫浦的動作概念

電荷幫浦為接收前一級的相位頻率偵測器的輸出 UP 和 DN當 UP 為高態DN 為低態時開關 A 導通開關 B 不導通此時 Iup 的電流流向

C 使電容 C的電位上升(充電)當 DN為高態且 UP為低態時開關 B導通開關 A 不導通此時 C的電流流向地使電容 C的電位下降(放電)當 UP 和 DN 的電位都為低態時則開關 A 和開關 B 同時不導通不對

電容 C做充放電的動作Vc保持電位不變

(二)在鎖相迴路中充電幫浦(Charge Pump)對系統主要的影響有

(a)相位的誤差

鎖相迴路中充電幫浦對相位頻率偵測器造成的相位偏移會加大系統

的相位誤差而造成相位偏移的原因為充放電的不匹配（為佈局及

電路本身因素）及電荷的分享的效應（如圖）

圖 27 電荷幫浦的簡單模型

23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆

如圖 C1充電至 VCCC2 放電至 VSS當 S1和 S2導通時因為 C1和 C2 兩寄生電容會與實際電容 C 做電荷分享的效應而使 C 上的電容因而有充電或放電的效果而使的鎖相迴路的相位誤差變大

(b)鎖定時間

充電幫浦之所以會影響鎖相迴路主要在於其充電和放電的電流大小

太大的電流因為容易補過頭了會使系統不穩定但鎖定時間較快且

鎖定的時間和後級迴路濾波器的時間常數有關所以必需與其做一通

盤的考量取捨配合才不會使阻尼因素ζ 過大或過小而影響鎖定的

時間

Charge pump 的相位雜訊 Phase noise 在 pll中並不是很重要的

1) 有兩個重要的因素

2) 電流的不匹配(Current mismatch) 它會產生虛頻(spur)

3) 積体電流 noise 它會影響產生 VCO相位雜訊由以下式子可知

(充電幫浦輸出平均電阻)(迴路濾波器的 Transfer Function)Kvco

所以我們在討論相位雜訊(phase noise) 從 charge pump中產生的原因他是因為積体電流雜訊並不是相位雜訊(phase noise)

圖 28 電荷分享示意圖

24

2-2-3迴路濾波器(Loop filter)

迴路濾波器主要功能為連接充電幫浦的注入或抽出電流而使 VC的直流

信號上升或下降藉此直流控制後級的電壓控制振盪器振盪出不同的

頻率而迴路濾波器的頻寬和系統的鎖定時間成正比和系統的相位雜

訊成反比

(一) 一階被動式迴路濾波器

一階的迴路濾波器是由一個電阻和一個電容產生

R1

C

LOOP FILTER

T=1fr 參考頻率的週期

ωu=2 π sdot fu Unity Gain FrequencyN=fofr 迴路除值

Kφ=I2 π 相位頻率偵測器的增益

I 充電幫浦電流

PMdes 70deg = Phase Margin (50~70 degrees 建議值)開迴路 transfer functions

GH (s )= Kφlowast s C11sC1 R1 +

lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ

ω helliphellip(2-2-3-

1)開迴路增益角度

圖 29 一階迴路濾波器

25

AngleGH (ωu)=atan (ωu_ωz )minus180deg (2-2-3-2)

phase margin 因此可以得到PM (ωu_ωz) =atan (ωu_ωz) (2-2-3-3)

零點的位置

ωz=ωuωu_ωz (2-2-3-4)

magnitude transfer function可以得到

MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)

(s) = IpumpVturn (s) = R +

PsC1 (2-2-3-6)

圖29顯示了一階濾波器且其轉移函數可以表示成

F(s)=IV = (

11

1sC

R + ) (2-2-3-7)

將式子(2-2-3-7)帶入則整個PLL的轉移函數為

H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26

ξ為阻尼因數(Damping ratio)一般最佳值為0707 nω 為自然振盪頻率

(2-2-3-8)式中的G(s)為PLL系統的開迴路轉移函數

G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω

當 )(sG =1時ω會大於 zω 所以此時

G(s)Ms

RKIMs

sRKI vcopumpvcopump 12

1 =asymp (2-2-3-10)

此時定義 cω =N

RKI vcopump 1 為開迴路增益G(s)的單位增益頻寬由(2-2-3-8)式

可知當 zc ωω gtgt 此時閉迴路增益H(s)下降3dB換言之 cω 即為我們所設計之

系統閉迴路頻寬(Closed loop filter bandwidth)

所以可以將(2-2-3-9)式改寫成

G(s)= cω 2

)(s

sz +ω (2-2-3-11)

而ξ和 nω 同樣可以代入 cω 來表示

z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27

(二)二階濾波器

二階的被動式迴路濾波器

R

Cp

C

LOOP FILTER

F(s) = F(1+sTz)s(1+sTp)Cp = integrating capC=可以濾掉 ripple 雜訊R可以增進phase margin會減少ripple

F(s) = IpumpVturn (s) = (R +

PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)

圖 210 二階迴路濾波器

28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)

二階濾波器為一階濾波器並聯一電容因為在一階濾波器中R可以

提供一個零點並使 phase margin(PM)小於 180 度來使 PLL的系統穩

定但其缺點是當每一次電流被注入濾波器時控制電壓會產生一個

大的跳動而使得此擾動嚴重的影響 VCO並破壞其輸出相位而

並聯一電容則可以緩和 R所造成的電壓抖動一般 C所並聯的電容

值約為 Cp的101~

51

倍即 1pω 是 zω 的 5~10倍所以 Phase Margin大

約可從 30 ο ~45 ο

而二階濾波器的轉移函數為

S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω

此時鎖相迴路的開迴路轉移函數可以表示成

29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)

此時 cω 為開迴路增益G(s)的單位增益頻寬

而為了求系統穩定此時將 zω 與 1pω 的幾何平均數定義成 cω

即 cω = 1pz ωω bull 此時 )(sG =1(s= cjω ) (2-2-3-23)

因此整個PLL的轉移函數為

)(1)()(

sGsGMsH

+bull

= (2-2-3-24)

在此我們定義一個參數γ

c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)

利用2-2-3-21式代入可得

12

2

1 minus= γCC

cω =M

KRI vcopump )11( 21 γminussdot

(2-2-3-27)

而當 S=j cω 時以知開迴路增益 G(S)=1 可得閉迴路增益

H(s)=γγ

γγj

jM+

minus+2

2 )1(2

若 γ gtgt1則 asymp)(SH2M亦即 cω 可視為閉迴路濾

波器頻寬(closed loop filter bandwidth)

30

2-2-4預除器(prescale)

在頻率合成器中除中電壓控制振盪器外再來最高頻的元件就是預除器(除四除五)了他接收振盪器的高頻率將他做除頻的動作將其降至較低

頻然後接至可程式計數器

一個基本的除頻器可以用D Flip-Flop來完成它是利用D Flip-Flop的輸出端反向拉回至輸入端而形成一個除二的除頻器如圖211所示將三個除二的除頻器串接即為一個除八電路

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout

圖 211 除八電路

圖 212 除四除五電路

圖 213 除四除五 waveform

31

2-3射頻PLL電路之設計考量

在考慮一個 PLL 頻率合成器什麼是重要的參數呢

其主要的參數為相位雜訊(Phase noise)參考虛頻(reference spurs)和鎖定時間(lock time)今天高規格的 RF 頻率合成器通常需要

(1)能夠有夠寬的頻率範圍至少要比需求的範圍大

(2)能夠平順的切換通道

(3)能夠有夠小的相位抖動(Phase jitter )和頻率的變動

(4)能夠有濾波器整合在ic 內

在一般的鎖相迴路中如圖214由五個主要組成的的方塊包括VCO[3]高頻的除頻器通常也稱為 prescaler 相位和頻率偵測器充電幫浦和

迴路濾波器經由改變除頻器的除數鎖相迴路可以合成一個新的頻率

圖 214 PLL電路方塊圖

32

圖 215 PLL迴路濾波器設計

圖 216 迴路濾波器 Response

33

第三章電路模擬-使用（ADS2002～2003C）來進行模擬

3-1相位頻率偵測器模擬

本論文使用 TSPC 架構的 DFF 此種架構有省電及操作頻率高的優

點

True Single-Phase Clocked (TSPC)

3-1-1實驗電路模擬環境

圖 32 相位頻率偵測器電路圖

圖 31 正緣及負緣觸發的 TSPC DFF

34

3-1-2 PFD模擬結果

(1)當 DIV頻率領先 REF時則 Dn 輸出一脈波其寬度為 REF減DIV反之同理

圖 33 相位頻率偵測器模擬設定

圖 34 DIV頻率領先 REF

35

3-1-3電路改良及模擬結果 Glitch Free

圖 35 REF頻率領先 DIV

圖 36 電路改良 Glitch Free

36

3-1-4模擬結果

(1)PFD Dead Zone為 100ps一般需含電流幫浦 Dead Zone稱之

圖 37 PFD Dead Zone

37

(2)PFD 動做正常且 Glitch Free

圖 38 PFD Glitch free模擬結果

38

模擬結果改良後的 PFD明顯的減少MOS轉態所產生的 Glitch

左圖為 DIV 頻率領先 REF時Dn產生脈波Up幾乎為 0

右圖為 REF頻率領先 DIV時Up產生脈波Dn幾乎為 0

39

3-2充電幫埔(Charge Pump) 模擬

本論文採用電流式充電幫浦並使用 cascade current mirrors 方式如下圖

Simple mos current mirrors

Mos Requlated cascade current mirrors

圖 39 Simple mos current mirrors

圖 310 Cascade current mirrors

40

3-2-1充電幫浦電路與模擬設定

VCT

VDD_D

VDD_D

TSMC_CM018RF_NMOSM23

Width=101 umLength=05 umType=18V_nom

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D

TSMC_CM018RF_PMOSM10


VDD_D



VDD_D



TSMC_CM018RF_RESR1

R=100 Ohml=27905 umw=2 umType=N+ Poly wi silicide (wgt=20)





VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6

I_ProbeI_Probe5 TSMC_CM018RF_NMOS

M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D




Width=10 umLength=05 umType=18V_nomTSMC_CM018RF_NMOS

M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D

VDD_DTSMC_CM018RF_PMOSM20




電壓設計為 18v頻率設定為 10Mhz接一電容 1nF

圖 311 充電幫浦電路

圖 312 充電幫浦模擬設定

41

3-2-2模擬結果 (相位頻率偵測器+充電幫浦)

(1)Pump 電流為 4674uA

當 PFD的輸出Up和Dn同時為高電位或同時為低電位時則Charge Pump輸出OUT保持原來的DC 電壓不做充放電的動作則VCO 的 control 電壓不變此時為 LUCK　的狀態則 VCO 的輸出頻率不再改變此結果

可看出 Charge Pump 的充電放電的電流為相等的 4674uA

圖 313 充電幫浦電流

42

(2) 鎖定時 UP與 DN均無輸出

當 PFD 的輸入迴授頻率(DIV)和參考頻率(REF)相同頻率和相位則其

輸出 UpDn為零使 Charge Pump 不對 loop filter 做充放電

圖 314 鎖定時無輸出

43

(3)迴授頻率領先時放電

當 PFD 的輸入迴授的頻率(DIV)領先參考頻率(REF)則其輸出 Up 為零Dn則為其頻率的差使 Charge Pump 對 loop filter 放電

圖 315 迴授頻率領先時放電

44

(4)參考頻率領先時充電

當 PFD 的輸入參考頻率(REF)領先迴授的頻率(DIV)則其輸出 Dn 為零Up則為其頻率的差使 Charge Pump 對 loop filter 充電

圖 316 參考頻率領先時充電

45

(5)迴授相位領先時放電

當 PFD 的輸入迴授的頻率(DIV)和參考頻率(REF)相同但 DIV的相位(Phase)領先 REF的相位(Phase)其輸出 Up為零Dn

則為其相位(Phase)的差使 Charge Pump 對 loop filter 放電


46

(6)參考相位領先時充電

當 PFD 的輸入迴授的頻率(DIV)和參考頻率(REF)相同但 REF 的相位(Phase)領先 DIV的相位(Phase)其輸出 D n為零Up

則為其相位(Phase)的差使 Charge Pump 對 loop filter 充電

圖 318 參考相位領先時充電

47

3-3預除器(pre scalers )除三十二三十三[9]

3-3-1預除器模擬結果

A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6

Width=11 umLength=018001 umTy pe=18V_nom

TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

圖 319 加入 NAND 的 TSPC DFF

圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1

圖 322 除四除五模擬設定


49

3-3-2模擬結果

(10除四電路MC=0

(2)除五電路MC=1 圖 323 除四模擬結果

圖 324 除五模擬結果

50

(3)除八電路設計

Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3

(4)除三十二三十三電路設計

QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4

圖 325 除八電路設計(Divideramptemp)

圖 326除三十二三十三電路設計(Divider32_33_dis)

51

(5)除三十二

(6)除三十三圖 327 除三十二模擬結果

圖 328 除三十三模擬結果

52

(7)加入 preamp 電路設計

pre_amp_out

IN

VDD_D

TranTran1

MaxTimeStep=(1frequ)01StopTime=80(1frequ) secStartTime=00 nsec

TRANSIENT

VARVAR1

frequ=6 GHzVDD_D=18 Vpow e=18 V

EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D

Pre_amp_outVc o _ ou t

V_DCSRC5Vdc=0 V

TSMC_CM018RF_PROCESSTSMC_CM018RF_PROCESS

Resistance=TypicalRFCornerCase=TTBIPCornerCase=TTCornerCase=TT

Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1

PhaseNoise=list(10Hz-20dB 100Hz-40dB 1KHz-50dB)Rout=50 OhmP=dbmtow (-10)Freq=frequ

in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_MIMCAPC1

Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1

R=1 kOhml=279054 umw=2 umType=N+ Poly wi si l icide (wgt=20)

TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2


PortPre_amp_outNum=2

TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3

圖 329 Preamp+除頻器

圖 330 Preamp 電路

53

(8)加入 preamp模擬結果

(9)除三十二

輸入 6G 的 200mV 的信號經過 pre_amp 的放大後加至除頻器輸出為1875Mhz

圖 331 Preamp 模擬結果

圖 332 Preamp+除三十二模擬結果

54

(10)除三十三

輸入 6G 的正負 200mV 的信號經過 pre_amp 的放大後加至除頻器輸出為 1818Mhz

圖 333 Preamp+除三十三模擬結果

55

3-4十四位元移位暫存器及栓鎖正反器

3-4-1 14bit Shift 模擬

資料由 CLK 和 Data 和 LE 三個 PIN 串列接入經由移位暫存器及栓

鎖正反器 latch住資料

CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4

Period=1frequWidth=05(1frequ)Delay=0 nsecVhigh=18 VVlow=0 V

DT

VtBitSeqSRC5

BitSeq=110100000000000Fall=0nsecRise=0 nsecRate=frequVhigh=18 VVlow=0 V

t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1

frequ=10MhzVDD_D=18 Vpowe=18 V

EqnVar

V_DCSRC1Vdc=powe

VDD_D

圖 334 十四位元移位暫存器

56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5

圖 337 移位暫存器 data shift

圖 335 移位暫存器 SELL

圖 336 ALTERA 移位暫存器

57

3-4-2移位暫存器和栓鎖電路

(1)輸入頻率 20Mhz做模擬Data IN=10111100010111

LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D

S5 O5S8 S11 O11S7 S4 O4S10 O10S6 S3 O3S5 S9 O9S4 S2 O2S3 S8 O8S2 S1 O1S OS1 VDD_DVDD_DVDD_D C



Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4

BitSeq=000000000000010000Fall=0secRise=0secRate=frequVhigh=18 VVlow=0 V

t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1

Freq[1]=10 GHzMaxTimeStep=01(1frequ)StopTime=16(1frequ)StartTime=08(1frequ)

TRANSIENT

VtSineSRC2

Phase=0Damping=0Delay=0 nsecFreq=frequAmplitude=09 VVdc=09 V

VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

圖 340 Data Latch 後資料

59

(3)栓鎖正反器盡量使用少量的 mos 數量

VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5


圖 341 栓鎖正反器電路

60

(4) 可程式計數器

D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B

VDD_DTSPC_DFF_counterX1

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D

LoadData_IN Load_BarDataIN_Bar

VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar


Width=32 umLength=018001 umType=18V_nom VDD_D

DataIN_Bar



VDD_DData_IN



Data_IN


Width=2 umLength=018001 umType=18V_nom Load_Bar



Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4

圖 342 可程式計數器

圖 343 計數器 CELL

61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1

MaxTimeStep=(1frequ)05StopTime=50(1frequ) secStartT ime=00 nsec

TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12

BitSeq=01111111111111111111111111111111111111111111111111111111111111111111111Fall=0Rise=0Rate=frequVhigh=18 VVlow=0 V

t

Load

VtPulseDTSRC4

Rout=1 OhmPeriod=1frequWidth=05(1frequ)Delay=0 nsecVhigh=18 VVlow=0 V

DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1

frequ=100MHzVDD_D=18 Vpowe=18 V

EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D2TSPC_DFF_counterX8

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D

m1time=1450nsecCLK=1800 V




140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2

Eqn in_time=(indep(m2)-indep(m1))

Eqn OUTT=(indep(m4)-indep(m3))

Eqn coun99=OUTTin_time

timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V

m3time=1003nsecOUT=1833 V




02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V

圖 344 可程式計數器模擬設計[9]

圖 345 可程式計數器模擬結果

62

第四章RF IC LAYOUT 建議

本章節是我們在 IC-layout 時應該注意的事項在 RF信號時這些細節更

應該去小心注意

1 繞線越長線的寬度就需越大可降低寄生電阻

2 MOS 的 Source 和 body 接在一起或 Source 的電壓和 body 的電壓相同rarrMOS 的 Source 可和ｎ + 或ｐ + Diffusion 連在一起 (butteddiffusion)

3 所有的元件（不包含電感）儘量擺近一點可減少繞線的長度

4 訊號線和訊號線不要上下疊在一起跑或靠得很近儘可能從 MOS 相對的兩端拉出訊號線和 DC bias的繞線較沒關係

Gate

12

Signal

63

5 兩訊號線在繞時中間可擺 ground metal做隔離

S1

12

S2

12

12

12

S1 S2

6 繞線轉彎的弧度不要太大至少用二次 45的轉彎轉成 90

Very Good

會相互 couple不好

訊號只被 bypass至 groundS1的訊號不會跑至 S2反之較好

Good Very Good

64

7 不同寬度的 metal要接在一起的時侯

　　　　　　

8 距離短的連接用下層的 metal（如 metal1metal2）較長距離可用

較上層因為較長距離的連接需較大的 widthrarr會有較大的 Area用較上層的 metal可降低寄生電容

　　　　　 Substrate

t1

Cp 較小t2

9 一條Metal 連接線的效應rarr會有 RLC

　　　　　

R2

Substrate

L1

除非特殊需求（如使用 Metal 繞電感或用 Metal 的寄生電容當 line電容ps一般較不會用Metal 來繞電阻）否則都希望 RLC的值最小降低 RLC最有效的方法是縮短Metal的長度

bad Good

65

10 RLC 的值對高頻訊號會有較大的影響所以一般多由高頻往低頻佈局

11 二 Metal相鄰就會有寄生的電容存在一般的設計是希望此寄生電容最小最簡單的方法就是增加二Metal的距離

變小了變小了

無法改變

12 如何將一條重要的 signal做隔離

( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal

無法改變一般較重的訊號最好避免在其上或下有其它的訊號在跑

上下二層及左右用 ground的 metal及 via包起來

缺點signal對 ground會有大的寄生電容

66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2

使用 well放在下面當一 ground平面rarr會耗掉較多的面積

若 signal1與 signal2 都是高頻訊號中間放一層 ground可避免相互干擾

67

13 儘量避免有銳角的元件

　　　

較好

Cap Cap

14 Well Contact Substrate Contact 越多越好可避免 latch up 及降低

noise

15 Analog的 ground必須與 Digital的 ground分開Digital的 ground絕對不能接至 P-sub會將 substrate 弄髒影響 Analog的 Performance

16 一般來說 N-well 接 VDD P-well 接 ground但若有一 Bias 比 VDD或 ground乾淨若此 Bias 不會讓 p-n junction forward bias則將 well接至此 bias會有較好的效果

68

17 如何讓 ground 更乾淨

(a) 增大 ground metal的 width

　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C

R L 變小可降低電流在 R L上的壓降 C變大可將 C上方的 AC訊號 bypass掉

69

(b) ground PAD畫大一點（至少是原來 PAD的二倍）可打二條以上的Bondwire降低 Bondwire的電感效應

　　　　

=

L1 2

L1 2

L1 2

L1 2

(c) ground的繞法儘量用樹狀結構不要有一大迴路

(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4

此 ground的Metal就像一天線會吸收高頻訊號亦即電路

亦受外界訊號干擾

70

18 Top layer Metal的特性最好因Metal的厚度大寄生的電阻小及距

substrate 遠寄生電容小應善加利用如Spiral Inductor 較長距離的連線 VDD或 ground 的拉線

19 一區域上不要有二個或二個以上的元件如在 MOS 上方擺上 MIMCap 或 Spiral inductorhellip等等亦即 MOS 的上方不要有其它的元件

或訊號線穿過RLChellip亦相同繞線最好從它們的旁邊繞過

20 對稱性的電路除了元件要對稱繞線亦要對稱

21 對稱性的MOSM1左邊是 DrainM2的 Drain需設在左邊

M1 M2

D DS S

較淡

GImplant

較淡

G

22 遇到須要對稱的電路所有可以做到的事情都須對稱 MOS 的元件要對稱MOS 的環境要對稱電流的流向要對稱繞線要對稱溫度

環境要對稱（亦即與等溫線正交）

PS (MOS的環境要對稱)

D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G

Dummy MOS是用來讓M1M2左右環境相同Dummy MOS可接成MOS Cap當 Bypass電容使用

71

23 Spir1 inductor外圍 20um以內不要有電路接近

Double Guard ring

20um

24 二互為反相的訊號經過二電感此二電感不要擺太接近且繞的方向

須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+

p-welln+ 接 VDDDeep N-well

Digital CKT 需用此 Guard ring完整的包圍起來

72

26 Passive的電阻電容下方擺上 P-Well及 Deep N-Well做 Shielding

p+ p+

M4

Deep n-well

MIM CaP

p-well

p+ n+n+p+ p+p+ p+ p+

p-well

n+ n+

Deep n-well

Poly

27 須要Match的MOSRC應多利用 Dummy Component使其環境相同

C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1

Metal的寄生電阻電容都對稱了

73

28 MIMPIP 兩端的特性不一樣

C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B

高頻時的等效電路

至少應視為

CKT designer決定兩端如何接

29 三明治電容

M5

M4

M3

M2

M1

30 VDD常會掛一 Bypass電容將 VDD上的 Ripple Noisehellip Filter掉

VDD

GND

C bypass

所以 VDD在佈局時可和 Ground的Metal交錯疊著(有如三明治電容)一來可節省面積再著VDD和 Ground的寄生電容亦變大可使 VDD

更 stable

74

31 大電流的 metal 在轉彎時應在 metal 中間挖幾個溝道尤其是高頻的電流時因為高頻訊號的電流只會流在金屬的表面(Skin effect)

　　　

增加截面外圍周長

　　　

電流分佈在金屬的表面

32 Share Drain(Source)降低 Drain(Source)的寄生電容

(a) 若高頻訊號只出現在 Drainrarr二個 MOS 並聯在一起再去找出所

需等效的 Channel width

S SD

G G

Guard ring

(b) 若高頻出現在 MOS 的 Drain 及 Source並聯多顆 MOS 使 Drain及 Source的 Area共用減少寄生電容

Drain共用等效寄生電容為單獨一顆MOS的一半

75

S S SD D D

(c) Bias 電路就不要使用上述二種 MOS因為寄生電容有益 Bypassnoise及 ripple

D S

G

33 對稱性的訊號 Signal path要 Balance

Cell

PAD

PAD

Cell

PAD

PAD

Signal path

不對稱 Signal path較對稱

用 Guard ring將此MOS包起來並聯的MOS 不要超過 10顆尢其是有大電流的MOS(因較容易 latch up)

76

34 PAD下面擺 Deep N-Well做 Shielding

Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5

35 PAD分 RFPADAC PADDC PAD(a) RF PAD八角形Area小一點M4-M5(b) AC PAD八角形(可較接近正方形)Area可比 RF PAD大M4-

M5(c) DC PAD接近方形(四個直角還是去掉較好)Area 不 CareM4-

M536 若 Bondwire的電感會影響電路此時可用 multi bondwire因此 PAD需要大一點參考 17(b)

37 不同層的 metal 相接Via 至少用二個若在大電流的地方則 Via越多越好

38 重要的 signal最好跑直接盡可能不要轉彎

39 兩 metal相接的地方盡可能在沒有轉彎的地方

差

好

修正如下會較好

77

探針要 Probe的 PAD(Low Freq Probe PAD)

Top layer metal

ViaPassive Window Via 為5um 5um

2um

2um

10um

10um

10um

PS此 Probe PAD 不適合用在高頻及訊號很微弱的地方通常用在

Probe某點的 DC值或某點低頻的Waveform 若那一點的 driving能力很弱則需使用 Active Probe(約 1pF電容並聯 10MΩ電阻的 Loading)

標準製程的 IC上要做出非常精準的 RLC是非常困難的除非事後用 Laser做 triming

On Wafer Probe高頻訊號時不能使用 Probe PAD高頻訊號量測

時有專用的 Probe head和 Probe holderProbe head通常有二種G-SG-S-GProbe PAD的畫法如下

PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um

這種 Probe PAD很容易 Probe但 Area有點大

78

大電流和較容易產生雜訊的電路應用 guard ring完整的包圍起來

以防止 latch up及隔離 noise

Poly通常只會被拿來做MOS的 gateResistor Capacitor盡量不要

拿來繞線除非特殊用途如下

M1 M2 M3 M4 M5 M6A B

S S S SD D D

AB

M1 M2 M3 M4 M5

M6

訊號由 ArarrB 時會有 RC delay所以 MOS 是由 M1 慢慢 turn on至M6若用在 Switch大電流時可降低 Power line的 spark

79

第五章結論

本論文以 tsmc 018um RF CMOS 製程來模擬 5Ghz的頻率合成器並希

望能達到 80211a WLAN 各項參數射頻為 U-NII 頻帶高頻段5725~5825Ghz 其中頻率合成器重要的元件之一電壓控制振盪器是採用

學長的設計未來目標是把電壓控制振盪器也加入電路設計

頻率合成器中訊號雜訊也是非常重要的參數這也是本論文尚未達到的

地方所以 vco與雜訊的分析將是未來做進一步研究的目標

80

參考文獻

[1] Razavirdquo類比CMOS積體電路設計rdquoMcGraw Hill電腦系列叢書2002年6月[2] C-Y Yang and S-I Liu ldquoFast Switching Frequency Synthesizer with a

Discriminator-Aided Phase Detectorrdquo IEEE Journal of Solid-StateCircuitOct2000

[3] 申仲加 rdquo應用於無線區域網之5GHz CMOS 壓控振盪器rdquo 中華大學電機工程研究所碩士論文2003 年7月

[4] C Y Yang G K Dehng J M Hsu S I Liu rdquoNew dynamic flip-flops forhighspeed dual-modulus prescalerrdquo IEEE Journal of Solid-StateCircuitvol33no10Oct 1998

[5] 陳幼林rdquo應用於80211a WLAN 之5GHz 頻率合成器設計 rdquo中華大學電機工程研究所碩士論文2003 年7 月

[6] 蕭天岳 rdquo鎖相迴路頻率合成器之暫態響應及相位雜訊研究rdquo 中華大學電機工程研究所碩士論文2001 年7 月

[7] 王周弘rdquo新型 Fractional-N頻率合成器之積体電路設計rdquo華梵大學

電機工程研究所碩士論文2002 年十一月

[8] Roland E Best ldquoPhase Locked Loops Design Simulation andApplicationsrdquo 4th Edition McGraw Hill 1999

[9] C-Y Yang G-K Dehng J-M Hsu and S-I Liu ldquoNew dynamic flipflopsfor high-speed dual-modulus prescalerrdquo IEEE J Solid-State Circuitsvol33 pp 1568ndash1571 Oct 1998

2

摘要

在無線的通訊系統中頻率合成器一直扮演著很重要的角色而頻率合

成器的組成包括高頻的電壓控制振盪器雙模預除器等低頻的包括相位頻

率偵測器充電幫埔和迴路濾波器等

本論文使用台積電 TSMC 018um製程模擬應用於通訊系統中 5GHz頻段的頻率合成器並且使用安捷倫的 ADS 做為模擬的軟体以下簡要說明各章節內容

第一章緒論說明本論文之研究動機及其相關背景

第二章頻率合成器之簡介主要元件的介紹同時也介紹射頻 PLL 電路

之設計考量

第三章利用 TSMC RF CMOS 018um製程的model並使用模擬軟體 ADS來進行模擬與設計

第四章 RF IC LAYOUT 建議

第五章結論

3

ABSTRSCT










4

誌謝











5

目錄

中文摘要 2

ABSTRACT 3

誌謝 4

目錄 5

圖表目錄 7

第一章緒論 11












6



3-1-4模擬結果 36











第五章結論 79

參考文獻 80

7

圖表目錄















圖 211 除八電路 30


8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











3

ABSTRSCT










4

誌謝











5

目錄

中文摘要 2

ABSTRACT 3

誌謝 4

目錄 5

圖表目錄 7

第一章緒論 11












6



3-1-4模擬結果 36











第五章結論 79

參考文獻 80

7

圖表目錄















圖 211 除八電路 30


8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











4

誌謝











5

目錄

中文摘要 2

ABSTRACT 3

誌謝 4

目錄 5

圖表目錄 7

第一章緒論 11












6



3-1-4模擬結果 36











第五章結論 79

參考文獻 80

7

圖表目錄















圖 211 除八電路 30


8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











5

目錄

中文摘要 2

ABSTRACT 3

誌謝 4

目錄 5

圖表目錄 7

第一章緒論 11












6



3-1-4模擬結果 36











第五章結論 79

參考文獻 80

7

圖表目錄















圖 211 除八電路 30


8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











6



3-1-4模擬結果 36











第五章結論 79

參考文獻 80

7

圖表目錄















圖 211 除八電路 30


8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











7

圖表目錄















圖 211 除八電路 30


8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











8




















9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











9





圖 320 TSPC DFF 47















10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











10












11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











11

第一章緒論




家庭及辦公室

















12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











12






13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











13

VCOKvco


Kd

Loop FIlterF(s)

PrescalerD ivide

1N

XTALReference

D ivider1R

REF

DIV




低通濾波器


ChargePum p Vct

電荷幫埔

Dn

Up











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











14










所以









例如


15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











15























16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











16












示出來




OUTf2

1

1

1

f1

1

0

Out

0

f1

OR Gate

0

1

0

U1A1

23

1

0

1

f2


表 21 OR 真值表

17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











17

U12

DFF

12

3QD

CLK

U13

DFF

12

3QD

CLK

U14

AND2

12

3

F-REF

F-DIV

Up

DnCLK


F-DIV

Up

Dn

F-REF

F-DIV F-DIVF-REF

Up

Dn Dn

Up




18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











18











A

A

A

B

B

Up=0Dn=1

Up=1Dn=0

Up=0Dn=0

B狀態0

狀態1狀態2


19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











19







U2A

14093

1

23

U3A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U4A

14093

1

23

U5A

14584

1 2

U5A

14584

1 2U5A

14584

1 2

U6A

4023FP

128

9

U5A

14584

1 2U5A

14584

1 2

U5A

14584

1 2

U8A

4023FP

128

9

U7A

4012

23

45

1

Up

Down

F-REF

F-DIV


20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











20


















敏度

21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











21


估的事





(e)相位偏移





22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











22












(a)相位的誤差





23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











23

C1

I2

0

I1

0C2

S2

00

S1

C

1

1

11

IVCtthen

QQciftIQ

VCQc

∆=∆

∆=∆∆=∆

∆=∆


(b)鎖定時間





時間








24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











24





訊成反比



R1

C

LOOP FILTER







lowast sKv

N1

=Ns

Kv 1sC1

1szK +Φ




25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











25



零點的位置



MagGH (ωu)=1=N

Kwu

wuC1

1wu_wz2 Φ+ Kv (2-2-3-5)


PsC1 (2-2-3-6)


F(s)=IV = (

11

1sC

R + ) (2-2-3-7)


H(s)= =)()(

ss

ref

out

θθ

)(1

2)(2

sGsKsF

I vcopump

+

bullbullπ

π (2-2-3-8)

=M1)(2)(

1)(2

2 ++

+

nn

n

ss

s

ωξ

ω

ωξ

= 22

2

22

nn

nn

sss

ωξωωξω++

+ M

其中 M

KIR vcopump

21=ξ 且

MCKI vcopump

n =ω

26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











26



G(s)= 21

21

11 )()1(

MssRKI

SMCC

sRKIzvcopump

vcopump +=

+ω

(2-2-3-9)

11

1CRz =ω


G(s)Ms

RKIMs


1 =asymp (2-2-3-10)

此時定義 cω =N





G(s)= cω 2

)(s

sz +ω (2-2-3-11)


z

Kω

ξ21

= 如果ξ =0707 則 zc ωω 2= (2-2-3-12)

zcn ωωω = 如果ξ =0707 則 nω = 2 zω (2-2-3-13)

27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











27



R

Cp

C

LOOP FILTER



PsC1 ) (

sC1 ) =

sCsCR

sCsCR

P

P

11

1)1(

++

+ =

sCsCR

CCssCR

P

P

11

12

++

+

=

CCssCsCCRCs

CCsRsC

P

PP

P

P

2

2

2

1

++

+

= )()(

12

PP

P

CCsCRCsRsC

+++ (2-2-3-14)

F(s) = ))((

12

PP

P

P

CCsCC

RCCsRsC

+++

+ = )1(

1

++

+

P

P

P

CCRsCCs

RsC

PCC +1 (2-2-3-15)


28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











28

F(s) =PCC +

1

ssCCCRC

RsC

P

P

P

++

+2)(

1 =P

P

CCRC+ ss

CCCC

R

RCs

P

P

P

++

+

2)1

1(

1

(2-2-3-16)

= Kf ss

s

p

z

+

+times

21ω

ω (2-2-3-17)

Kf = CC

RC

P

P

+ (2-2-3-18)

ωz = PRC

1 (2-2-3-19)

ωp = CCCC

R P

P +1 (2-2-3-20)






值約為 Cp的101~

51


約可從 30 ο ~45 ο


S

CCpSSCsFp

p

1

12

1

11

)(ω

ω

+

+sdot+

= (2-2-3-21)

其中CpRz

1=ω

CCpRCpC

p+

=1ω


29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











29

S

CCSSCMKI

sGp

p

VCOpump

1

21

12

2

1

11

)( ω

ω

+

+sdot+

sdot= (2-2-3-22)





)(1)()(

sGsGMsH

+bull

= (2-2-3-24)


c

p

z

c

ωω

ωωγ 1=equiv (2-2-3-25)

γω

γωω 1pzcK =bull== (2-2-3-26)


12

2

1 minus= γCC

cω =M


(2-2-3-27)


H(s)=γγ

γγj

jM+

minus+2

2 )1(2



30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











30





U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

Q

U17A

2

3

5

6

D

CLK

Q

QFin Fout




31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











31











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











32



33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











33




點





34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











34





35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











35




36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











36

3-1-4模擬結果



37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











37



38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











38




39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











39







40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











40


VCT

VDD_D

VDD_D



TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM9


VDD_D



VDD_D



VDD_D



TSMC_CM018RF_RESR1






VDD_D

VDD_D

TSMC_CM018RF_PMOSM3


I_ProbeI_Probe6


M4


PortVCTNum=4

PortDnNum=3

PortUPNum=2

PortVDD_DNum=1

VDD_D

TSMC_CM018RF_PMOSM2


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

VDD_D



VDD_D

VDD_D





M6


TSMC_CM018RF_NMOSM5


I_ProbeI_Probe4

I_ProbeI_Probe3

I_ProbeI_Probe1

I_ProbeI_Probe2

VDD_D

TSMC_CM018RF_PMOSM7


VDD_D

VDD_D





VDD_D








41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











41






42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











42





43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











43




44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











44




45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











45





46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











46





47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











47



A

VDD_D

CLK CLK

D

QbarB

Q

VDD_DCLK

VDD_D

CLK

TSMC_CM018RF_NMOSM9


TSMC_CM018RF_NMOSM8


TSMC_CM018RF_NMOSM6




TSMC_CM018RF_PMOSM4




TSMC_CM018RF_PMOSM2


TSMC_CM018RF_PMOSM3


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5




PortQbarNum=5

PortVDD_DNum=4

PortQNum=3

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1

A

VDD_D

CLK CLK

D

B

CLK

VDD_D

CLK

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_PMOSM4


TSMC_CM018RF_NMOSM9






TSMC_CM018RF_PMOSM3


TSMC_CM018RF_PMOSM2


PortQNum=3

PortQ2Num=6

TSMC_CM018RF_NMOSM1


TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM8


PortVDD_DNum=4

TSMC_CM018RF_NMOSM7


PortDNum=2

PortCLKNum=1


圖 320 TSPC DFF

48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











48

Q1Q3

Q2

VDD_D

PortQNum=3

VDD_D

TSPC_DFFX2

D Qbar

Q

VDD_D

CLK

TSPC_DFF_DX3

D

CLK

Q2 Q

VDD_DVDD_D

TSPC_DFF_DX1

D

CLK

Q2 Q

VDD_D

PortVDD_DNum=4

PortMCNum=2

PortinNum=1



49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











49

3-3-2模擬結果

(10除四電路MC=0



50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











50


Q1_A

VDD_D

Qx Q4Q1_B Qout

VDD_D

inv-dividerBX16

VDD_

D

O UTI N

nor3X8

VD

D_D

Y

ABC

VDD_D

TSPC_DFF2X11

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X10

D Qbar

Q

VDD_D

CLK

VDD_D

TSPC_DFF2X9

D Qbar

Q

VDD_D

CLK

VDD_D

inv-dividerAX15

VDD_

D

O UTI N

PortVDD_DNum=4

PortINNum=1

PortMCNum=5

VDD_Dnand2X7

VDD

YBA

PortOUTNum=2

PortModeNum=3


QoutIN

MCVDD_D

PortOUTNum=2

divider8tempX18

VDD_D

MC

IN

Mode

OUT

PortModeNum=3VDD_D

divider4_5X17

in Q

MC

VDD_D

PortINNum=1

PortVDD_DNum=4



51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











51

(5)除三十二



52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











52


pre_amp_out

IN

VDD_D

TranTran1


TRANSIENT

VARVAR1


EqnVar

VDD_D

divider32_33_disX3

Mode

OUT

VDD_D

IN

VDD_D

preampX2

VDD_D


V_DCSRC5Vdc=0 V



Si - Substrate

TSMC RF CMOS 018um

V_DCSRC1Vdc=pow e

OSCw PhNoiseOSC1


in B

VDD_D

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_PMOSM6


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM3



Cs=099 pFlt=30 um

TSMC_CM018RF_RESR1


TSMC_CM018RF_PMOSM2


TSMC_CM018RF_RESR2



TSMC_CM018RF_NMOSM4


PortVco_outNum=1

PortVDD_DNum=3



53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











53


(9)除三十二




54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











54

(10)除三十三



55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











55





CLK

shift14_2X1

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S11cVDD_D

2345678910111213

VtPulseDTSRC4


DT

VtBitSeqSRC5


t



Si - Substrate

TSMC RF CMOS 018um

TranTran1


TRANSIENT

VARVAR1


EqnVar

V_DCSRC1Vdc=powe

VDD_D


56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











56

clk

VDD_D

TGMX17

Ng

Pg

io2 io1

TGMX16

Ng

Pg

io2 io1

TGMX21

Ng

Pg

io2 io1

TGMX22

Ng

Pg

io2 io1

invX18

VD

D_

D

OUT IN

VDD_D

PortQbNum=4

PortQNum=3

invX23

VD

D_

D

O UTI N

VDD_D

invX24

VD

D_

D

OUT IN

VDD_D

invX14

VD

D_

D

O UTI N

VDD_D

PortDNum=1 inv

X19

VD

D_

D

O UTI N

VDD_D

PortCLKNum=2

invX20

VD

D_

D

O UTI N

VDD_D

invX13

VD

D_

D

O UTI N

VDD_D

invX9

VD

D_

D

O UTI N

PortVDD_DNum=5




57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











57



LatcCLK S13

S12 S7 O7S13 O13S11 S6 O6S10 S12 O12S9

D




Si - Substrate

TSMC RF CMOS 018um

latch7_2X2

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

latch7_2X4

O5

O7

O6

O4

O3

O2

O1D1

D2

D3

D4

D5

D6

D7

VDD_D

CLK

VtBitSeqSRC4


t

shift14_2X3

CLKS13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

VDD_D C

D S1

VARVAR2frequ=20Mhz

EqnVar

VtBitSeqSRC3


t

TranTran1


TRANSIENT

VtSineSRC2


VARVAR1

VDD_D=18VQ=18V

EqnVarV_DC

SRC1Vdc=Q

VDD_D

05101500

20

V

05101500

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V



58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











58

(2)latch 後的資料=10111100010111

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V

05101500

20

V

051015

00

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

-40-20020

-60

40

V

-40-20020

-60

40

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

00051015

-05

20

V

100 200 300 400 500 600 7000 800

00051015

-05

20

time nsec

V


59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











59


VDD_D

latch0904X7

VDD_D

CLK

D Q

VDD_D

latch0904X6

VDD_D

CLK

D Q

VDD_D

latch0904X8

VDD_D

CLK

D Q

VDD_D

latch0904X4

VDD_D

CLK

D Q

VDD_D

latch0904X3

VDD_D

CLK

D Q

VDD_D

latch0904X2

VDD_D

CLK

D Q

VDD_D

latch0904X1

VDD_D

CLK

D Q

PortO7Num=7

PortO6Num=6

PortO5Num=5

PortO4Num=4

PortO3Num=3

PortO2Num=2

PortO1Num=1

PortD7Num=8

PortD6Num=9

PortD5Num=10

PortD4Num=11

PortD3Num=12

PortD2Num=13

PortD1Num=14

PortVDD_DNum=16

PortCLKNum=15

CLK

VDD_D

invX1

VDD_

D

OUTIN

VDD_D

invX2

VDD_

D

OUTIN

VDD_D

PortCLKNum=4

PortDNum=3

PortVDD_DNum=2

PortQNum=1

TSMC_CM018RF_PMOSM4


VDD_D

TSMC_CM018RF_PMOSM3


VDD_D

TSMC_CM018RF_PMOSM1


VDD_D

TSMC_CM018RF_NMOSM6


TSMC_CM018RF_NMOSM2


TSMC_CM018RF_NMOSM5



60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











60


D1 D2 D4 D5D3 D6

Load

CLK CLK_d

OUT

q q1 q2 q3 q4

VDD_D

nand3X11

C

Y B

A

VDD_D VDD_D

Load

PortPOUTNum=4

PortD1Num=5

PortD2Num=6

PortD6Num=6

PortD5Num=5

PortD4Num=4

PortD3Num=3

TSPC_DFF_counterX20

Data

_ IN

Load

QCLK

VDD_D

QbarD

VDD_D

nand2_PC6X21

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X17

Nor2

VDD_

D

Y

A

B

VDD_D

nand2_PC6X22

Nand2Y

B

VDD

A

VDD_D

nor2_PC6X16

Nor2

VDD

_D

Y

A

B


Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX2

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX8

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

TSPC_DFF_counterX10

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

q5

TSPC_DFF_counterX7

Dat

a_I

N

Loa

d

QCLK

VDD_D

QbarD

VDD_D

PortVDD_DNum=3

PortCLK_INNum=1

PortLoadNum=2

nand2X4

VDD

YBA

CLK

VDD_D


VDD_D

D

CLKQ

TSMC_CM018RF_NMOSM6






PortLoadNum=7

PortData_INNum=6



DataIN_Bar



DataIN_Bar



VDD_DData_IN



Data_IN





Load_Bar







VDD_DLoad



VDD_D

Load

PortQbarNum=5

TSMC_CM018RF_NMOSM8


TSMC_CM018RF_PMOSM4


PortQNum=3





TSMC_CM018RF_PMOSM3


CLK

TSMC_CM018RF_NMOSM5


TSMC_CM018RF_NMOSM1


TSMC_CM018RF_PMOSM2


VDD_D



VDD_D

TSMC_CM018RF_NMOSM7


CLK

PortDNum=2

PortCLKNum=1

PortVDD_DNum=4



61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











61

Load

CLK

CLK_d

OUT

q q1 q2 q3 q4

VDD_DVDD_D

VDD_DVDD_D VDD_D

VDD_D

Load

VDD_D

TranTran1


TRANSIENT

V_DCSRC5Vdc=0 V

D1

V_DCSRC6Vdc=0 V

D2



Si - Substrate

TSMC RF CMOS 018um

VtBitSeqSRC12


t

Load

VtPulseDTSRC4


DT

V_DCSRC9Vdc=18 V

D3V_DCSRC11Vdc=0 V

D5V_DCSRC10Vdc=0 V

D6V_DCSRC8Vdc=18 V

D4VARVAR1


EqnVar

nand2_PC6X22

Nand2YB

VDD

A

nand2_PC6X21

Nand2YB

VDD

A

TSPC_DFF_counterX20

Data

_IN

Loa

d

QCLK

VDD_D

QbarD

D5

TSPC_DFF_counterX2

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D


Data

_IN

Loa

d

QCLK

VDD_D

QbarD

VDD_D

q5

D6

TSPC_DFF_counterX1

Data

_IN

Load

QCLK

VDD_D

QbarD

VDD_D

D1

nor2_PC6X17

Nor2

VDD_

D

YA

B

nor2_PC6X16

Nor2

VDD_

DY

A

B

nand3X11

C

Y B

A

VDD_D

nand2X4

VDD

YBA

V_DCSRC1Vdc=powe

VDD_D





140 160 180 200 220120 240

0

1

2

-1

3

time nsec

CLK

V

m1m2




timeltinv alid

OUTT1201E-7

coun9912009

in_time10000

time000 s

D1000 V

D2000 V

D318 V

D418 V

D5000 V

D6000 V





02 04 06 08 10 12 1400 16

00

05

10

15

-05

20

time usec

OU

T V

m3m4

Load

V



62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











62








Gate

12

Signal

63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











63


S1

12

S2

12

12

12

S1 S2


Very Good



Good Very Good

64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











64


　　　　　　




t1

Cp 較小t2


　　　　　

R2

Substrate

L1


bad Good

65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











65



變小了變小了

無法改變


( a )

　　 Ground

GroundM3

Via

M1

Via

M2

Via

M2M2

ViaSignal




66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











66

( b )

　　　

M2

P_Well

VDD

Via

M5

Via

Signal

P+

Via

P+n+

M4

n+

M1

P+

Via

Deep N-Well

gnd

M3

P+VDD

( c )

　　　

Signal1

Gnd

Signal2



67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











67


　　　

較好

Cap Cap


noise



68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











68



　　　　　

R and L會變小

L1

R2

C會變大

　　　　　

+

i

v

R

-ideeal Ground

L1 2

C


69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











69


　　　　

=

L1 2

L1 2

L1 2

L1 2


(差)

Cell3

Cell2

修正

Cell1

(佳)

Cell4

Cell3

Cell4

Cell3

Ground

Cell2

Ground

Cell2

Cell1

Cell1

Ground

Cell4



70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











70







M1 M2

D DS S

較淡

GImplant

較淡

G




D

G

Dummy Mos

S

M2M1 Dummy Mos

D S

G


71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











71


Double Guard ring

20um


須相反

ii30um以上

Double Guard

25 Guard ring

p+

p-sub

p+

p+

n+ n+

P-well

p+

p+P-well

p+

p+ 接 ground

n+Deep N-well

n+



72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











72


p+ p+

M4

Deep n-well

MIM CaP

p-well


p-well

n+ n+

Deep n-well

Poly


C1

C1

C2

C2

Dummy

Dummy

Dummy Dummy

Dummy

Dummy

DummyDummy

Dummy

Dummy

R1

R2 R1

R2

Poly

Metal(沒有對稱)

Dummy

Poly

Dummy

R1R1

R2

R2

R2R1


73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











73


C

Cs

CpL

1 2

R

RP

Deep n-well

MIM PIP

M4

p-well

A

B

B

A

沒有這麼簡單

AB

約C8(PIP CAP)A B


至少應視為


29 三明治電容

M5

M4

M3

M2

M1


VDD

GND

C bypass


更 stable

74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











74


　　　


　　　





S SD

G G

Guard ring



75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











75

S S SD D D


D S

G


Cell

PAD

PAD

Cell

PAD

PAD

Signal path



76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











76


Deep n-well

n+

M4

p+n+

p-well

p+p+p+

PADM5







差

好


77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











77


Top layer metal


2um

2um

10um

10um

10um






PAD

PAD

G

S

PAD

G

To Ground

To Ground

To Signal

100um

100um

100um

100um

100um


78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











78






S S S SD D D

AB

M1 M2 M3 M4 M5

M6


79

第五章結論






80

參考文獻











79

第五章結論






80

參考文獻











80

參考文獻











中 華 大 學 碩 士 論 文 -...

Documents

中華大學碩士論文 -...