© Copyright 2003 Nassda Corporation

OpenAccess 2.0 —A Nassda PerspectiveOpenAccess 2.0 —A Nassda Perspective

Graham Bell, Director of Marketing

©Nassda Corporation

Nanometer Verification FlowNanometer Verification Flow

File based flow in dotted arrows

Direct API and shared in-memory data flow in solid arrows

Nassda will partner with customers and vendors for a full-chip nanometer verification flow

File based flow in dotted arrows

Direct API and shared in-memory data flow in solid arrows

Nassda will partner with customers and vendors for a full-chip nanometer verification flow

OpenAccess DB

SchematicEditor

LayoutEditor

DRC / LVS

LayoutParasitic

Extraction

TransistorNetlist

Pre-layout & Post-layoutSimulation & Analysis

Waveforms, Analysis and Reports

DSPF / SPEF

©Nassda Corporation

Parasitic Detailed Model ViewParasitic Detailed Model View

Resistor Gnd Capacitor Coupling

Capacitor Inductor Mutual

Inductor Resistive

Inductor Diode

Resistor Gnd Capacitor Coupling

Capacitor Inductor Mutual

Inductor Resistive

Inductor Diode

©Nassda Corporation

Detailed Parasitic Modeling in OA 2.0Detailed Parasitic Modeling in OA 2.0

Fast creation of objects• 1.5 million parasitics per minute

Fast parasitic search• 2 seconds to build search table for 1 million

parasitics• Immediate search

Efficient database file size• 1 Million objects < 30Mb

Fast creation of objects• 1.5 million parasitics per minute

Fast parasitic search• 2 seconds to build search table for 1 million

parasitics• Immediate search

Efficient database file size• 1 Million objects < 30Mb

©Nassda Corporation

Detailed Parasitic Processing ResultsDetailed Parasitic Processing Results

No. of Devices

(M)Create

(s)Unload

(s)Load (s)

Find (s)

DB File Size (Mb)

0.1 3 0 2 0 2.80.5 18 1 10 1 13.81 39 3 22 2 27.92 87 6 53 6 57.15 306 15 198 25 144.4

©Nassda Corporation

Next StepsNext Steps

Live databases from customers Pre- and post-layout netlist Browsing and debug capabilities Partnering with others to demonstrate a

nanometer verification flow Future: post-layout design optimization

Live databases from customers Pre- and post-layout netlist Browsing and debug capabilities Partnering with others to demonstrate a

nanometer verification flow Future: post-layout design optimization