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Practical Oscilloscopes at Workaday Prices 15-MHz bandwidth, 2mV sensi t iv i ty , 3% accuracy, sweeps usab le to 20ns /d iv and an 8 x 10 cm CRT w i th in te rna l g ra t icu le wou ld normal ly c lass these osc i l loscopes as laboratory ins t ruments but they wi l l f ind wide use in the serv ice shop, techn ica l schoo l , and indust ry .

b y H a n s - G u n t e r H o h m a n n

ADVANCES IN INSTRUMENTATION nowadays do not always involve the bettering of previous

performance specifications but rather the bettering of performance/price ratios. Several new instru ments recently described here â€” a counter1, a digital voltmeter2, and a function generator3 â€” are of interest because their design made high-quality performance attainable for the technical school, service shop, and other low-budget operations, as well as for the well- equipped electronics laboratory.

Now joining the family of instruments available for restricted budgets are two new oscilloscopes. With a frequency range of dc to 1 5 MHz, these belong among the basic tools for everyday work in the lab, service shop and production area. Advances in tech nology made it possible to design these instruments with a better performance/price ratio than would have been possible 5 or 6 years ago.

One of the new oscilloscopes, Model 1220A (Fig. 1), is a dual-channel instrument and the other, Model 1221A (Fig. 2), is a lower-cost, single channel ver sion. These instruments have the performance needed for meeting a wide variety of applications (15 MHz bandwidth, 2 mV sensitivity, 3% accuracy, and cal ibrated sweep t imes from 0.5 s/div to 100 ns/div â€” even faster with the magnifier) and they have the most useful oscilloscope features (xio sweep magnifier, beam finder, X-Y display capabi lity, internal CRT graticule, TV sync separator). Above all, they have traditional HP reliability, and they have an affordable price.

Easy Operat ion Despite the minimal cost, the new oscilloscopes

have a number of operating conveniences that make them easy instruments to use. Considerable thought was devoted to achieving an uncluttered front-panel layout with controls placed so operation is easily un derstood. Automatic triggering assures that a base

line is present even in the absence of a signal or if the trigger level control is set beyond the range of the sig nal. Although the dual-channel Model 1220A oscil loscope operates in either a chopped or an alternate sweep mode when displaying two signals, the opera tor need not concern himself with making the choice. The choice is made by the TIME/DIV switch, which selects the alternate-sweep mode (display channel A on one sweep then channel B on the next) when the sweep rate is fast enough to avoid flicker. On the slower sweeps, 1 ms/cm or longer, the switch selects the chopped mode (the CRT spot switches back and forth from one waveform to the other at a 200-kHz rate to trace both waveforms on the same

C o v e r : A s n e w d e v e l o p - I ments br ing instrument costs down , TV se rv i ce shops j o i n t h e m a n y o t h e r b u d g e t - restr ic ted establ ishments that

l ean now ava i l t hemse lves o f qua l i t y i ns t r umen ts , l i ke t he M o d e l 1 2 2 0 A O s c i l l o s c o p e descr ibed here. Our thanks to

A l e o H o m e E l e c t r o n i c s S e r v i c e C e n t e r , S a n t a Clara, Cal i forn ia, and to technic ian J im Hagan for prov id ing the set t ing for th is photo.

In this Issue: Prac t i ca l Osc i l l oscopes a t Workaday Prices, by Hans-GÃ¼nter Hohmann . . . p a g e 2

A D a t a E r r o r A n a l y z e r f o r T r a c k i n g D o w n P r o b l e m s i n D a t a C o m m u n i c a t i o n s , b y J e f f r e y P . D u e r r

L a b o r a t o r y N o t e b o o k - S h a r p C u t - O f f F i l t e r s f o r T h a t A w k w a r d U H F B a n d p a g e 1 0

page 11

P R I N T E D I N U . S . A . HEWLETT-PACKARD COMPANY, 1974


F i g . 1 . N e w M o d e l 7 2 2 0 / 4 d u a l - channe l Osc i l l oscope has pe r fo r mance and qua l i t y usua l l y f ound o n l y i n l a b o r a t o r y i n s t r u m e n t s , yet it carries a down-to-earth price. S u i t a b l e f o r t h e g e n e r a l r u n o f a u d i o , v i d e o , l o g i c , a n d c o n t r o l measu remen ts , i t can a / so make low- level measurements.

sweep). Similarly, when triggering from a TV signal, the sweep triggers on either the horizontal or the ver tical sync pulses according to the setting of the TIME/ DIV switch.

But even with their operating simplicity, the in struments have the flexibility needed for a wide range of applications. The operator can select the source of sweep triggers (internal, external, ac line, TV) and he can select the point on the waveform where he would want triggering to occur (slope, le-

F i g . 2 . L o w e r - p r i c e d M o d e l 1 2 2 1 A O s c i l l o s c o p e i s i d e n t i c a l t o M o d e l 1 2 2 0 A e x c e p t t h a t i t h a s o n l y o n e v e r t i c a l channel.

vel). External signals can also be applied to the hori zontal deflection amplifiers for making X-Y plots or the Lissajous figures commonly used for phase-shift measurements. There is also a rear-panel Z-axis in put for modulating the CRT beam intensity.

These instruments also have reduced bulk and weight, weighing about 16 Ibs (8 kg) each.

Reducing Costs Obtaining reliability and versatility at low cost re

quired some departures from traditional practice. A major expense in producing a complicated instru ment like an oscilloscope is in assembly and test. The design of the new oscilloscopes eliminates several production steps both in fabricating parts and testing the circuits. For example, the cabinet is made of a molded, thermosetting resin (Fig. 3) that has a me chanical stability comparable to that of aluminum and that is widely used as a replacement for metal in automobiles and household appliances. It allows these oscilloscopes to be used in production areas, around process control equipment, and in other areas where ruggedness is needed. Because the cabin et can be molded in one operation with all mounting posts, bar stiffeners, access holes and the like in place, several manufacturing steps are eliminated. The cabinet is metallized on the inside surfaces where RF shielding is desired.

The internal chassis parts were designed in modu lar form for quick assembly by plugging together. This has the further advantage that the modules can


F i g . 3 . T h e m a j o r s t r u c t u r a l c o m p o n e n t i s m o l d e d w i t h a t he rmose t t i ng res in , g rea t l y r educ ing t he number o f ope ra t ions needed to manufacture the ins t rument .

be completely pre-tested by an automatic test system before final assembly. Most interconnections are made on printed-circuit boards with intermodule connections made by plug-in flat cables, significant ly reducing wiring and assembly time.

In some cases, costs were reduced by using pre mium components rather than the least expensive. For example, precision resistors and capacitors are used in the sweep timing circuits. It was therefore not necessary to include the trimmers that otherwise would be needed had lower cost components with looser tolerances been used. Hence, no time is taken at the test station for adjusting those variable com ponents that are no longer included.

Part of the cost reduction is simply a matter of ad vancing technology. High-performance solid-state components are now obtainable at lower prices and

the wide variety of available off-the-shelf integrated circuits make it possible to be almost extravagant in the use of functions. For instance, selection of most input sensitivity ranges is performed by switching the gain of the amplifiers. The input attenuator there fore needs only two positions and a straight-through position, reducing the number of adjustable fre quency-compensating capacitors needed.

The Overv iew A simplified block diagram of the new Model

1220A dual-channel oscilloscope is shown in Fig. 4. As can be seen, the general scheme of things is not much different from other dual-channel oscillo scopes. The Model 1221A single-channel version is similar except that it omits channel B and the circuits needed to multiplex two input channels into the single vertical CRT drive channel.

Solid-state circuits are used throughout. Power consumption is low, less than 40W, reducing inter nal heat rise with a consequent enhancement of relia bility. No vent holes are needed, lessening the prob lems associated with operating in adverse environ ments.

The CRT Although the design of any oscilloscope begins

with the cathode-ray tube, the CRT design has to take into account the circuits that may be used. The Hew lett-Packard Model 1310A large-screen Graphic Dis play had shown that substantial drive voltages at high frequencies can be obtained at moderate cost from solid-state circuits.4 This meant that the expan sion-mesh electrode â€” which had originally made high performance economically possible in all solid- state oscilloscope5 â€” would not be needed for the new

F i g . 4 . S i m p l i f i e d b l o c k d i a g r a m o f t h e M o d e l 1 2 2 0 A O s c i l l o s c o p e . T h e M o d e l 1 2 2 1 A i s s im i l a r excep t t ha t i t om i t s chan nel B and the chop/a l t contro l .


F i g . 5 . T h e c a t h o d e - r a y t u b e f o r t h e n e w o s c i l l o s c o p e s uses an uncompl icated s t ructure that reduces the number o f manufactur ing steps.

scopes. Furthermore, the drive voltage available meant that beam acceleration could be obtained en tirely in the electron gun, and a post-accelerating field would not be needed. All this added up to a re latively simple structure that eliminated several pro cessing steps.

One processing step that was not eliminated was insertion of the internal graticule. The black grati cule lines are deposited on the inner surface of the faceplate and fused onto the faceplate before the phosphor (P31) is deposited, placing the graticule in the same plane as the phosphor. This eliminates the parallax errors that otherwise occur when the grati cule is external to the CRT (Fig. 6). The improvement in reading accuracy is considered to be well worth the extra expense. Vertical deflection accuracy is within 3%, about as close as the eye can discern. This accuracy enables the oscilloscopes to be used as volt meters as well as waveform tracers.

Gain Switching A skeleton diagram of the input attenuator and

first preamplifier stage is shown in Fig. 7. Input impe dance on all ranges is 1 Mil in parallel with 30 pF.

The input signal goes to a high-impedance FET stage that is part of a differential amplifier. The other input to the amplifier is a dc balance voltage. The two in put FET's are mounted on the same substrate and thus have good thermal stability so once the balance voltage is set, it seldom needs readjustment. This made practical the instruments' high sensitivity (2mV/cm deflection factor).

The gain of the differential amplifier is changed by switching current sources Q5 and Q6. On the three most sensitive ranges, Q6 is turned on and Q5 off so emitter resistors Rl and R2 in parallel with R3 and R4 determine the gain of the amplifier. On all other ranges, Q5 is on and Q6 off so the smaller resistors are effectively cut out of the circuit by the decou pling diodes, reducing the amplifier gain by a factor of 10. As gain switching is performed by control vol tages, the electrical and mechanical design could be simplified.

The output of the first stage passes through a se cond differential stage (not shown) that has adjust able feedback to calibrate the gain of the vertical amplifier. From there, the signal goes to another stage that uses three sets of switched emitter resistors to give gains proportional to xi, x 2, and X5,

The signal then passes through a dc shifter to give vertical positioning control and a diode gate that mul tiplexes the two channels into a single channel (Fig. 4). The single channel goes to the CRT driver.

Economical Dr ive One leg of the CRT driver stage is shown in Fig. 8.

By dividing the 95V supply voltage across four tran sistors, lower-cost, low-voltage, high-frequency tran sistors may be used to obtain the 60V swing needed for each CRT deflection electrode.

The lower two transistors (QlO, Qll) are con nected as a cascode amplifier for better high fre quency response. The upper two (Q12, Q13), also in cascode, serve as a constant-current load for QlO and

Fig . 6 . P lac ing the CRT gra t icu le in the same plane as the phosphor assures h igh measurement accur a c y f r o m a n y v i e w i n g a n g l e b y el iminat ing paral lax.


+ 3.5V

G N D

X 0 . 1 A t t e n u a t o r

X 0 . 0 1 A t t e n u a t o r

- O U A i . o Â»-â€¢ â€” o â€” >

3 . 5 V

Overload Protection â€”

Diodes

(Balance)

Fig. at tenuator The input needs only two frequency-compensated attenuator sect ions. The other ranges amplifiers. obtained by using dc voltages to switch the gain of the amplifiers.

Qll. A constant-current source supplies more cur rent for charging the distributed load capacitance than a passive load would (at the same power dissipa tion), thus speeding up the transient response. ''How ever, the steady-state current flow normally estab lishes the maximum charge rate. To permit the steady-state current to be small, and hence keep power dissipation low, the current source in this cir cuit is modulated by the signal through capacitor Gil. High-speed transients passing through Cll to Q13 increase available current during fast transients to speed up the response of the amplifier. This con figuration thus gives fast transient response with low steady-state current.

The circuit shown in Fig. 8 supplies the drive vol tage for one CRT vertical deflection electrode and an identical amplifier drives the other electrode in the opposite phase. The horizontal drive amplifiers use a similar configuration but with higher-voltage transis tors operating from a +210V supply. This obtains the higher drive voltage needed for the horizontal deflec tion plates.

Logical Tr iggering Triggering is often a problem with oscilloscopes,

most of the problems arising because a new trigger may occur before the sweep circuits have fully re covered from the previous sweep. This results in an erratic display.

Basically, the new oscilloscopes' trigger and

+95V

Ver t i ca l Drive

Signa l

F i g . 8 . O u t p u t s t a g e u s e s a c a s c o d e d r i v e r ( 0 1 0 , 0 1 1 ) wi th a constant-current load (O12, 013). R10 establ ishes the steady-state current.


Fig. prevent sweeps and sweep generat ing c i rcu i t uses two holdof fs to prevent errat ic sweeps (see text).

sweep circuits follow established laboratory oscillo scope practice. The trigger signal is applied to a dif ferential amplifier and the polarity switch selects one of the inputs according to the trigger slope de sired (Fig. 4). The negative-going slope of the output switches a Schmitt trigger as it crosses the threshold- voltage level (Fig. 9). The resulting positive-going step at the output of the Schmitt circuit triggers the gate generator, a flip-flop. It in turn switches off the ramp capacitor discharge switch (Q20 in Fig. 9) and unblanks the CRT. Ramp capacitor C20 now charges through constant-current source Q21, generating the sweep voltage. Once triggered, the Q output of the gate generator holds off the Schmitt trigger by way of gate-inverter F.

When the sweep ramp reaches 10V, it triggers the cutoff Schmitt trigger circuit which in turn resets the gate generator flip-flop. To prevent retriggering while the ramp capacitor is discharging, the negative- going reset trigger is processed through NAND gates

C and D, which act as a sweep hold-off circuit. The output of gate D, which serves merely as an inverter, is fed back to gate C, clamping the output of gate D low until sweep holdoff capacitor C21 discharges suf ficiently to allow the gate D output to rise again. By holding the CLR input to the gate generator low while sweep holdoff capacitor C21 discharges, gate D pre vents a new sweep from being initiated during the holdoff period.

This raises a new problem â€” an erratic sweep could occur if a trigger arrives at the gate generator at the same time that the holdoff circuit is removing the CLR signal. An erratic sweep would result because the switching time of the gate generator would be differ ent in this case. Therefore, a trigger inhibit flip-flop and a signal delay have been added.

Normally, the low-to-high transition at the output of the input Schmitt trigger initially causes a high-to- low transition at the output of gate A, but the Schmitt transition is also delayed and inverted in in-


verters G so it causes the gate A output to go high again a few nanoseconds later. This delayed transi tion passes through gate B and triggers the gate gener ator, starting the sweep. Gate B was enabled by the trigger inhibit circuit which had been clocked by the Schmitt trigger a few nanoseconds earlier.

During the holdoff period, the triggering transi tion cannot pass gate B so long as the trigger inhibit flip-flop's Q output is held low by the holdoff signal at the CLR input. However, if a trigger arrives at the trigger inhibit flip-flop at the same time that the holdoff signal is being removed, the switching time of the Q output would be affected, but this causes no problem because the transition will be complete by the time the trigger arrives at gate B because of the de lays in the inverters G. Thus it is not possible for a trigger to arrive at the gate generator at the same time the holdoff signal is being removed. The result is so lidly stable triggering.

The total delay from trigger Schmitt transition to C R T u n b l a n k i n g a n d s w e e p s t a r t i s a b o u t 0.1/LAS.

Always a Base l ine In the absence of triggers, the sweep circuit be

comes self-triggering so the CRT trace is never lost â€” there is always a baseline. The trailing edge of the holdoff pulse starts a new sweep whenever the autotrigger circuit enables gate E.

The autotrigger circuit is a monostable multivibra tor. With no input triggers, the Q output of this cir cuit is high, allowing the output of gate E to go low on occurrence of the trailing edge of the sweep reset pulse. The negative-going step out of gate E is ap plied to the "preset" input of the gate generator, start ing a sweep. As long as gate E is enabled, sweeps will occur automatically.

An input trigger sets the autotrigger monostable multivibrator, blocking gate E. The monostable re sets itself 0.5 s after the last input trigger so in the ab sence of any input triggers, a baseline appears on the CRT. Whenever there are triggers, the monostable re mains in the set state and gate E is closed, preventing self-triggering of the sweeps.

Few Parts The two Schmitt triggers are on one integrated cir

cuit and the two flip-flops on another. Four of the gates are on one 1C and two more are on another (two other gates in this 1C are used elsewhere in the instru ment). All three amplifiers in the delay chain are on one 1C (three other amplifiers in the same 1C are used elsewhere). In other words, most of the trigger cir cuitry is implemented with six integrated circuits, and these are low-cost, standard TTL logic circuits, another example of how improved performance can now be obtained at lower cost.

TV Sync Because it is expected that these oscilloscopes will

find wide use in service shops, a TV sync separator is included (Fig. 4). This works along conventional lines in that it clamps to the peak value of a compo site TV waveform and clips off 60% of the waveform, leaving the TV sync pulses. These are cleaned up by applying them to a Schmitt trigger before sending them on to the sweep trigger circuit, or they are passed through a low-pass filter to obtain the vertical sync pulse, then shaped by a Schmitt trigger. The ver tical pulses are passed to a -H2 circuit, however, so that the resulting triggers occur on every second field, and hence at the same point in each frame for a clean display.

Economical Regulated High-Vol tage To assure a constant deflection factor and hence de

flection accuracy, the new oscilloscopes have a regu lator on the high-voltage supply for the accelerating electrodes. Recent practice has been to derive the ac celerating voltages by using an ultrasonic oscillator to drive a step-up transformer that supplies the high- voltage rectifier, making it possible to apply level control signals at low voltage levels to the oscillator.

The Models 1220A and 1221A have a high-voltage regulating system that does not require a separate os-

95V Power Supply 95V

( In tens i ty ) 2 - 5 M C R T

Gr id

F i g . 1 0 . H i g h - v o l t a g e p o w e r s u p p l y u s e s a r e g u l a t o r t h a t operates at low vol tage levels.


cillator to enable control with low voltages. As shown in the diagram of Fig. 10, the high voltage is obtained from a separate winding on the power trans former. The ground return, however, passes through a series-pass transistor Q30. The regulator amplifier causes the voltage drop across Q30 to change in the right amount to compensate for voltage changes in the high-voltage supply, as sensed at a tap on the re sistive divider, using the regulated 95V supply as a reference.

All the other voltages in the oscilloscope are regu lated too, a feature that costs relatively little to imple ment nowadays because of the availability of low- cost integrated-circuit regulators.

Acknowledgments The Models 1220A and 1221A Oscilloscopes re

sulted from the efforts of many people. Project leader was Ulrich Hubner, who also designed the high-voltage power supply and blanking circuits.

Stefan Traub developed the vertical amplifiers while Frank Rochlitzer and Horst Schweikardt designed the sweep and trigger circuits. Mechanical design was by Rudiger Plessner and Bruno Holzer with the assistance of Siegfried Dippon of the process engi neering group. S

References 1. IT. Band, H.J. Jekat, and E.G. May, "Lilliputian Measuring System Does Much, Costs Little," Hewlett- Packard Journal, August 1971. 2. A. Gookin, "Compactness and Versatility in a New Plug-Together Digital Multimeter," Hewlett-Packard Jour nal, August 1972. 3. E.H. Heflin, "Compact Function Generator with En hanced Capability/Cost Ratio," Hewlett-Packard Journal, July 1973. 4. J. Riggen and D. Fogg, "An Agile Graphic Display De vice," Hewlett-Packard Journal, April 1972. 5. F.G. Siegel, "A New DC-50+ MHz Transistorized Oscil loscope of Basic Instrumentation Character," Hewlett- Packard Journal, August 1966.

S P E C I F I C A T I O N S M o d e l s 1 2 2 0 A a n d 1 2 2 1 A O s c i l l o s c o p e s

M o d e s o t O p

EXTERNAL appro. 2 Hz to 15 MHz on aÃ§naU CM v p-p w mor* EXTERNAL INPUT RC appro* 1 msgorlm enr jMed by appro. 30 pF LINE trigoers on bne frequency TV SYNC MparMor tot - or - v ideo, requree 1 cm of v i r jeo Mgnal to t r igo*

CHANNEL A; CHANNEL B: cf iannera A and B cssplayed alternately on succes sive sweeps lAl t l . t r iggering t>y A channel cnannets A and B rkaplayed by swtcninc between criÃ¡rmete at appro. 200 kHz rate Â«itn bunking ounng switch- i n g ( C h o p ) , a u t o m a t i c s e l e c t i o n o f a l t e r n a t * o r c n o p m o d e C h o p , a t sweep speeds from 0 5 s.'cm to t ma. cm Alt. 0 5 mÂ«/cm to 0 1 *e*cm

Vert ic i l Ampl i f iers BANDWIDTH: 13 06 down from 50 kHz 6 div reference signal from a terminated

50-onrn sourcel DC-COUPLED dC lo 1 5 MHz AC-COUPLED rawer kmrl is appro. 2 Hz R ISETIME appro . 23 ns

D E F L E C T I O N F A C T O R RANGES from 2 mv cm to 10V cm in 1 2 5 sequence - 3s accuracy witn ver

rear n caktxated posi tron on tOmv cm to 1 0V cm ranges -5N on 2 and 5

VERNIER corvanuouaty vanatte between ranges attends maximum denecson factor to 25 V cm

INPUT RC: appro. I Ml ) shunter ] by appro. 30 pF INPUT COUPLING ac dc or gnd selectable GnrJ posi t ion crsconnecta s-gnai

Â«put and grounds arnc*t ier inpul

T i m e B a s e

> sequence :4*b accuracy * . rn

a m o r e t h a n 1 0 t i m e s M a u m u m

RANGES from 0 1 f i&cm to 0 5 s < Expander m cal ibrated posi t ion

E X P A N D E R c o n t i n u o u s l y e x p a n d * s w e e p h usaWe sweep speed is approx 20 ntvcm

SWEEP MODE sweep >s tnggered by intern* or externa! Signal BngM baaMkne (Hplayed -n abaence of mpm *grxat

15 MHz on signats causing 1 cm or mor* v INTERNAL appro . 2 Hz I I def tec ton

0 1 Â«semi LrsaMe arse as a row-pass finer L E V E L A N D S L O P E

INTERNAL al any point on positive or negative slope of ttarxayarf waveform E X T E R N A L c o n t i n u o u s l y v a r i a b l e f r o m - 0 5 V t o - 0 5 V o n * r t n * r s l o p e o f

t r igger waveform - 10 extends t r igger rang* to -5V lo -5V

E x t e r n a l H o r i z o n t a l I n p u t BANDWIDTH: dC lo t MHz COUPLING: dc

Continuous adfjÂ«ment between rang** by Expandttr INPUT RC: appro.! i megonm snunteO Oy approÂ» 30 pF K-V PHASE SÂ»Â«FT: 3 at lOOkHz

C a t h o d e - R a y T u b * a n d C o n t r o l s T Y P E P 3 1 a c c e l e r a t o r a p p r o x 2 k V a c c e l e r a t i n g p o t e n t i a l P 3 1 p h o s p n o r

Blu* kght f iner furnished P7 pnospnor and Â«moer hit,Â» m lieu oÃ P31 available GRATICULES â€¢ 10cm.niernalgrabcu.e.O 2 cm tubd.v.sÂ·or.Â· on maior horizontal

MAM FINDER: (Mums trac* 10 CRT Â» m regardeess ol setting ol horizontal and

I square wave for ad* jst -ng probe P f lOBC ADJUST: approx 3 V p*Mk . 2 Â«

INTENSITY MOOULATtON: * S V (TTL cotrvpatio.Â»! dc !o 1 MHz blanM tracÂ» OÃ any irntnsity mput R approx 1 k ohm

taMN.1 P O W E R : 1 0 0 1 2 0 2 2 0 V - 5 1 0 % 4 8 W 6 6 H z a p p r o . 3 5 I V WEIGHT

' 220A ne t . 16 ' ' 4 B (7 3 kg ) 1 22' A net, 1 5vÂ» ft (7 O hg}

m Â « P | S . . - U I x 4 U e H | . O P E R A T I N G E N V t R O M H C N T

TEMPERATURE 0 to -45 C rvon-opf t ra tma 10 75 ' C HUMIDITY to 95% rotaftv* hurrvdiry lo -40* C ALTITUDE 10 15.000 R (4600 m) VIBRATION vibratAd in thrM pianos lor 1 S minutÂ» aach wntn 0.010 in (0 25 mm)

excurs ion ,0 to 55 HZ

A c C * * Â « O f , a > * VOLTAGE DIVIDER PROBE Model 10013A 10- IO-1 vol tage div ider proba pro-

^aestOMll!rvputresistaix:.>inunl,x3e-y IQpF Ma-ntains luH 15MHz Dar-Owiolh C A M E R A A D A P T E R M o d e l 1 0 3 7 3 * C a m e r a A d a p t e r a l l o w s M o d e l 1 2 3 A

Camera lo be used FRONT PANEL COVER: Model 101 17A Front Panal Cover provides protection

and storage space tor proba*

i standard 19 m <*8 3 cm) rack requnng onty 8*Â» m (22 2 cm) of vertical space

PRICES IN U.S.A. Model 1 220A Dual Channel Oeolloac.ape. $695 Model 1221A Sngke Cnann.M Oecrtoecope. $575

P7 phospnor instead of P31 add S20 Model 10013A Voltage Divider Probe. $30 Model 10373A Camera Adapter $45 Hentatve) Model 101 <7A Front-panel Cover $20 Model 101 19A Rack Mounting Kit $65

MANUFACTURING DIVISION: Hewlet t -Packard GmbH Herrenberger Strasse 110 0-7030 BoMngen Wurt ternberg West Germanv COLORADO SPRINGS D IV IS ION i KM GaÃ±Ãan ol (he Gods Road Colorado Springs Colorado 80907

Hans-Gunter Hohmann Obta in ing a Dip lom Ingenieur in e lec t ron ics f rom the Technische Hochschule in Aachen, Germany, in 1967, Hans- GÃ¼nter Hohmann jo ined Hewlett-Packard GmbH short ly thereaf te r , s ta r t ing in research and deve lopment on ins t ru ments for acoust ic measurements He subsequent ly became pro jec t leader on severa l p roducts , inc lud ing the 8064A Rea l -T ime Aud io Spect rum Ana lyzer , and group leader fo r acoust ic products. He then became group leader for low-cost osc i l loscopes. Act ive in seasonal spor ts and other l ight a th le t ic events , Hans-Gunter a lso en joys read ing about h is to ry , both natura l and cu l tura l . S ince becoming a fa ther a year ago he does less o f the former and more o f the la t ter .


Laboratory Notebook Sharp Cut -of f F i l ters for That Awkward UHF Band

With discrete components too lossy, and cavities too bulky, the design of compact, sharp cut-off filters for the frequencies between 200 and 1000 MHz poses a problem.

In designing the Model 78101 A ECG Telemetry Receiver, * we faced this problem. Here was needed a filter that would remove an image frequency at 423 MHz without overly attenuating the carrier at 467 MHz (IF o/22 MHz and LO at 445 MHzJ. Ordinari ly this would be done with bandpass filters, several in series be ing required to get adequate rejection in this frequency band. Several filters in series, though, means considerable loss.

This problem was solved by using a transmission-line filter. This filter is not only effective, but it is also inexpensive.

Shown in the drawing below, the filter has two transmission- line fre that form a series-resonant trap for the image fre quency and a parallel-resonant passband for the carrier. Oper ation to as follows: Capacitor Cl tunes transmission-line Zl to series resonance at 423 MHz, thus effectively shorting out any

zi

Signal Input O Â »

Signa l F low Â»â€¢ o

signals at the image frequency. At higher frequencies, Zl is in ductive but transmission-line Z2, being shorter, is capacitive. C2 is tuned to resonate Z2 with Zl at 467 MHz so the carrier 'sees' a parallel resonant circuit, and passes with negligible loss.

As shown in the plot of frequency response, this design easi ly achieves more than 35 dB rejection of signals at the image fre quency in a 50Ã1 system, and more than 45 dB in a 200ÃÃ sys tem.

Design Execution There are a number of ways that such a circuit can be con

structed. Using lengths of coaxial cable was not entirely satis factory, however, because the fringing fields at the open ends of the cable where the capacitors are attached interacted with other filters nearby. â€¢Larscn et al, "An Effective ECG Telemetry System." Hewlett-Packard Journal. April 1972

- 1 0

o - 2 0

- 3 0

- 4 0

4 0 0 4 2 0 4 4 0 4 6 0 Frequency (MHz)

4 8 0 5 0 0

The design that evolved uses a long, narrow, sheet-metal box with an open side that is clamped to the ground plane of a printed-circuit board, forming the outer conductor of a coaxial line. The center conductor is a flat bar mounted at each end by a trimmer capacitor, as shown in the drawing. This forms a completely shielded, low-loss, air-dielectric transmission line.

Variable

Center Conductor

Capaci torV \

S igna l Conduc to r Printed Circuit Board

The single structure contains both sections of coaxial line. The signal lead, brought from the other side of the printed-cir cuit board through a hole in the ground plane, attaches to the center conductor at the point that divides the line into the ser ies-resonant and parallel-resonant sections. Actually, two sig nal leads are used, one for the input to the filter and one f or the output, eliminating a common impedance between input and output that would degrade performance. These leads attach on opposite sides of the center-conductor bar.

Two of these filters are used in the HP Model 78101A ECG Telemetry Receiver, one at the antenna input and one at the output of the two-stage tuned RF amplifier. Overall, an image frequency rejection of more than 100 dB is obtained.

James Larsen Richard Oilman Richard Tverdoch

Medical Electronics Division

10


A Data Error Analyzer for Tracking Down Problems in Data Communications A combined data generator and se l f -synchron iz ing receiver , th is new inst rument makes s ix d i f ferent measurements s imul taneously, help ing to p inpoint sources of t rouble in data communicat ions systems.

by Jeffrey R. Duerr

WITH THE GROWING USE of voice-communi cation channels for the transmission of digital

data, maintaining transmission reliability becomes of increasing concern.

Reliability can be enhanced by repeating messages or by transmitting at slower rates, which means less efficient use of facilities, or it can be enhanced by the use of error-correcting codes, which implies more complex equipment. On the other hand, increased re liability results from consistently maintaining opti mum system performance.

Making sure that optimum performance is main tained at all times has not been as simple and straight forward as one might surmise. The transmission of di gital data over any distance often involves sophisti cated equipment designed and manufactured by several different firms. The data may originate in a keyboard/display terminal or a computer made by one firm, be coupled to someone else's telephone sys tem by a modem made by still another firm, be trans mitted over the telephone system to another modem, and finally reach the receiving terminal or computer. The system is usually a combination of the efforts of a terminal manufacturer, a separate modem manufac

turer, a representative of the telephone company, and an in-house technician, none of whom are liable to be involved in a comprehensive view of the whole system.

Diagnostic programs that can show whether or not a system is operating satisfactorily have been writ ten, but interpreting results when the system does not operate properly is often hard to do, especially since those who understand the diagnostics may not have a good understanding of the various parts of the system.

For these reasons a new instrument was con ceived, an instrument sufficiently complex to fully exercise a sophisticated data link yet simple enough to be operated without detailed knowledge of the var ious parts of the system under test. Information pre sented by the instrument is unambiguous and easily interpreted to help track down the system compon ent at fault.

This instrument, Model 1645A Data Error Ana lyzer [Fig. 1) , is designed primarily to survey data communications systems that use voice-grade phone lines. It derives the information necessary to ap proach solutions to network problems by generating

F i g . 1 . M o d e l 1 6 4 5 A D a t a E r r o r A n a l y z e r g e n e r a t e s d i g i t a l t e s t pat terns in i ts t ransmit ter sect ion, t r ansmi t s t he pa t te rns th rough a c o m m u n i c a t i o n s c h a n n e l , a n d analyzes the rece ived pat terns in i ts rece iver sect ion by compar ing t h e m t o l o c a l l y - g e n e r a t e d p a t te rns I t ana lyzes the pat te rns s ix ways s imul taneously.

11


and interpreting digital patterns. It operates at 12 standard bit rates from 75 to 9600 bits/s but it can ana lyze synchronous systems at any bit rate up to 5 Mbits/s.

Mult ip le Tests The Analyzer generates pseudorandom bit se

quences for the data input. At the receiving end, it compares the received sequence to a locally gener ated sequence identical to the transmitted sequence. For end-to-end measurements, two instruments are used, but because the instrument contains both trans mitting and receiving circuits, only one is needed for loop-around tests.

The instrument makes several tests as it compares the received and locally generated sequences. Be sides measuring bit-error rate, which gives a mea sure of how well a digital transmission system is per forming, it measures several other parameters to help localize problems. The tests it performs are: â€¢ Bit error rate (BER), the ratio of number of in correct bits to number of bits received. It is fast be coming the preferred indicator of digital transmis sion quality. â€¢ Block error rate (BKER), the ratio of the number of data blocks that have errors to the number of blocks received. In the 1645A, each block has 1000 bits. When compared to bit-error rate, this indicates the distribution of error, that is, whether they are evenly distributed or whether they occur in bursts. â€¢ Skew, a comparison of the number of times that a "1" data bit is in error to the number of times that a "0" is in error. As measured by the new Data Error Analyzer, skew is the percentage of time that " 1 "s " are in error with respect to total errors. If the reading is not consistently near 50%, it indicates that the er rors may be pattern sensitive or that a decision thresh old somewhere in the system is improperly set. â€¢ Jitter, which is peak-to-peak timing variations in the received bits expressed as percent of nominal bit period. This can be the result of power line pickup or other interference with the timing of the system. â€¢ Total peak distortion, which is jitter plus bias, bias being a condition where marks, or "1". data bits, are consistently of a different length from the spaces, or "0" data bits, expressed as a percent of nominal bit period. It usually results from an improperly set threshold level and often results in skew. â€¢ Clock slip, the number of times that data jumped one bit period or more during the selected measure ment interval. It usually results from phase hits caused by path switching in the transmission link or it could be caused by slippage of the bit synchronizer in a synchronous modem. â€¢ A synch ronous sys tem Â¡s de f i ned as one where sys tem t im ing i s synch ron i zed to a mas te r c l ock i n t he t r ansm i t t i ng modem. A c l ock - recove ry c i r cu i t i n t he r ece i v i ng modem recons t i t u t es t he mas te r c l ock fo r the te rmina l . In an asynchronous sys tem, t im ing is cont ro l led by the te rmina l . eg . a te le typewr i te r

â€¢ Carrier loss, expressed as the number of times that input data faded during the measurement period. An output is provided so the number of bits lost can be totaled by an external counter to derive a measure of total lost time.

Organiz ing Test Resul ts Errors are accumulated for a time interval equiva

lent to the number of bits selected by a front-panel switch, which gives a choice of 102 to 109 bits in de cade steps. Tests may also be conducted in an AUTO mode that terminates a test on the next decade number of bits received after 98 errors have been counted. This assures valid (non-overranged) read ings when the instrument must be left unattended. Tests may also be started and stopped manually.

Single tests can be made, each in response to a front-panel switch, or tests may be repeated automati cally.

Regardless of the test selected for display during the measurement interval, front-panel indicators flash to show occurrence of each of four types of er rors (BER, BKER, clock slip, carrier loss). During the test, the display presents a continuously updated in dication of number of errors. Results of all tests are stored internally and at the conclusion of the meas urement interval, are made available for readout individually, as selected by a front-panel switch. This permits comparison of all values obtained on the same data, an aid in diagnosing problems. The re sults of any four tests are also printed sequentially if an external printer is used, permitting long-term, repetitive tests to be conducted unattended.

The instrument outputs a pulse once per received digital sequence, enabling oscilloscope viewing of the received sequence. It also outputs a pulse when ever an error is detected. One of the uses for this out put is to trigger an oscilloscope or logic analyzer when an error occurs, so the 16 bits that precede the error can be displayed. A 16-bit delay makes the last 16 bits available at a front-panel connector. This is useful in determining whether certain bit patterns cause the errors.

The time lapse between a data edge and an internal clock reference is available at a front-panel connec tor as an analog signal. This allows oscilloscope study of the cyclic nature of any jitter, often helping by providing clues as to the cause of the jitter, e.g., powerline pickup.

Where I t Goes In evaluating a system, the Data Error Analyzer

usually connects to the modem in place of the termin al. Accordingly, it generates and responds to the "handshake" signals used by modems. The display includes the necessary indicators (DATA SET READY,

12


CLEAR TO SEND) and a front-panel switch selects the control Status (DATA TERMINAL READY, REQUEST TO SEND). The switch also has a BACKWARD CHANNEL posi tion to allow tests involving the modem's supervi sory channel.

Interface is by way of a plug-in circuit card and connector (Fig. 2) that can be changed to meet the requirements of different interface standards. Nor mally, the instrument is supplied with a card that meets the logic-level and pin numbering require ments of EIA specification RS232C (CCITT V 24).

TTL-compatible inputs and outputs through BNC connectors on the front and rear panels facilitate use of the instrument in the lab and in other special situa tions.

Test Patterns A front-panel switch selects one of seven digital se

quences in NRZ (non-return to zero) format for trans mission and at the same time it sets the receiver cir cuits to the identical pattern. Four pseudorandom bit sequences (PRBS) are available (63, 511, 1047, and 1 048 575 bits) and there are three mark:space pat-

Fig. 2 . P lug- in modules in ter face the Data Error Analyzer to the system to be tes ted. The c i rcu i t card conver ts the ins t ru ment 's logic levels to those required by the system. An appro pr ia te connector is inc luded.

terns, a single mark (or "1") preceded by 1, 3, or 7 spaces ("0"), a greater range of test sequences than CCITT requirements. A DATA/DATA switch allows the complement of the selected pattern to be used, e.g. , a

Data Terminal Input

Transmit Output

Data Terminal Input

L o c a l M o d e m T e s t

â€” Data Link-

Transmit Outputs

Data Terminal Input

Interface Connector

v Receive ' Inputs

Interlace Connector

Full Directions End-to-end Test (Transmission and Receive in Both Directions Simultaneously.)

Data Terminal Input

\

- D a t a L i n k -

Transmit / O u t p u t s Data Terminal

â€¢ Input

Fu l l Duplex Loop Around Test Fig. 3. Some of the ways by which t h e D a t a E r r o r A n a l y z e r i s c o n nected to a system for tests.

13 © Copr. 1949-1998 Hewlett-Packard Co.

single space preceded by seven marks. The pattern selector switch also has a MARK posi

tion that simply places a dc level on the output. In end-to-end measurements, as long as the receiv

ing instrument is set to the same pattern and bit rate as the transmitting instrument, the receiver circuits automatically synchronize to the transmitted bit rate and automatically align the locally-generated bit se quence to that transmitted. The receiving circuits al so sense whether or not the polarity of the transmit ted bit sequence may have been inverted during transmission and perform a re-inversion if neces sary. Furthermore, the display circuits are autoranging. Thus, in routine tests the operator need concern himself only with setting the pattern and bit-rate switches and selecting the time duration of the test.

The instrument also has a LOOP mode that internal ly couples the transmitting circuits directly to the re ceiving circuits to verify that the instrument is operat ing correctly. One bit in each PRBS sequence can be made a deliberate error so the operation of the error- detecting circuits can be confirmed.

Some of the ways that the Data Error Analyzer may be connected to a system for tests is shown in Fig. 3. The manner in which it used to track down a prob lem is shown by the troubleshooting diagram of Fig. 4. Instrument Operat ion

A block diagram of the Data Error Analyzer is shown in Fig. 5. The pseudorandom digital se quences are generated in a shift register that has feed back through exclusive-OR gates to its input from se lected stages within the register. The mark:space se quences are generated by a counter that resets after a selected number of counts.

The clock frequency is divided down from a 5.76 MHz crystal oscillator to one of the standard modem clock frequencies, or it can be supplied by an exter nal source.

The selected sequence is supplied to the front panel through a TTL-level buffer and to the interface module that converts the sequence to levels suitable for the system to be tested. These are the only cir cuits concerned with the transmit function. All the others belong to the receiver.

The test sequence, after transmission through the unit or system under test, is brought into the instru ment either through a front-panel connector (not shown) or through the interface module. It is then dis tributed to the various circuits.

Receiver timing is controlled by the bit synchron izer. This has a stable 5.76 MHz oscillator that is phase-locked to the incoming data stream. The out put of the oscillator is divided down to derive the se lected clock frequency. It is not used, however, if an external clock is supplied.

Checking for Errors The incoming data is compared bit by bit to the out

put of a closed-loop shift register that is configured the same as the transmitting shift register. Whenever the two bit sequences differ, an error is counted.

Start

L o w

C h e c k m o d e m a u t o m a t i c c o n t r o l

c i rcui ts C h e c k

channe l

C h e c k T e r m i n a l s

Check Channe l

N o c h a n g e

C h e c k Channe l

C h e c k m o d e m b i t synchron izer

F i g . 4 . T r o u b l e s h o o t i n g d i a g r a m s h o w s h o w v a r i o u s t e s t resul ts are used to track down problems in a data communica t ions system.

14


From this, measurements of bit-error rate are de rived.

The incoming data is also compared to the output of an open-loop shift register that uses the same exclusive-OR gate configuration as the transmit register but which has no feedback connection. This regis ter is used for synchronizing the closed-loop shift register, for detecting clock slip, and for detecting the need for inverting the polarity of the incoming data stream, as will be described subsequently.

Block-error rate is measured by incrementing a counter every 1000 bits only if one or more errors had occurred during the 1000-bit block. Skew is mea sured by totaling all errors in one counter and only the 1's errors in a second counter. When the all-error counter overflows on a count of 100 (actually 98 be cause of internal logic), the contents of the 1's-only counter is latched out as the measure of skew.

F i g . 5 . B l o c k d i a g r a m o f M o d e l 1645A Data Error Analyzer .

The jitter/bias circuit compares the timing of the da ta edges to clock pulses derived from the phase- locked oscillator. From this comparison, values for jitter and total peak distortion are derived.

Carrier loss is detected by a counter that totals clock pulses between data transitions in the incom ing data stream. If more than 16 clock periods elapse without a data transition, it is assumed that a dropout occurred. For the long pseudorandom sequence, which has up to 20 bits without a transition, the deci sion threshold is set to 32. The error measuring cir cuits are inhibited when carrier loss is detected so as not to count false errors beyond those counted dur ing the detection period. The error count resumes, however, after the carrier returns so measurements are not aborted by a carrier loss.

The incoming data is also applied to a 16-bit shift register that serves for temporary storage. This

15


> â € ¢ 1 2 3

Open- loop Register

Received Data

Parallel Load

Closed-loop Register

r + ' 1 2 3

F e e d back

errors F i g . 6 . S i m p l i f i e d d i a g r a m i l l u s t r a t e s c o n c e p t b e h i n d c l o s e d - l o o p ( f e e d b a c k ) a n d o p e n - l o o p ( f eed fo rwa rd ) r eg i s te r s and how t h e t w o c o n f i g u r a t i o n s a r e u s e d in the Data Error Analyzer.

makes the 16 bits that precede an error available for examination.

Automat ic Sync For the error detection circuits to work, the closed-

loop shift register in the receiver must operate in synchronism with the shift register in the transmit ter. Frame sync, as it is called, is accomplished with the help of the open-loop shift register.

By way of explanation, the two shift register con figurations are shown in Fig. 6. The output of the closed-loop or feedback register is passed through an exclusive-OR gate and fed back into the input. There is an output from the exclusive-OR gate only when its inputs differ, so the output of the feedback register may or may not be fed back unaltered depending on the state of the other input to the gate. With proper choice of feedback taps (and precautions to assure that the shift register is never in the all-zero state), the shift register generates all possible combinations of N ones and zeros, except all zeros, where N is the number of states in the register.

If the same PRBS sequence generated by the feed back register were fed into the open-loop or feedfor ward register, the output of the feedforward register would be identical to its input, just as though it were supplying its own input. If, however, an error were injected into the input stream, it would cause two er rors at the output (once in each stage connected to the exclusive-OR gate). Open-loop shift registers therefore are not accurate indicators of bit-error rate, not only adding errors but also cancelling errors when there is more than one error in the register. However, frame sync with the data stream is auto matically achieved as soon as the data loads N bits into the register.

These properties are used to advantage in the new Data Error Analyzer. As shown in Fig. 6, the incom

ing bit stream is fed only to the feedforward register but it is compared to the outputs of both registers. The instrument, however, counts only the errors from the feedback register when measuring bit-error rate.

The comparison of the errors detected by the two registers determines the course of action within the instrument. At startup or following a clock slip, both registers will be out of frame sync, but within N bits the feedforward register will be loaded by the incom ing data and will stop generating errors. The feed back register, on the other hand, continues to gener ate errors.

Errors from the feedback register are totaled in a counter that is reset by errors from the feedforward re gister. If the counter overflows, indicating a great ex cess of feedback errors over feedforward errors, the overflow turns on a front-panel OUT OF LOCK indica tor and it initiates the transfer of the contents of the feedforward register, which now has valid data, into the feedback register. This is how the instrument achieves frame sync automatically.

Following start up, frame sync is required only when there has been a clock slip or when there has been a carrier loss. Each time frame sync is triggered, the clock slip totalizer is incremented one count.

This system is also used to detect the polarity of the data stream. If the data stream is inverted by the system under test, the output of the feedforward re gister will nevertheless have the proper polarity be cause both inputs to the exclusive-OR gate are in verted. The feedforward error detector would thus de tect errors 100% of the time. If errors are counted 100% of the time, the control circuits switch an in verter into the data path.

The autopolarity system is locked up during a test interval to prevent bursts of errors from triggering polarity inversion.

16


Data

Clock Edge

1 0 0 C l o c k Ji t ter Total Peak Output

Switch Control

Display

F i g . 7 . B l o c k d i a g r a m o f j i t t e r measurement c i rcu i t .

Ji t ter /Tota l Peak Measurement Jitter is measured by counting 100 x clock pulses

(100 x faster than the clock rate) from a data edge to the clock edge, which normally occurs half way through the data bit period. The difference between the lowest and highest values counted during the test interval is a measure of jitter.

This is carried out by the system diagrammed in Fig. 7. Upon sensing a positive-going data edge, the edge detector generates a start pulse for the con troller which in turn enables the interval counter to start totalizing 100 x clock pulses. The next clock edge stops the count, the exact count depending upon the position of the data edge with respect to the clock edge.

The count thus obtained is compared to the count in the low store register. If the count in the interval counter is the lesser of the two, it is loaded into the low store register in place of the count already there (the register was loaded with the first interval count at the beginning of a test).

The count in the interval counter is also compared to the sum of the counts in the low store and differ ence store registers. If the new count is greater than this sum, which represents the maximum count that has been received, the number in the low store reg ister is subtracted from the new count and the result is loaded into the difference store register.

The difference register now contains a number that corresponds to jitter directly in terms of percent

of clock period (100 counts equals 100%). The con tents of this register are displayed to give readings of jitter.

Total peak distortion (jitter plus bias) is measured by switching the edge detector to respond to both posit ive- and negative-going data edges. The number in the difference store thus reflects both the edge variations (jitter) and the relative positional dif ference between positive and negative edges (bias).

Fig. 8 . Osci l logram of analog waveform avai lab le at J ITTER/ TOTAL PEAK output . The nature of the waveform helps deter mine the cause of the j i t ter ( the waveform appears quant ized because i t i s made up o f d iscre te samples) .

17


An additional feature of the system is that the inter val counter contains continuously up-dated informa tion about the position of data edges with respect to the clock. When the data-edge-to-clock count is com plete, this information is converted to an analog vol tage and presented at a front-panel connector, gener ating a waveform that corresponds to the movement of data edges with respect to the clock. The resulting waveform can be viewed on an oscilloscope, as shown in Fig. 8, as an aid in determining the source of the jitter. This output (JITTER/TOTAL PEAK) is cali brated so 1 volt out represents 10% distortion.

When the Analyzer is measuring total peak distor tion, the oscilloscope's vertical deflection switches back and forth from the voltage corresponding to the positive-edge-to-clock interval to the voltage corre sponding to the negative-edge-to-clock interval, trac ing out two waveforms. The separation between waveforms is proportional to bias.

When the Analyzer is used with an external clock, the jitter measurement circuits are disabled since no 100X clock would then be available. Jitter in synch ronous systems, where an external clock most likely would be used, is usually less than 1% and is not a problem at the modem output. Jitter is primarily of concern with asynchronous systems where it may be as much as 20%.

Received Clock Compare Data Out

50

Data In

Single Sample

_ J I

Reconstructed Data

Analog Filtered Data Threshold

Fig. 9. Stat is t ica l f i l ter reduces ef fects of noise.

Statistical Filter A switchable filter is included in the incoming

data path. Usually, the filter in the modem cleans up a noisy signal. Whether or not it is performing satis factorily can be determined by comparing bit-error- rate measurements with the Analyzer 's f i l ter switched out to those made with the filter in.

The filter has to accommodate asynchronous bit frequencies from 75 to 9600 bps. As shown by the waveform in Fig. 9, analog filtering does not obtain reliable results so the filter used is a digital type that uses majority logic to decide whether a particular bit is a one or a zero. Each bit is sampled 100 times. Each time the sample is above the median threshold, it in crements a counter. At the end of the bit, the compara tor checks to see if 50 or more counts have accumu lated. If so, that data bit is classed as a one. Otherwise it is a zero.

When the filter is disabled, the incoming data is sampled once in the center of each bit to determine whether it is a one or a zero. Stable Clock

As mentioned previously, stable clock pulses are derived in the bit synchronizer. The heart of the bit synchronizer is a voltage-controlled 5.76 MHz LC oscillator that can be electrically tuned over a Â±0.5% range. As in the case of the transmitter, dividers de rive the various clock rates.

As shown in Fig. 10, the oscillator frequency is con trolled by a phase detector, an RS flip-flop that is trig gered on by a data edge and off by the next clock edge. This not only ensures that the instrument locks to the incoming bit rate, but it also places the clock edge midway in a bit period.

The output of the phase detector is averaged by a low-pass filter that is a compromise between stabi lity (long time constant) and acquisition speed. Loop bandwidth is 3 Hz, which is well below the rate of change of jitter and other parameters to be measured with reference to the clock, but which permits fast ac quisition from the operator's point of view.

The filter's time constant, however, would allow the oscillator to drift off frequency during the long pseudorandom sequence, which has long strings of bits in a row where no data edges occur. These would cause the phase detector to remain in either one of its two stable states, pulling the oscillator off frequency. Lengthening the filter's time constant to prevent drift from this source would seriously hamper acqui sition speed.

This problem was solved by using a switch that disconnects the phase detector output, allowing the filter capacitor to retain its present voltage until the switch closes again. The switch is controlled by a comparator circuit that monitors the internal states of the input feedback shift register and turns off the

18


Data Estimate

Multiple-bit Detector

FET Amplif ier

Data Edge

Received Data

Data Edge

Clock

Phase Detector Output

Switch

Filter Input

F ig . 10 . VCO con t ro l l oop .

switch whenever it detects that the register is about to output a long string of ones or zeros.

This arrangement reduces jitter during the long pseudorandom sequence from 15% or so to less than

1%. Another indication of the effectiveness of this cir cuit is that if the data input is removed, the oscillator remains in the correct phase for more than 5 seconds, equivalent to more than 375 bits at the slowest rate.

Autorange Control The traditional way of displaying bit-error rate is

as a number times 10 raised to some negative power (Axio~x). This method is used in the Data Error Analyzer. It was also desired to display the count in progress which would indicate how much of the test interval had elapsed. This is accomplished by using the exponent in the display to indicate the number of data bits received in decade steps. At the conclusion of the test, the display then shows the overall bit-er ror rate properly ranged.

The autoranging system is shown in Fig. 11. Clock pulses are totalized in nine decade counters con nected in tandem. The output of each of these counters goes to a selector. Initially, the output of the first decade is selected. As the clock count goes through 10, the first decade's output passes through the selector to increment the exponent counter. The exponent counter then shifts the selector to the next decade. This procedure repeats for each decade.

The count in the exponent counter is displayed continuously as the exponent. It is also compared to the number selected by the front-panel EXPONENT RANGE switch and when they become equal, the com parator stops the measurement.

In the automatic mode, the exponent counter re ceives a signal from the bit-error counter when 98 er rors have been counted. It then stops the measure ment when it receives the increment signal from the clock counter at the next decade change.

C l o c k P u l s e s

C o u n t e r s

1 0 1 1 0 2 1 0 3 1 0 " 1 0 5 1 0 6 1 0 7 1 0 " 1 0 '

Multiplex/Selector

Output

Exponent Display

98 Bit Errors

Exponent Select

Fig. 11. Autorange c i rcu i t se lec ts appropr iate exponent to terminate test interval automatical ly.

19


The exponent counter's output passes through the block subtract circuit before display. This circuit sub tracts 3 from the exponent count when the instru ment is displaying block error rate, giving block er-

S P E C I F I C A T I O N S HP Mode l 1645A Data Er ror Ana lyzer

Bit Rate I N T E R N A L T R A N S M I T T E R

BITS PER SECOND: selectable 75. 150. 200. 300. 600, 1200, 1800. 2400. 3600. 4800, 7200. 9600.

CRYSTAL FREQUENCY: 5 .76 MHz Â±0.03%; <0.01% j i t ter . INTERNAL RECEIVER (wi th b i t synchron izer )

RATE: dc to 9 .6 kbps . TIME TO LOOP LOCK: 2 s max at <0.01 error rate .

E X T E R N A L T R A N S M I T T E R a n d R E C E I V E R F R E Q U E N C Y : d c t o 5 M H z

Data Outputs/ Inputs R E A R P A N E L

INPUTS: backward channe l da ta , ex te rna l t r ansmi t t e r c l ock , and ex te rna l re ce iver c lock requ i re TTL leve l : max imum input 5 .5V.

OUTPUTS: bi ts lost and transmit ter sync provide TTL levels; internal t ransmit ter c lock p rov ides >2V in to 50 ohms.

MULT IP IN CONNECTORS: RS 232C connec to r and i n te r f ace l eve l s f o r i n t e r fac ing TTL s tandard commun ica t ions sys tems. P r in te r ou tpu t p rov ides TTL leve l outputs in BCD 8421 code.

F R O N T P A N E L INPUT: data Input requ i res TTL leve ls ; max imum Input , 5 .5V. OUTPUTS : receiver sync. 1 6 bits before error, and event provide TTL levels; data

output provides >2V Into 50 ohms. J i t ter / total peak analog output provides 1V p-p for 10% of p-p d is tor t ion f rom waveform caus ing j i t ter .

General DIMENSIONS: 5 .25 i n H . 16 .75 I n W. 11 .25 i n D (133 x 416 x 286 mm) . WEIGHT: 22 Ib (10 kg) . POWER: 115 or 230 Vac , 48 to 440 Hz , 150 VA max. O P E R A T I N G E N V I R O N M E N T

TEMPERATURE: 0Â°C to *55Â°C. HUMIDITY: to 95% relative humidity at 40Â°C. ALTITUDE: to 15,000 ft . (4600 m). V I B R A T I O N : v i b r a t e d i n t h r e e p l a n e s f o r 1 5 m i n u t e s e a c h w i t h 0 . 0 1 0 I n

(0.25 mm) excursion, 10 to 55 Hz. PRICE IN U.S.A. : 1645A. $2150. M A N U F A C T U R I N G D I V I S I O N : C O L O R A D O S P R I N G S D I V I S I O N

1900 Garden of the Gods Road Colorado Springs. Colorado 80907

ror rate directly.

Acknowledgments Appreciation is expressed to Al Knack for the inno

vative mechanical design, to Rick Vestal for many hours of patiently taking data on and with the Model 1645A, to Maxine Cheyney whose talents were essen tial to modularizing a complicated system, and to Eddie Donn whose creativeness was responsible for many of the basic ideas.

Jeffrey R. Duerr Joining HP in 1 970 after two years in aerospace communica t ions, Jeff Duerr init ial ly worked on the 6940A/1 900A program mable pulse generator system. Then, as project leader on the 1 645A Data Error Analyzer, he combined engineering with the market ing research needed for deve lop ing an in ternat iona l product . He is now a sales engineer in the Colorado Spr ings Division. A native of Cleveland, Jeff earned a BSEE degree at the University of Rochester and an MSEE degree in communi cations from the State University of New York at Buffalo (1 967). Jeff l ikes to spend weekends backpacking in summer and ski ing in w in ter and he en joys photography and b lue-grass banjo p ick ing a l l year around.

Hewle t t -Packard Company . 1501 Page Mi l l Road. Palo Al to , Cal i forn ia 94304

FEBRUARY 1974 Volume 25 â€¢ Number 6

Technica l In format ion f rom the Laborator ies o f Hewle t t -Packard Company

Hewle t t -Packard S A . . CH-1217 Meynn 2 Geneva. Swi tzer land

Yokogawa-Hewle t t -Packard L td . . Sh ibuya-Ku Tokyo 151 Japan

Editorial Director â€¢ Howard L. Roberts Managing Editor â€¢ Richard P. Dolan

Cont r ibut ing Ed i tors . Ross H . Snyder . Laurence D. Shergal is

Ar t D i rec tor . Photographer . Arv ld A . Dan ie lson Art Assistant â€¢ Sue M. Reinheimer

Administrative Services â€¢ Anne S. LoPresti European Production Manager â€¢ Kurt Hungerbuhler

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