© 2009, D. J. Foreman 1

Computer Organization

© 2009, D. J. Foreman 2

Basic Architecture ReviewVon Neumann

■ Distinct single-ALU & single-Control■ Fixed circuitry

Non-von Neumann■ Various changes

• Multiple ALUs

• Merged ALU and Control

• Alternatives to ALU

© 2009, D. J. Foreman 3

Timing Cycle – timing in a computer comes from a

master clock controlled by a crystal oscillator Clock ticks (million cycles / sec) Frequency = 1/period and Period = 1/frequency Let’s use 10 MHz to make the arithmetic easier

■ 10 MHz = 10 x 106 Hz = 107 Hz■ Period is 1/10*1 / 106 = .1 µsec = 10 - 7 seconds

Terms■ Giga = 109 and nano = 10-9

■ Mega = 106 and micro = 10-6

© 2009, D. J. Foreman 4

Storage Speed HierarchyOn the Motherboard

■ CPU Registers – extremely fast■ Cache (CPU Internal) – very fast■ Cache (External) – fast■ Main Memory - slow

External■ Flash disk – 0 latency■ Magnetic Disks – high latency■ Optical Disk – very high latency■ Magnetic Tapes – seq'l, extremely high latency

© 2009, D. J. Foreman 5

Instruction Processing1. Fetch – get instruction from RAM2. Decode - h/w determines operation from

bit pattern of first (or more) byte(s)3. Obtain operand data

■ From Registers or RAM■ Into ALU

4. Execute (perform the operation)5. Store results back to RAM6. Update Instruction Counter

■ (sometimes called Program Counter)

© 2009, D. J. Foreman 6

Device-Controller/Software Relationship

Application

API

O/S

Device driver

Devicecontroller

Device

S/W

H/W

© 2009, D. J. Foreman 7

Device Controller InterfaceData widthCommands

■ Read■ Write■ Seek

Status codes■ Busy■ Error■ Done■ Ready

© 2009, D. J. Foreman 8

I/O OperationsController manages deviceDevices are MUCH slower than CPUCPU can process while device runsNeed to know when done

■ Polling (continual testing for "done")■ Special h/w for notification – interrupt flag

• One bit in CPU (explore: 1 per device)

• Turned on by device controller

• Turned off by O/S

• No "race" conditions

© 2009, D. J. Foreman 9

Interrupt Handling SequenceController (atomic action)

■ turns on flag■ Sets code indicating which device

H/W (atomic action)■ Switches to privileged mode■ interrupts off■ Memory protection off■ Sets IC to general interrupt handler in O/S

O/S■ Saves registers (NOT part of atomic actions)

© 2009, D. J. Foreman 10

Kernel S/W Interrupt HandlingSave (uses multiple machine cycles)

■ Registers■ Stack

Determine interrupt cause■ I/O, error, service request, external signal

Jump to proper interrupt-handler

© 2009, D. J. Foreman 11

Kernel Returns to the UserRestores user's state & values

■ User mode (kernel/user)■ Registers■ Stack

Load IC with interrupts enabled• Allows new interrupt before switching

(return to processing on previous slide)

© 2009, D. J. Foreman 12

Trap or System CallInstruction

Atomic operation■ Causes an interrupt (type=service request)■ It is NOT a “call” as if to a function

Common service request handler■ Uses code to select address in trap table■ Trap table contains addresses of specific

programs for specific request

© 2009, D. J. Foreman 13

Traps or Kernel “Calls”Examples

■ cout << x;■ seek (device, position);■ X=ftime();

User functions expand into assembly code for a "trap" or "svc" instruction

"trap" causes a H/W switch to the kernelKernel performs op and returns to user

© 2009, D. J. Foreman 14

System call example

fork (My_fork_loc);

{ ●

●

●

trap (K_FORK,

*My_fork_loc);

}

My_fork_loc:…;

*Do_fork

Do_fork(loc){ ●

●

start_process (loc);

mode=0;

return;

}

Traptable

*Do_fork

User space Kernel space

K_fork is entry # for "FORK"Kernel space

© 2009, D. J. Foreman 15

Instruction Processing with Interrupts

fetch executeInterruptsallowed?

No

yesprevious

instInterruptpending?

No

processinterrupt

yes

© 2009, D. J. Foreman 16

Direct Memory Addressing (DMA)Allows device controller to access RAM

w/o going through the CPU

Increases throughput

Reduces interrupt handling

© 2009, D. J. Foreman 17

Device addressingTwo methods shown in text:

■ Conventional• External to RAM• Limited only by size of device address

■ Memory-mapped devices• Uses reserved part of RAM• Limited by reserved space

Third method – used in some mainframes■ Channels – addresses 00-0f (1 byte)■ Sub-channels – addresses 00-ff (2nd byte)■ Total of 4096 independent devices (0000-0fff)

© 2009, D. J. Foreman 18

Loader ProcessingFind the executable file

Resolve relative addresses within program to actual locations

Connect DLL's to procedure call structure■ Shared collection of programs & entry points

© 2009, D. J. Foreman 19

Pipelined Instructions

Fetch Decode Execute Store

Fetch Decode Execute Store

Fetch Decode Execute Store

Done DoneDonet1, etct0

© 2009, D. J. Foreman 20

Software, Firmware, HardwareSoftware

■ Programs you can install/remove/transport to another computer which are stored on disk, CD, etc and run from within RAM

Firmware■ Programs usually installed only by chip maker

and which run from within ROM■ May be upgraded by user (depends on chip)

Hardware■ The physical components of the system

Hex address IBM z/390 memory content0 IPL PSW or Restart PSW8 IPL CCW1 or Restart old PSW10 IPL CCW218 External Old PSW20 Supervisor Call Old PSW28 Program Check Old PSW30 Machine Check Old PSW38 I/O Old PSW58 External New PSW60 Supervisor Call New PSW68 Program Check New PSW70 Machine Check New PSW78 I/O New PSW80 External interrupt data88 (4 bytes) SVC interruption data: 13-14= ILC,

16-31= interruption code (SVC #)

paired

paired

© 2009, D. J. Foreman 21

© 2009, D. J. Foreman 22

PC-bootable disk layout0x00-0x02 jump inst to 0x1e0x03-0x0a PC manufacturer name0x0b-0x0c sectors/cluster0x0d-0x0f reserved for boot record0x10-0x10 # of FAT's0x11-0x12 # root directory entries0x13-0x14 # logical sectors0x15-0x15 media descriptor0x16-0x17 sectors/FAT0x18-0x19 sectors/track0x1a-0x10b # surfaces (heads)0x1c-0x1d # hidden sectors0x1e-… boot program