© 2003 xilinx, inc. all rights reserved power estimation

© 2003 Xilinx, Inc. All Rights Reserved

Power Estimation

Power Estimation - 18 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

After completing this module, you will be able to:

Objectives

• List the three phases of the design cycle where power calculations can be performed

• Estimate power consumption by using the Xilinx Power Estimator worksheet

• Estimate power consumption by using the XPower utility


Outline

• Introduction• Power Estimator Worksheet• Using XPower Software• Summary


Performance (MHz)P

MA

X

Package PowerLimit

Real World DesignPower Consumption

High Density

LowDensity

Power Consumption Overview

• As devices get larger and faster, power consumption goes up

• First generation FPGAs had:– Lower performance– Lower power requirements– No package power concerns

• Today's FPGAs have:– Much higher performance– Higher power requirements– Package power limit concerns exist


Power Consumption Concerns

• High-speed and high-density designs require more power, leading to higher junction temperatures

• Package thermal limits exist– 125oC for plastic– 150oC for ceramic

• Power directly limits:– System performance– Design density– Package options– Device reliability


Estimating Power Consumption

• Estimating power consumption is a complex calculation– Power consumption of an FPGA is almost exclusively dynamic– Power consumption is design dependent and is affected by:

• Output loading• System performance (switching frequency)• Design density (number of interconnects)• Design activity (percent of interconnects switching)• Logic block and interconnect structure• Supply voltage


Estimating Power Consumption

• Power calculations can be performed at three distinct phases of the design cycle

– Concept phase: A rough estimate of power can be calculated based on estimates of logic capacity and activity rates

• Use the Xilinx Power Estimator worksheets on the Web– Design phase: Power can be calculated more accurately based on detailed

information about how the design is implemented in the FPGA• Use XPower™ software

– System integration phase: Power is calculated in a lab environment• Use actual instrumentation

• Accurate power calculation at an early stage in the design cycle will result in fewer problems later


Activity Rates

• Accurate activity rates (A.K.A. toggle rates)are required for meaningful power calculations

• Clocks and input signals have an absolute frequency• Synchronous logic nets use a percentage activity rate

– 100-percent indicates that a net is expected to change state on every clock cycle

– Allows you to adjust the primary clock frequency and see the effect on power consumption

– Can be set globally to an average activity rate, on groups or individual nets• Logic elements also use a percentage activity rate

– Based on the activity rate of output signals of the logic element– Logic elements have capacitance


Outline



Xilinx Power Estimator

• Excel worksheets with power estimation formulas built in– Enter design data in white boxes– Power estimates are shown in red boxes

• Worksheet sections:– Summary (device totals)– Quiescent power– CLB logic– Block RAMs– Block multipliers– DCMs– I/O pins


Power Estimator Worksheet:Summary and Quiescent


Power Estimator Worksheet:CLB, RAM, and Multipliers


Power Estimator Worksheet:DCM and I/O


Outline



What is the XPower Software?

• A utility for estimating the power consumption and junction temperature of FPGA and CPLD devices

• Reads an implemented design (NCD file) and timing constraint data• You supply activity rates:

– Clock frequencies– Activity rates for nets, logic elements, and output pins– Capacitive loading on output pins– Power supply data and ambient temperature– Detailed design activity data from simulation (VCD file)

• XPower calculates total average power consumption and generates a report


Running XPower

• Expand Implement Design Place & Route

• Double-click Analyze Power to launch XPower in interactive mode

• Use the Generate Power Data process to create reports using VCD files or TCL scripts


XPower GUI


XPower Reports

• ASCII (design.pwr) or HTML (design.html) formats– Select format in the Edit Preferences dialog

• Summary of power consumption• Detailed breakdown of power usage (optional)• Thermal data

– Junction temperature– Theta J-A for chosen package


XPower Summary ReportPower summary: I(mA) P(mW)----------------------------------------------------------------Total estimated power consumption: 807 Vccint 1.50V: 160 240 Vccaux 3.30V: 100 330 Vcco33 3.30V: 72 237(Additional breakdowns deleted)

Thermal summary:---------------------------------------------------------------- Estimated junction temperature: 46C 250 LFM 43C... Ambient temp: 25C Case temp: 43C Theta J-A range: 26 - 26C/W

Decoupling Network Summary: Cap Range (uF) #----------------------------------------------------------------Capacitor Recommendations: Total for Vccint : 8 470.0 - 1000.0 : 1 0.0470 - 0.2200 : 1 0.0100 - 0.0470 : 2 0.0010 - 0.0047 : 4(Other power supplies deleted)


XPower Detailed Report

Power details:-------------------------------------------------------------------------------Clocks: Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)-------------------------------------------------------------------------------rd_clk_inst/IBUFG Logic: rd_clk_inst/CLKDLL 40 166.7 10.0 15.0 rd_clk_inst/BUFG 6 166.7 1.5 2.3 Nets: rd_clk_dll 364 231 166.7 58.0 86.9 rd_clk_inst/CLK0 1 0 166.7 0.0 ~0.0 rd_clk_inst/IBUFG 1 0 166.7 0.0 ~0.0. . .-------------------------------------------------------------------------------Outputs: Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)-------------------------------------------------------------------------------Vcco33 final_data_obuf[0] 35000 13 5.0 0.8 2.6. . .-------------------------------------------------------------------------------Logic: Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)-------------------------------------------------------------------------------cha_fifo_inst/.../FIFO_BRAM.A 32 6.0 0.3 0.4. . .


Outline



Review Questions

• Power estimations are typically made during which three phases of the design cycle?

• What methods can be used to enter activity rates into the XPower tool?


Answers

• Power estimations are typically made during which three phases of the design cycle?

– Concept phase: Rough estimate based on estimated logic capacity and activity rates

– Design phase: More accurate estimate based on information about how the design is implemented in the FPGA

– System integration phase: Actual power usage is measured in a lab environment

• What methods can be used to enter activity rates into the XPower tool?– Load a VCD file– Manually enter activity rates


Summary

• Power calculations can be performed at three distinct phases of the design cycle:

– Concept phase: (Xilinx Power Estimator Worksheet)– Design phase: (XPower software)– System integration phase: (lab measurements)

• Accurate power calculation at an early stage in the design cycle will result in fewer problems later

• XPower software is a utility for estimating the power consumption and the junction temperature of FPGA and CPLD devices

• XPower software uses activity rates to calculate total average power consumption


Where Can I Learn More?

• Software manuals: Development System Reference Guide– XPower chapter

• Online Help from XPower GUI• Application Notes:

– XAPP158: “Powering Xilinx FPGAs”– XAPP415: “Packaging Thermal Management”

• Power Estimators (Excel spreadsheets): – http://www.xilinx.com/ise/power_tools/spreadsheet_pt.htm

© 2003 xilinx, inc. all rights reserved power estimation

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